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2016-07-30chromeos mainboards: remove chromeos.aslAaron Durbin
Use the ACPI generator for creating the Chrome OS gpio package. Each mainboard has its own list of Chrome OS gpios that are fed into a helper to generate the ACPI external OIPG package. Additionally, the common chromeos.asl is now conditionally included based on CONFIG_CHROMEOS. Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-25apollolake: Move CHROMEOS config to SoCFurquan Shaikh
All the mainboards share the same config options for CHROMEOS. Instead of duplicating those in every mainboard, move the CHROMEOS config to SoC and make it dependent on MAINBOARD_HAS_CHROMEOS. BUG=chrome-os-partner:55431 Change-Id: I2d54ff6beac9fca7596a8f104e3c1447cada5c05 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15821 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-25intel/amenia: Add chromeos.c to verstageFurquan Shaikh
BUG=chrome-os-partner:55431 Change-Id: I94fe54c12d7438a71f81a9053cc9785c0aa1e6cf Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15823 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-22intel/amenia: Write protect GPIO relative to bank offsetsselvar2
Update the write protect GPIO reported in ACPI to GPIO_75. Also update the controller ID to "INT3452:01" which will point at the goldmont device and includes write protect GPIO. BUG=none BRANCH=none TEST=verify crossystem output for wpsw_cur. Change-Id: Id6b172e289976072836746c1814e0300544a06cb Signed-off-by: sselvar2 <susendra.selvaraj@intel.com> Reviewed-on: https://coreboot.intel.com/7771 Reviewed-by: Sparry, Icarus W <icarus.w.sparry@intel.com> Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15496 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19intel/amenia: Add DA7219 support in acpiHarsha Priya
Add DA7219 support in acpi. DA7219 has advanced accessory detection functionality. Also add DA7219's AAD as a ACPI data node. Change-Id: I979275cb2ab1e593ff1e5d360bea83b843e45021 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15625 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-15intel/amenia: Add wake-up from lid openShaunak Saha
This patch adds support to wake up from S3 on lidopen. mainboard.asl has the _PRW defined for the wakeup support in S3. BUG = chrome-os-partner:53992 TEST = Platform wakes up from S3 on lidopen. Change-Id: I48b456baf5f7e1c2f28454fa66bb90ad761bb103 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15618 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15soc/intel/apollolake: Consolidate ISH enablingAndrey Petrov
Since the Integrated Sensor Hub can be disabled through devicetree.cb as a PCI device, there is no need for a separate register variable. Remove handling the register and update mainboards' devicetrees. Also keep ISH disabled on both Reef and Amenia. Change-Id: I90dbf57b353ae1b80295ecf39877b10ed21de146 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15710 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15mainboards/apollolake: use common Chrome EC SMI helpersAaron Durbin
Reduce duplicate code by using the Chrome EC SMI helper functions. BUG=chrome-os-partner:54977 Change-Id: Iba2ca7185ad7f0566858ce99f5ad8325ecc243cf Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15687 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
2016-07-15mainboards: align on using ACPI_Sx definitionsAaron Durbin
The mainboard_smi_sleep() function takes ACPI sleep values of the form S3=3, S4=4, S5=5, etc. All the chipsets ensure that whatever hardware PM1 control register values are used the interface to the mainboard is the same. Move all the SMI handlers in the mainboard directory to not open code the literal values 3 and 5 for ACPI_S3 and ACPI_S5. There were a few notable exceptions where the code was attempting to use the hardware values and not the common translated values. The few users of SLEEP_STATE_X were updated to align with ACPI_SX as those defines are already equal. The removal of SLEEP_STATE_X defines is forthcoming in a subsequent patch. BUG=chrome-os-partner:54977 Change-Id: I76592c9107778cce5995e5af764760453f54dc50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15664 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-14intel/amenia: Add mainboard SMI handlerShaunak Saha
This patch adds a mainboard SMI handler file which has functions to set proper Wake mask before going to sleep so that system can wake up on lidopen, key press etc. Also SCI mask is set on boot which will enable timely update of battery UI on charger connect/disconnect. BUG = chrome-os-partner:53992 TEST = Amenia platform wakes from S3 on lidopen, key press and also sysfs entry for AC is updated on charger connect/disconnect. Change-Id: If3dc6924c51c228241b7a647566b97398326ec0e Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15616 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-14intel/amenia: Add Maxim98357a supportHarsha Priya
Adds Maxim98357a support for amenia using the generic driver in drivers/generic/max98357 Change-Id: I333d4e810e42309ac76dd90c19f05cf3e3a518f1 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15624 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-14intel/amenia: Update gpio config for audioHarsha Priya
This changelist updates gpio config for speaker SDMODE pin. It disables speaker by default. Audio kernel is expected to enable this when audio rendering starts. Change-Id: Id33ad29e637bf1fe6b02e8a4b0fd9e220e8983b6 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15623 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-13mainboard/intel/amenia: use new gpio interrupt macrosAaron Durbin
Utilize the new interrupt macros in order to specify correct polarity of the gpio interupts. Some of the interrupts were working by catching the opposite edge of the asserted interrupt. BUG=chrome-os-partner:54977 Change-Id: I55bee2c4363cfdbf340a4d5b3574b34152e0069c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15646 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-13intel/amenia: Disable unused PCIe portsJagadish Krishnamoorthy
Disable PCIe A0, A1, A2, A3, B1 ports. Enable B0 port which is used for wifi. BUG=chrome-os-partner:54288 BRANCH=None TEST=lspci should show only PCIe B0 device Change-Id: I266d6eb7ddd56888f6b07b59681c2d9f0a6c0a9e Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15599 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-12intel/amenia: Add GPE routing settingsShaunak Saha
This patch sets the devicetree for gpe0_dw configuration and also configures the GPIO lines for SCI. EC_SCI_GPI is configured to proper value. BUG = chrome-os-partner:53438 TEST = Toggle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupt Change-Id: I3ae9ef7c6a3c8688bcb6cb4c73f5618e7cde342c Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15325 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-07board/intel/amenia: Enable LPSS S0ixHannah Williams
This setting will enable S0ix for LPSS Change-Id: Ie07cb8437d0cee61a03638aa980fd3322fef0c4e Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15056 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-01mainboard/intel/amenia: add NHLT supportSaurabh Satija
Add ACPI NHLT table generation that the current hardware supports as well select the hardware used on the board. Amenia has support for two audio codecs, Dialog for headsets and Maxim for speakers. Change-Id: Iaba9ec81ffb4f128f2e4413dec5174d9ecb856c9 Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Reviewed-on: https://review.coreboot.org/15024 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-28intel/amenia: Configure unused PadsJagadish Krishnamoorthy
Configure unused Pads as NC and sort the pads according to the gpio community. Move the pad configurations from mainboard to gpio.h BUG=none TEST=Boot to OS and check all functionalities. Change-Id: I8e9eeebf5d75c71c521649c72612c06f3fa43701 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15327 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-27intel/amenia: disable unused devicesJagadish Krishnamoorthy
BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I486a4c5e8970047477068e22b799d06caea03330 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15338 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22mainboard: Remove use of IFD_BIOS_START/IFD_BIOS_ENDFurquan Shaikh
BUG=chrome-os-partner:54563 Change-Id: If07710333cbb84ce70d6d4fa40602a74c898c08a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15293 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-09intel/amenia: Program EMMC dll settingZhao, Lijian
EMMC TX DATA Control needs to be programmed to 0x1A1A to make amenia system can run stable on EMMC with HS400 mode. Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15092 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08mainboard/intel/amenia: Enable VIRT_DEV_SWITCHRavi Sarawadi
Enable virtual dev switch config. BUG=None TEST= On Dev FW screen, press SPACE key to boot to normal mode Change-Id: I0fba36ed85025e4d17da106978dcc88497afee09 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/15080 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08Intel/amenia: Make the device address more readableZhao, Lijian
Use central header file to include device address and interrupt line to avoid confusion. Change-Id: I9560031d9f6e12c665c8ae12f7028a67b6c8c904 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7248 Tested-by: N, Harshapriya <harshapriya.n@intel.com> Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7580 Reviewed-by: N, Harshapriya <harshapriya.n@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15083 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-07intel/amenia: Add asl code to enable google ChromeECShaunak Saha
This patch adds asl code to include support for Google ChromeEC. We need this to show the battery icon and notifications like charger connect/disconnect etc. BUG = 53096 TEST = Plug/Unplug AC Adapter multiple times and make sure the battery connected is charging properly. Change-Id: Id908f145789402573ea54fc4f15cf7a0e651ebf4 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/14987 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-05-26mainboard/intel/amenia: Configure DDI0, DDI1 HPD GPIO lines.Abhay Kumar
1. Configure GPIO_199 and GPIO_200 as NF2 to work as HPD. 2. Make 20k Pullup and remove duplicate code. Change-Id: I8c78d867b03d5f2a6f02165c20777ae25e352ce7 Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/14899 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-26mainboard/intel/amenia: Disable Integrated Sensor HubHannah Williams
Providing an option to enable or disable ISH interface. Leaving it disabled for now. Change-Id: Id4e71d60a6c2da6c6c070d41f66f6c161de38595 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14895 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-25intel/amenia: Extend IFD size by 512 KBBora Guvendik
Increase BIOS region size by 512KB since device extension size is reduced from 1MB to 512KB BUG=chrome-os-partner:52589 TEST=Build Coreboot and boots CQ-DEPEND=CL:*259448,CL:345642,CL:*259445 Change-Id: Ib81b117a3afe730aafa54b4ef31b1e9ab1f67111 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/14929 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-24intel/amenia: Configure Trackpad IC_SDA_HOLD timeJagadish Krishnamoorthy
Elan trackpad needs greater sda hold time. Configure IC_SDA_HOLD register to increase the i2c sda hold time by 0.3us. Change-Id: I3d966eed62a059ecb6a0a88e9f4e6b4ba7a925e4 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/14922 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-12soc/intel/apollolake: use common FADT infrastructureAaron Durbin
Instead of having the mainboards duplicate the same boilerplate code utilize the common FADT infrastructure to reduce duplication. Change-Id: If824619fd619433974e588050a933d2c19b97ec8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14779 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-12intel/amenia: Enable touchscreen in ACPIFreddy Paul
Add support for Elan touchscreen on I2C3 for amenia BUG=None TEST=Boot to Chromium OS and verify if touchscreen is working. Change-Id: Ic75bef0e5878bd5b8c0d727400679663d9f591e3 Signed-off-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://review.coreboot.org/14768 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-11lib: remove FLASHMAP_OFFSET config variableAaron Durbin
The FLASHMAP_OFFSET config variable is used in lib/fmap.c, however the fmdtool creates a fmap_config.h with a FMAP_OFFSET #define. Those 2 values are not consistent. Therefore, remove the Kconfig variable and defer to the #define generated by fmdtool. Change-Id: Ib4ecbc429e142b3e250106eea59fea1caa222917 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14765 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-06intel/amenia: Declare ChromeEC in devicetree.cbAlexandru Gagniuc
This allows the chomeec driver to declare its resources so that IO windows to LPC are opened up during resource allocation. Change-Id: Ife98ecb4cbf5393493e6c71742de8d37953df548 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14591 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06intel/amenia: Check with EC if we should enter recovery modeAlexandru Gagniuc
Change-Id: Id35a74e3968315659b323e0ba348ad38ca11981b Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14590 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06intel/amenia: Configure the bridge to ChromeEC in the bootblockAlexandru Gagniuc
Communication with ChromeEC, which is on the LPC bus, is needed early on for vboot purposes. I'm not sure if Google wants to have the interface available in bootblock or romstage, so we're confguring it in the bootblock. The bridge is automatically reconfigured during ramstage in a way in which we don't get duplicate windows opened upt to LPC. Change-Id: I77887e881d23f655495dec2687394409a5bb8cf5 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14588 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06intel/amenia: Do not manually open up IO windowsAlexandru Gagniuc
Do not use devicetree.cb to manually control hardware registers. This interface will be removed in a subsequent commit and replaced with runtime allocation that also does sanity checking. Change-Id: I55561085ea467f19f52110b1a59f45fe290c7f09 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14582 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-29soc/intel/apollolake: clarify Fast SPI CS2 pad configurationAaron Durbin
The pad for CS2 of the Fast SPI interface needs to be configured for automatic MMIO translation when a SPI TPM is utilized. Instead of unconditionally configuring that pad under LPC_TPM provide a explicit Kconfig for a mainboard to select. Change-Id: Ia94b90e12d71a4b849359188a853f7e036cc583b Signed-off-by: Aaron Durbin <adurbin@chormium.org> Reviewed-on: https://review.coreboot.org/14531 Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Tested-by: build bot (Jenkins)
2016-04-28mainboard/amenia: Enable Chrome EC Interface/KeyboardDivya Sasidharan
Enabled LPC channel between host and EC. Superio.asl will enable proper probing of onboard keyboard. Change-Id: I57014fc90b345661853280ae3402f86e56af5fb9 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://review.coreboot.org/14468 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-20mainboard/amenia: add the inital files for amenia boardZhao, Lijian
Add amenia board files Change-Id: I6731a348b4c0550d3b9381adb5fb83719f90a5da Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/14352 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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