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The mainboard is not being worked on anymore, not available outside of
Intel and thus has litle practical use. Remove mainboard code completely.
Change-Id: Ic2c7ea3810ee70afc01a42786f8ccba9313134e4
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16725
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This patch sets tuned RAPL power limit PL1 value to
12W in acpi/dptf.asl for RAPL MSR register. With PL1
as 12W for WebGL and stream case, we measured SoC power
reaching upto 6W. Above 12W PL1 value, we observed that
Soc power going above 6W. With PL1 as 12W, system is
able to leverage full TDP capacity.
BUG=chrome-os-partner:56524
TEST=Built, booted on reef and verifed the package
power with heavy workload.
Change-Id: I8185ce890f27e29bc138ea568af536bc274fe7b8
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/16596
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch enables DPTF support for Intel Amenia
platform, adds the ASL settings specific to Amenia
boards.
BUG=chrome-os-partner:53096
TEST=Verify that the thermal zones are enumerated
under /sys/class/thermal in Amenia board. Navigate to
/sys/class/thermal, and verify that a thermal
zone of type TCPU exists there.
Change-Id: I400e2312a20870058f3a386004fad748d3ee4460
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15094
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Use the ACPI generator for creating the Chrome OS gpio
package. Each mainboard has its own list of Chrome OS
gpios that are fed into a helper to generate the ACPI
external OIPG package. Additionally, the common
chromeos.asl is now conditionally included based on
CONFIG_CHROMEOS.
Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Update the write protect GPIO reported in ACPI to GPIO_75.
Also update the controller ID to "INT3452:01" which will
point at the goldmont device and includes write protect GPIO.
BUG=none
BRANCH=none
TEST=verify crossystem output for wpsw_cur.
Change-Id: Id6b172e289976072836746c1814e0300544a06cb
Signed-off-by: sselvar2 <susendra.selvaraj@intel.com>
Reviewed-on: https://coreboot.intel.com/7771
Reviewed-by: Sparry, Icarus W <icarus.w.sparry@intel.com>
Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15496
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch adds support to wake up from S3 on lidopen.
mainboard.asl has the _PRW defined for the wakeup support
in S3.
BUG = chrome-os-partner:53992
TEST = Platform wakes up from S3 on lidopen.
Change-Id: I48b456baf5f7e1c2f28454fa66bb90ad761bb103
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15618
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use central header file to include device address and interrupt
line to avoid confusion.
Change-Id: I9560031d9f6e12c665c8ae12f7028a67b6c8c904
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com>
Reviewed-on: https://chromium.devtools.intel.com/7248
Tested-by: N, Harshapriya <harshapriya.n@intel.com>
Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://chromium.devtools.intel.com/7580
Reviewed-by: N, Harshapriya <harshapriya.n@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15083
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch adds asl code to include support for Google ChromeEC.
We need this to show the battery icon and notifications like charger
connect/disconnect etc.
BUG = 53096
TEST = Plug/Unplug AC Adapter multiple times and make sure the battery
connected is charging properly.
Change-Id: Id908f145789402573ea54fc4f15cf7a0e651ebf4
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/14987
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Elan trackpad needs greater sda hold time.
Configure IC_SDA_HOLD register to increase
the i2c sda hold time by 0.3us.
Change-Id: I3d966eed62a059ecb6a0a88e9f4e6b4ba7a925e4
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/14922
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add support for Elan touchscreen on I2C3 for amenia
BUG=None
TEST=Boot to Chromium OS and verify if touchscreen is working.
Change-Id: Ic75bef0e5878bd5b8c0d727400679663d9f591e3
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://review.coreboot.org/14768
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enabled LPC channel between host and EC.
Superio.asl will enable proper probing of onboard keyboard.
Change-Id: I57014fc90b345661853280ae3402f86e56af5fb9
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://review.coreboot.org/14468
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add amenia board files
Change-Id: I6731a348b4c0550d3b9381adb5fb83719f90a5da
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/14352
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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