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List of changes:
1. Initialize dq_map array in a single line
2. Make dqs_map array also in a single line
TEST=Able to build and boot ADLRVP LP4 SKU.
Change-Id: I64f2b38492934c8ede301f4b252c8700060ed4ac
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48077
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=Able to pass MRC training on DDR4/5 SKUs
Change-Id: I38fcb17a1be5a8544a17cef8255631b6abef0741
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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List of changes:
1. Configure CTRLCLK and CTRLDATA for HDMI
2. Enable Ddc and HPD for Port-B
3. Disable dual eDP configuration for Port-A and B
TEST=Able to see depthcharge pre-boot screens over HDMI-B port.
Change-Id: I7509b981f35fc60a7885b2b07067cb0d35ec625f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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HPD_1: A19 -> E14
HPD_2: A20 -> A18
Change-Id: Idf3c8f4931bf8364bb9216a9369df7e05dcde047
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Currently the decision of whether or not to use mrc_cache in recovery
mode is made within the individual platforms' drivers (ie: fsp2.0,
fsp1.1, etc.). As this is not platform specific, but uses common
vboot infrastructure, the code can be unified and moved into
mrc_cache. The conditions are as follows:
1. If HAS_RECOVERY_MRC_CACHE, use mrc_cache data (unless retrain
switch is true)
2. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_BOOTBLOCK, this
means that memory training will occur after verified boot,
meaning that mrc_cache will be filled with data from executing
RW code. So in this case, we never want to use the training
data in the mrc_cache for recovery mode.
3. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_ROMSTAGE, this
means that memory training happens before verfied boot, meaning
that the mrc_cache data is generated by RO code, so it is safe
to use for a recovery boot.
4. Any platform that does not use vboot should be unaffected.
Additionally, we have removed the
MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config because the
mrc_cache driver takes care of invalidating the mrc_cache data for
normal mode. If the platform:
1. !HAS_RECOVERY_MRC_CACHE, always invalidate mrc_cache data
2. HAS_RECOVERY_MRC_CACHE, only invalidate if retrain switch is set
BUG=b:150502246
BRANCH=None
TEST=1. run dut-control power_state:rec_force_mrc twice on lazor
ensure that memory retraining happens both times
run dut-control power_state:rec twice on lazor
ensure that memory retraining happens only first time
2. remove HAS_RECOVERY_MRC_CACHE from lazor Kconfig
boot twice to ensure caching of memory training occurred
on each boot.
Change-Id: I3875a7b4a4ba3c1aa8a3c1507b3993036a7155fc
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46855
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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WWAN_RST#: E10 -> F14
WWAN_PWR_EN: E13-> F21
Change-Id: I7182f384eb7a404dfe623c64e29467b41c6b0bdd
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The patch replaces if-else-if ladder with switch case for readability
purpose.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I268db8bc63aaf64d4a91c9a44ef5282154b20a53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47054
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds the PMC MUX and CONx devices for adlrvp. Device
specific method contains the port and orientation details used
to configure the mux.
BUG=b:170607415
TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects
in SSDT tables.
Change-Id: I3b5bb73991feb99577c16fea00c381dd0f855769
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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List of changes:
1. Use devicetree.cb from default location
2. Create variant directory for ADL RVP with external EC as
'adlrvp_p_ext_ec'
3. Add initial overridetree.cb for 'adlrvp_p' and 'adlrvp_p_ext_ec'
to override 'devicetree.cb' as applicable.
4. Move all common files between 'adlrvp_p' and 'adlrvp_p_ext_ec'
to mainboard directory
TEST=Build and boot both ADLRVP with onboard and external EC.
Change-Id: I3591e214ed32dc9baaa49b92dff59579f29c7bd6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47335
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The patch configures GPIO pins to enable DMIC.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2907737071f7d6b3c88c492d90edf8455d1fa50a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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The patch enables ALC711 Audio codec.
Test=Verified on ADL RVP.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I73f480dad1047cebd7ffc66e0104ff10cacc300b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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This patch enables TCSS xDCI, TBT PCIe root ports and DMA controllers
for ADLRVP.
BUG=b:170607415
TEST=Built and booted on ADLRVP.
Change-Id: Iabd6cc7c589d1c20cde9d66c0a63e2cf16316b33
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47288
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch configures the HPD1 and HPD2 GPIO's.
BUG=b:170607415
TEST=Built and booted adlrvp. Verified the hotplug
functionality is working.
Change-Id: Ied2d4c56220212a15103e9a2fbd01ce6f0811a74
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This patch adds DDR5 memory configuration parameters to FSP.
TEST=Able to build and boot ADLRVP with DDR5 memory.
Change-Id: I4711d66c7b4b7b09e15a4d06e28c876ec35bc192
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46485
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change reorganizes the CNVi device entries in mainboard
devicetree/overridetree and SoC chipset tree to make it consistent
with how other SoC internal PCI devices are represented i.e. without a
chip driver around the SoC controller itself.
Before:
chip drivers/wifi/generic
register "wake" = "..."
device pci xx.y on end
end
After:
device pci xx.y on
chip drivers/wifi/generic
register "wake" = "..."
device generic 0 on end
end
end
Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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List of changes:
1. Split mem_cfg for DDR4 and LPDDR4 as per board_id
2. Move dq_pins_interleaved into board-specific memory configuration
information
TEST=Able to build and boot DDR4 and LPDDR4 ADLRVP SKUs.
Change-Id: I6ef19209767c810426bba0c8bc48178bf2e2a110
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46873
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The dt option `speed_shift_enable` is obsolete now. Drop it.
Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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TEST=Build and test booting ADL RVP form NVMe and Optane
localhost ~ # lspci -d :f1a6
Show all the NVMe devices and be really verbose
localhost ~ # lspci -vvvd :f1a6
Print PCIe lane capabilities and configurations for all the NVMe devices.
Change-Id: I0a04b23b17df574d4fa3bae233ca40cd3b104201
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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A regular M.2 NVMe SSD shows up on RP9 and runs at x4 width.
Optane memory module shows up as 2 NVMe devices in x2 config:
- NVMe storage device uses RP9
- NVMe Optane memory uses RP11
Note: These two devices are sharing CLK PINs because of same M.2 slot.
TEST=Build and boot ADL RVP board using Intel Optane card.
Change-Id: Ia21d7d2fd07c4fb32291af7bb5a2e41e40316278
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Make PCI ClkReq-to-ClkSrc mapping correct to fix SSD detection issue
on ADL RVP.
TEST=Able to detect WD SSD card over PCH SSD RP9.
Change-Id: I7e26429281f8d3b9edae0f266a5868118369be3f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch programs GPIO for PCH SSD Power Enable (GPP_D16) and Port
Detect (GPP_A12) as per schematics.
TEST=Able to build and boot ADL RVP.
Change-Id: I015e46bdf25437c6b196deb3e610bc1b58726070
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add required ASL files into dsdt.asl
TEST=Dump and disassemble DSDT and verify all ACPI devices are present.
Change-Id: I70829e2bdb12fad20627d9aea47e745d9095f07a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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List of changes:
1. Add devicetree.cb config parameters related to FSP-S UPD
2. Configure GPIO as per ADL-P RVP
3. Add files required for ramstage(ec.c, mainboard.c)
4. Add smihandler.c for SMM
5. Add devicetree changes as below
- USB OC PIN programing
- GPE configuration
- SATA port mapping
- LPSS configuration
- Audio configuration
- IA common SoC configuration
- EDP configuration
- TCSS USB configuration
- Enable S0ix
TEST=Able to boot ADL-P RVP without Chrome EC (using on-board EC) with
UART log over legacy UART0 port as 0x3f8 with NVME at RP9 reach till
depthcharge payload.
Change-Id: I120885956c88babfa09d24ce1079d49306919b8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This change switches all mainboard devices to use drivers/wifi/generic
instead of drivers/intel/wifi chip driver for Intel WiFi
devices. There is no need for two separate chip drivers in coreboot to
handle Intel and non-Intel WiFi devices since the differences can be
handled at runtime using the PCI vendor ID. This also allows mainboard
to easily multi-source WiFi chips and still use the same firmware
image without having to distinguish between the chip drivers.
BUG=b:169802515
BRANCH=zork
Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I6f4d0bf9adc1cce4942a16675a072ffea00bd2e0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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List of changes:
1. Add DDR4 and LPDDR4 memory related code
- SPD for LPDDR4
- DQ byte map
- DQS CPU-DRAM map
- Rcomp resistor
- Rcomp target
2. Fill FSP-M related UPD parameters
3. Add devicetree.cb config parameters related to FSP-M UPD
TEST=Able to build and boot ADL-P RVP till ramstage early
Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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List of changes:
1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig
2. Add minimum code to make ADL-P RVP build successfully
3. Mainly bootblock and verstage code added to reach till verstage
4. Add support for 2 mainboards as ADL-P board with default EC (Windows
SKU) and Chrome EC (Chrome SKU)
5. Add empty dsdt.asl to avoid compilation error
TEST=Able to build and boot ADL-P RVP till romstage early.
Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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