coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2021-06-14	mb/intel/adlrvp: Add board id for MR DDR5 SKU	Deepti Deshatty
	Add support for Maple Ridge DDR5 SKU with boardid 0x16 TEST=Verified build for ADL-P Chrome RVP Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: I9f0e9072f5866b60fb8463bb90f61915c78568db Reviewed-on: https://review.coreboot.org/c/coreboot/+/52760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-04-02	mb/intel/adlrvp: Update VBT filenames	Tim Wawrzynczak
	These files were just renamed to put `adlrvp` in between `vbt` and the memory technology type. Change-Id: Icefbac462d0ec9c660541e9cf44686d6dcf82dfd Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52032 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15	mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs	Meera Ravindranath
	Add support to pick the right vbt from cbfs according to SKU-ID. Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-14	mb/intel/adlrvp: Add ADL-P ramstage mainboard code	Subrata Banik
	List of changes: 1. Add devicetree.cb config parameters related to FSP-S UPD 2. Configure GPIO as per ADL-P RVP 3. Add files required for ramstage(ec.c, mainboard.c) 4. Add smihandler.c for SMM 5. Add devicetree changes as below - USB OC PIN programing - GPE configuration - SATA port mapping - LPSS configuration - Audio configuration - IA common SoC configuration - EDP configuration - TCSS USB configuration - Enable S0ix TEST=Able to boot ADL-P RVP without Chrome EC (using on-board EC) with UART log over legacy UART0 port as 0x3f8 with NVME at RP9 reach till depthcharge payload. Change-Id: I120885956c88babfa09d24ce1079d49306919b8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>