| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-02-05 | soc/intel/alderlake: Refactor PCIE port config | Eric Lai |
| 2021-02-01 | soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ | Subrata Banik |
| 2021-01-30 | mb/intel/adlrvp: Remove unnecessary whitespace | Subrata Banik |
| 2021-01-28 | mb/intel/adlrvp: Remove ClkReq assignment for RP8 | Subrata Banik |
| 2021-01-10 | mb/intel/adlrvp: Fix FW download failed for PEG 060, 010 | Subrata Banik |
| 2021-01-10 | soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs | Subrata Banik |
| 2020-12-12 | mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8 | Subrata Banik |
| 2020-12-02 | mb/intel/adlrvp: Replace tab by white space in devicetree | Meera Ravindranath |
| 2020-12-01 | mainboard/intel/adlrvp: Enable PCH PCIe device over x1 slot | Subrata Banik |
| 2020-11-23 | mb/intel/adlrvp: Enable pre-boot display over HDMI-B port | Subrata Banik |
| 2020-11-08 | mb/intel/adlrvp: Refactor ADLRVP code to get rid of 'variants/baseboard' | Subrata Banik |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |