coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2021-05-03	mb/intel/adlrvp: Increase RO/RW region size in chromeos.fmd	Maulik V Vaghela
	While building adlrvp board with chromeos.fmd and adding all chromeos related artifacts, RO region is running out of space. Also, we need to increase RW region size to accommodate all binaries and artifacts. Aligning chromeos.fmd with Brya will help in solving this issue, thus aligning chromeos.fmd with Brya. BUG=b:184997582 BRANCH=NONE TEST=Code compiles fine and able to boot adlrvp platform Change-Id: I644e2e5ba06d2b816d413a7cc9f5f248d8a6fee8 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52732 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21	mb/intel/adlrvp: Add PRESERVE to UNIFIED_MRC_CACHE	Subrata Banik
	This patch preserves MRC training data across FW update. Change-Id: I6b7273471e4fc9dc25eac80904e012f86a981836 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49681 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23	mb/intel/adlrvp: Make SI_ALL region within 16MiB	Subrata Banik
	TEST=Able to build and boot ADLRVP. Change-Id: I93da53f8835e0eec4cf4e78daab26332fd55d334 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-08	mb/intel/adlrvp: Add initial ADL-P mainboard code	Subrata Banik
	List of changes: 1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig 2. Add minimum code to make ADL-P RVP build successfully 3. Mainly bootblock and verstage code added to reach till verstage 4. Add support for 2 mainboards as ADL-P board with default EC (Windows SKU) and Chrome EC (Chrome SKU) 5. Add empty dsdt.asl to avoid compilation error TEST=Able to build and boot ADL-P RVP till romstage early. Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>