coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-03-28	mb/intel/adlrvp: Enable CSE Lite SKU	Sridhar Siricilla
2021-03-15	mb/intel/adlrvp: Select ADL_ENABLE_USB4_PCIE_RESOURCES	Tim Wawrzynczak
2021-03-03	mb//: Don't select PCIEXP_HOTPLUG	Arthur Heymans
2021-02-27	vboot: update GBB flags to use altfw terminology	Joel Kitching
2021-02-24	mb/intel/adlrvp_m: Add initial code for adl-m variant board	Varshit Pandya
2021-02-04	mainboards: Remove default CHROMEOS=y	Kyösti Mälkki
2021-01-21	mb/intel/adlrvp: Remove redundant HAS_RECOVERY_MRC_CACHE Kconfig	Subrata Banik
2021-01-07	mb/intel/adlrvp: Fix building with CONFIG_CHROMEOS unset	Matt DeVillier
2020-12-17	mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports	V Sowmya
2020-11-13	mrc_cache: Move code for triggering memory training into mrc_cache	Shelley Chen
2020-11-09	mb/intel/adlrvp: Add PMC.MUX.CONx device configuration for adlrvp	V Sowmya
2020-11-08	mb/intel/adlrvp: Refactor ADLRVP code to get rid of 'variants/baseboard'	Subrata Banik
2020-11-07	mb/intel: Enable ALC711 Audio codec over SNDW0 link	Sridhar Siricilla
2020-10-11	mb/intel/adlrvp: Add ADL-P romstage mainboard code	Subrata Banik
2020-10-08	mb/intel/adlrvp: Add initial ADL-P mainboard code	Subrata Banik