| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-12-17 | mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports | V Sowmya |
| 2020-11-13 | mrc_cache: Move code for triggering memory training into mrc_cache | Shelley Chen |
| 2020-11-09 | mb/intel/adlrvp: Add PMC.MUX.CONx device configuration for adlrvp | V Sowmya |
| 2020-11-08 | mb/intel/adlrvp: Refactor ADLRVP code to get rid of 'variants/baseboard' | Subrata Banik |
| 2020-11-07 | mb/intel: Enable ALC711 Audio codec over SNDW0 link | Sridhar Siricilla |
| 2020-10-11 | mb/intel/adlrvp: Add ADL-P romstage mainboard code | Subrata Banik |
| 2020-10-08 | mb/intel/adlrvp: Add initial ADL-P mainboard code | Subrata Banik |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |