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Due to the automatic nature of this update, I am self-acking. It worked in
abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Options.lb file that already had a "uses CONFIG_COMPRESSED_PAYLOAD_LZMA"
line in it.
I figure that only adding it to the files that already have support
for LZMA payloads makes sure I don't break anything.
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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(Patch 2, refs #14)
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2529 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2527 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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and leaving enough room for a real payload (not /dev/null)
This is a wonderful example why "uses" sucks.
* add Config-abuild.lb for those boards that dont build with
the default settings and a real payload:
arima/hdama, amd/quartet, amd/serengeti_cheetah, ibm/e326
* if lzma is installed and a real payload is used, try compressing
it.
* fix a small bug in "abuild --help"
This patch is acked by me because its due to infrastructural changes only.
Flames welcome.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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1201_ht_bus0_dev0_fidvid_mb.diff part 1
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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1. x86_setup_mtrr take address bit.
2. generic ht, pcix, pcie beidge...
3. scan bus and reset_bus
4. ht read ctrl to decide if the ht chain
is ready
5. Intel e7520 and e7525 support
6. new ich5r support
7. intel sb 6300 support.
yhlu patch
1. split x86_setup_mtrrs to fixed and var
2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
3. in_conherent.c K8_SCAN_PCI_BUS
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
cache_as_ram for AMD and some intel
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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CROSS_COMPILE
CC
HOSTCC
OBJCOPY
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Move pci_set_method out of hardwaremain.c
- Re-add debugging name field but only include the CONFIG_CHIP_NAME is
enabled. All instances are now wrapped in CHIP_NAME
- Many minor cleanups so most ports build.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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