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2014-05-13southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridgeEdward O'Callaghan
We should configure i8254/i8259 down in to the southbridge rather than romstage of every AGESA/CIMx board much like Intel boards do. Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5669 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10Replace SERIAL_CPU_INIT with PARALLEL_CPU_INITKyösti Mälkki
Lines with 'select SERIAL_CPU_INIT' where redundant with the default being yes. Since there is no 'unselect SERIAL_CPU_INIT' possibility, invert the default and rename option. This squelches Kconfig warnings about unmet dependencies. Change-Id: Iae546c56006278489ebae10f2daa627af48abe94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5700 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-09superio/serverengines/pilot: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ia6ed36c8517a95b651fefdd855eec0ec91d73187 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5439 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-09Squelch some warnings from KconfigKyösti Mälkki
Overriding global config entries in mainboard directory Kconfig files often raise unnecessary warnings. Squelch some of those. Change-Id: Ib5127672ae068670028aa25c8ccb5366277622f2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5699 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA: Implement EmptyHeap()Kyösti Mälkki
Heap allocation begins with BIOS_HEAP_MANAGER, no need to clear the fields individually. Change-Id: Ia1af84bd09d1edf8f72223752557d44a96dec6e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5659 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam15tn: Use common GetHeapBase()Kyösti Mälkki
Implementation of this function is common for all boards in family, and also across different families. Change-Id: I562a132fa6d3ade2700d9a375d7aa21fcf8ea890 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5653 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-03Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh
CONFIG_ARCH is a property of the cpu or soc rather than a property of the board. Hence, move ARCH_* from every single board to respective cpu or soc Kconfigs. Also update abuild to ignore ARCH_ from mainboards. Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5570 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-30mainboard/: Avoid including early_serial.c from w83627hfEdward O'Callaghan
Following the reasoning of: dbbc136 mainboard/asrock/e350m1: Avoid including early_serial.c Change-Id: I5d729b90cf6713de2674fb00c726cd2944a3ab4e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5597 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-28AMD: Add common header file for CAR setupKyösti Mälkki
Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4683 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-26mainboard/*: Remove DUMP_ACPI_TABLES from amd boardsEdward O'Callaghan
Dumping the ACPI tables in this way has limited use, is not likely to be used and is poorly implemented. There are much more sophisticated tools available on Linux for debugging ACPI as such this code is outside the scope of coreboots 'bring up the hardware only' philosophy. A more generic implemention could be done with hexdump() in coreboot proper following on from this cleanup. Change-Id: Ifd3bfb76338609d18fcf7158d3c9a6d7c06c8847 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5530 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-21hp/pavilion_m6_1035dx: Map PCIE PME sources to GPE 0x18Alexandru Gagniuc
The PCIE PME pin from the APU is connected to GEVENT8, but the northbridge's ASL hardcodes this to GPE 0x18. Adjust the SCI map accordingly. Change-Id: Ie395e62919f6e97ef9bcc45c736f9debf4e09ba0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5556 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-21hp/pavilion_m6_1035dx: Map USB and PWRB PME sources to GPE 11Alexandru Gagniuc
Hudson ASL files assume the USB power event notifications are mapped to GPE 0xb. Since that GPE is not used on this board, map these events to GPE11. This GPE is already handled in ACPI via Method(_L0B). We adjust this method to also notify the XHCI controller at PCI 10:0. Change-Id: If33dd4bb5830820227f7c8b34594886cfae37282 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5554 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-21AMD hudson and yangtze boards: Let mainboard declare power buttonAlexandru Gagniuc
The power button was declared by hudson's ASL as \_SB.PCI0.PWRB, and always had the wake source declared as GPE3. This is not the correct wake source for all boards. On some laptops declaring a wake source is not needed, as the wake mechanism is handled by the EC. Move the declaration of the power button to mainboard ASL files, and scope it as \_SB.PWRB . This also makes the naming consistent with the examples in the ACPI spec. The wake source for the PWRB of HP Pavilion M6 1035dx is removed, as it is incorrect. Change-Id: I9c76566025e7f200c0376673f6c6ea299afa4a5d Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5546 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-20hp/pavilion_m6_1035dx: Do not re-init EC and lid SMI on S3 resumeAlexandru Gagniuc
It's not needed, and puts the EC back into APM mode. The EC does not shut down during S3 sleep, so we don't need to re-initialize it. Lid SMI will have been disabled in the switch to ACPI mode, don't re-enable it. Change-Id: I2c06df140f63427dac32ae095d29e68f64135358 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5555 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-20hp/pavilion_m6_1035dx: Suspend/resume on lid close/open with ACPIAlexandru Gagniuc
This patch completes ACPI support for the lid switch. The lid SCI now notifies the OSPM of the status change when the lid is closed or opened, allowing system to suspend. The wake source is also declares, and the system wakes when the lid is opened. The system resumes successfully, but the display still does not come back on. Change-Id: I803c4fc64e15f8d1a90791ec246af66604646d8b Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5549 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-20hp/pavilion_m6_1035dx: Add GEVENT to GPE SCI mapping tableAlexandru Gagniuc
Each GEVENT pins can be mapped to a specific GPE via the SCI map. The default mapping is not appropriate for this laptop, so use the AGESA functionality to map currently known events. Change-Id: Ifa50bf000cfc8e77a6a4d84752f89838f165f7a0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5548 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-20hp/pavilion_m6_1035dx: Move GEVENT/GPE definitions to common fileAlexandru Gagniuc
These definitions were scattered in a couple of files, and we risk scattering them all over the place. Provide a common file for these definitions. Change-Id: I1fe99e5097cf10a349661f3b2ae2377f5cdd6103 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5547 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-19hp/pavilion_m6_1035dx: Implement MB.LIDS ACPI methodAlexandru Gagniuc
Change-Id: I654ca745f7404b86aa25fb2e696751d616d0ca03 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5517 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-19hp/pavilion_m6_1035dx: Implement ACPI for wireless toggle hotkeyAlexandru Gagniuc
Change-Id: I2e9ab68263648af8c9d46999e960f0a0711b61d7 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5516 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-19ec/compal/ene932: Update to use coreboot EC-mainboard APIAlexandru Gagniuc
This patch implements a simple interface between the EC and mainboard ASL code. This interface does not rely on the preprocessor, and prevents name conflicts by scoping the interface methods. As this interface is documented on the coreboot wiki, an in-tree documentation is not provided. Change-Id: If0b09be4f5e17cc444539a30f0186590fa0b72b5 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5515 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-19hp/pavilion_m6_1035dx: Rename "LID0" ACPI object to "LID"Alexandru Gagniuc
There is only one lid switch, so it does not make sense to number it. This naming is also consistent with the examples in the ACPI spec. Change-Id: Ida0a4a89ca03b2aad4fc77e52996e86332d370cd Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5545 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-18hp/pavilion_m6_1035dx: Shutdown when lid is closed on non-ACPI OSAlexandru Gagniuc
This is handled by generating an SMI when GEVENT22 goes low. This pin is driven by the EC when the lid opens or closes. This SMI is disabled when switching to ACPI mode, so ACPI OSes are not affected. Change-Id: I38193572bf0416fd642002dba94c19257f0f6f5b Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/171 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-18southbridge/hudson: Compile refactored SMI setup utilities in SMMAlexandru Gagniuc
Refactor hudson_enable_gevent_smi() to allow configuring the interrupt mode and trigger level. Move the utilities which are useful in SMM to a separate file that is included in both ramstage and SMM. This is useful for SMI handlers which need to enable or disable GEVENT SMIs on-the-fly. A follow-up patch makes use of this infrastructure. Change-Id: Ifa4c300c00c178b18d7280690cfc4b8367c669b8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/170 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-18hp/pavilion_m6_1035dx: Shutdown on low battery with non-ACPI OSAlexandru Gagniuc
Intercept the low battery SMI from the EC, and shut down the system immediately. The EC only sends this SMI when the OS did not enable ACPI mode, so ACPI OSes are not affected by this. On the other hand, payloads such as GRUB or SeaBIOS will experience the shutdown. This behavior is helpful for protecting the battery, for example, when the OS fails to boot and we are stuck in the payload. The low battery SMI is triggered at 10% charge, at which point the risk of cell degradation exists. Change-Id: I4c6c1a4feed8576cbdbb1945768de0805a1f5e42 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5527 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-17AMD hudson yangtze: Drop MAX_PHYSICAL_CPUS in commentsKyösti Mälkki
Change-Id: I81de291da7b3db8d04a127d5a304b558f1c75b34 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5535 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-17hp/pavilion_m6_1035dx: Remove code which dumps ACPI tablesAlexandru Gagniuc
Dumping ACPI tables in canonical form has very little value, and is of questionable use except when debugging acpigen. Remove the code which dumps the tables. Change-Id: Id13c88cee8674b13e5cf5b5ed32c26283e586fd9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5526 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-17hp/pavilion_m6_1035dx: Add SMI handler and handle EC requestsAlexandru Gagniuc
The EC may disable some functionality, such as Caps Lock LED and battery charging if it never receives a command to go in APM mode. If we start it in APM mode, then immediately switch to ACPI mode, it will not get its SCIs serviced until an ACPI OS boots. If its SCIs are not serviced, it may assume the OS has hung. The way we solve this is to initalize the EC in APM mode, and only switch it to ACPI when an ACPI-capable OS issues the ACPI_ENABLE command. The switch has to be handled in SMM. Although we aren't yet processing SMIs from the EC, we are reading the status in order to satisfy the EC that the event is handled. Change-Id: Iffaeb9a6f57841f456c4bce8337dc09b287f8758 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5512 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-16southbridge/hudson: Use MMIO instead of PIO to access PM spaceAlexandru Gagniuc
The MMIO region is set up by AGESA very early on, so we can use it to access the PM register space in ramstage. 16-bit accessors are also provided to simplify some setup tasks. 16-bit accesses are not possible via PIO. The pm2_iowrite/read accessors are removed, as they are not used. Change-Id: Ie7967b5086eb004525c39721338c6495aedc8165 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5503 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-16AMD hudson yantgze: Drop MAX_PHYSICAL_CPUSKyösti Mälkki
Not used with AGESA vendorcode. Change-Id: I4de7e49d513a1bc8d6d4da1eea630b9eedf5de80 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5522 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-04-16AMD hudson yantgze: Drop APIC_ID_OFFSETKyösti Mälkki
Not used with AGESA vendorcode. Change-Id: I1c4e1dea8836143334d336f99afcee2ca326b0c9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5521 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-04-16AMD AGESA: Drop SB_HT_CHAIN_UNITID_OFFSET_ONLYKyösti Mälkki
Not used with AGESA vendorcode. Change-Id: Ic9a0513641bf76d748bb106675bccc33c7abe21e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5520 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-04-16AMD AGESA: Drop LIFT_BSP_APIC_IDKyösti Mälkki
Not used with AGESA vendorcode. Change-Id: Ie99abf5bcffd740e2e7ed6d78937ab32935ef214 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5519 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-04-16AMD AGESA: Drop AMDMCTKyösti Mälkki
This config option is fam10 only. Change-Id: I7f4619d2d4e7e7695a8ee691d879df2748f1c0c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5518 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-16hp/pavilion_m6_1035dx: Add EC keyboard controller to devicetreeAlexandru Gagniuc
This causes coreboot to call the keyboard initialization code for the KBC. This is only needed for payloads which do not initialize the keyboard. Change-Id: Id0bb77f2a8115fafc0cd6165a8431a7e07f0fac1 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5514 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-15hp/pavilion_m6_1035dx: Use hexdump() for dumping ACPI tablesEdward O'Callaghan
Following the rational of: 5188d40 jetway/nf81-t56n-lf: Use hexdump() for dumping ACPI tables Use "Debugging -> Output verbose ACPI debug messages" in menuconfig to toggle. Change-Id: Ibf03ef916a789d0f049190755213ba93191d4662 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5507 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-14hp/pavilion_m6_1035dx: Fix GPIO map and add WLAN pinAlexandru Gagniuc
Change-Id: I07725b71508c8b08451022307ae934c1b227f7f9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5491 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-13hudson boards: Don't require ide.asl file on boards without IDEAlexandru Gagniuc
Not all boards which use the AMD Hudson southbridge have IDE. However, the southbridge's asl included an 'ide.asl' file which had to be present in $(mainboard_dir)/acpi. Address this issue by removing the inclusion of 'ide.asl' from the southbridge 'fch.asl' and remove 'ide.asl' from Hudson boards, none of which have IDE. If future hudosn board will come with IDE, the device can be declared in the PCIO scope of dsdt.asl, right below the inclusion of 'fch.asl'. Change-Id: Ie2efb7ebf8f5b527e26d7aaaeafbd3053a9a6b28 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5459 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-13hp/pavilion_m6_1035dx: Add basic EC initializationAlexandru Gagniuc
The EC is now set to ACPI mode, and properly generates SCIs on external events. This fixes the issue where battery notifications were not working. The keyboard matrix type is also explicitly set up. Change-Id: Ib6f0d23984d4ed1320340282469b8325c83547d1 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5471 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-04-12hp/pavilion_m6_1035dx: Add ACPI support for lid switchAlexandru Gagniuc
This is sufficient to at least allow linux to recognize the lid switch and read its state correctly. Change-Id: Id5bd92466c72559f263c7ca8d23cbc741377a762 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5464 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-12hp/pavilion_m6_1035dx: Declare GPIO control block in ACPIAlexandru Gagniuc
Only the WLAN control pin and the lid switch input are declared, as those are the only pins whose function is known and tested. Change-Id: Ia5871882884ba9bb6d63418b34e33f92ead669eb Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5463 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-12hp/pavilion_m6_1035dx: Add ACPI support for reading battery levelAlexandru Gagniuc
Hook in the EC ASL code. This provides just enough information for the OS to be able to read the battery information. EC notifications (_Qxx) do not yet work, and it is unclear if the issue is in the ACPI code, or if the EC is not set up properly. Thus, the OS must boot with the battery inserted in order to be able to read its status. The _L03 ACPI method is also removed, as the EC SCI uses this event. Change-Id: I85cbaeb9c77e60bd1c68d928412f897de50c6329 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5445 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-09hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tablesAlexandru Gagniuc
Change-Id: I181da410490a92760ae1328a4286e805f5388886 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5462 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-09hp/pavilion_m6_1035dx: Simplify agesawrapper_amdinitcpuio()Alexandru Gagniuc
TRIVIAL. Rather than using the AGESA functions for PCI and MSR access, use the coreboot variants, which are cleaner and more readable. Change-Id: I4f24820606900e16f0d159df019f4560f1592489 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5468 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-07hp/pavilion_m6_1035dx: Remove inexistent devices from devicetreeAlexandru Gagniuc
This removes ominous "PCI: xx:xx.x not found" messages from coreboot console. Change-Id: I13a6f2497c04464e8dd0c4c5e7f40a1582f7f26c Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5461 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-03hp/pavilion_m6_1035dx: Sanitize #includesAlexandru Gagniuc
There were a number of things wrong with the includes. First, The includes did not use paths to AGESA files, thus relying on the compiler include paths to find the correct file. This made it unclear where the file included was located, and whether it was local, under vendorcode, or under a different directory. Instead, use full paths for each non-local include. Second, the local includes were mixed with the rest, making it unclear which file is local and which one is not. Keep the local includes at the top. This also prevents us from polluting the namespace of local headers, with library definitions, and allows us to catch if we missed an otherwise needed external header. Thirdly, alphabetize the order of includes where possible. Change-Id: I22c543291beabb83c16d912ea0a490be6ca4e03c Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5412 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-28mainboard/hp: Add initial support for Pavilion m6-1035dxAlexandru Gagniuc
This was a pathetically easy port, where all the components are already supported. This is basically a verbatim copy of amd/parmer. The EC is an ENE KB932, which is a part that does surprisingly little for an EC. This also means we need almost no code to get it working. I've "select"ed the EC in Kconfig, which is the only difference from parmer, although the keyboard worked fine without it. I haven't coupled in the ACPI code from the EC yet, so battery level is not readable from the OS. Hotkeys work except for brightness control, and the CapsLock LED blinks at regular intervals instead of following the CapsLock key. Change-Id: Idfec6f848b99a52e73eac22d516f3550477ad822 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5409 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-12hp/dl145_g1: Add missing copyright notesOskar Enoksson
Missing copyright notes added. Change-Id: I55b320a169b1125017c63b7a2384078465e7ce6e Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/5188 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-02-12hp/dl145_g1: Fix some commented out codeOskar Enoksson
Some out-commented code contained variables which changed name. This commit fixes the "problem". Change-Id: I8d9168c9f4b2cb6810b3e4dfeff2155f3c08357d Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/5187 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-02-11hp/dl145_g1: Add HAVE_HARD_RESETOskar Enoksson
This platform has a hard reset button Change-Id: Ic4d2f9382b6770654eea8842a37ad38cf12de459 Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/5097 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-02-11hp/dl145_g1: Adding FID/VID and Powernow ACPIOskar Enoksson
Add cool-n-quiet functionality which allows the OS to dynamic alter CPU voltage and frequency change in order to save power e.g. when the CPU load is low. Change-Id: I4c895a56bcf571d4276af192aeef87d120143063 Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/5186 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2014-02-11hp/dl145_g1: Adding ACPI supportOskar Enoksson
Basic ACPI support for this old platform. Created by copying and tweaking similar motherboard ACPI implementations in coreboot. Works reasonably well under Linux, providing HPET-timers and more under linux (tested under OpenSUSE 12.2 kernel 3.4.63-2.44). Not tested under Windows. Change-Id: I69431be962a0d272db398ecf4ac9f0249de8ebab Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/5185 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-01-19board_info.txt: Remove some needless name overrides.Vladimir Serbinenko
Overrides were to have names in line with wiki but names derived from the tree are better in some cases. Change-Id: Ic805ba9a3b9c7f926dc9ef27f8673f2c18e9af34 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4737 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-19board-status: Add board_info.txt extracted from wiki.Vladimir Serbinenko
board_info.txt is a file to be used by board-status to add some useful info to the generated table like flash chip type. This series is autogenerated from wiki page Supported_Motherboards. Change-Id: Ie2bda900713ef4883134477163320936c84c34f5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4701 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-30AMD K8 (rev F): Move rev F0/F1 workaround to headerKyösti Mälkki
Place this in header so it works also when raminit_f.c and raminit_f_dqs.c are not #included in romstage.c build. The workaround remains to be disabled for all boards. Change-Id: Iff0271ceb21ee1e28a1a31d6bbdb97e29d76461e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4568 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-30AMD K8 (rev F): Move MEM_TRAIN_SEQ check to northbridgeKyösti Mälkki
Do it just to remove MEM_TRAIN_SEQ test under mainboard/ to see all K8 rev F boards do the same things here. Change-Id: If75035a4ef8882c2618d434d83ba59c408593d86 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4567 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-30AMD K8 (pre-F): Clean platforms without K8_REV_F_SUPPORTKyösti Mälkki
Change-Id: Ie109f58bd8ce54754b8d0b00118e75ace8717df0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4566 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-29AMD K8 (rev-F): Always have RAMINIT_SYSINFOKyösti Mälkki
K8 Rev F raminit code cannot be built without RAMINIT_SYSINFO, so have the option enabled together with K8_REV_F_SUPPORT. Also move the option under AMD K8. Change-Id: I91fa0b4ae7e3e54fbcb4a4f91eb043956cd0fb60 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4582 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-29AMD fam10: Drop RAMINIT_SYSINFOKyösti Mälkki
AMD fam10 raminit cannot be built without RAMINIT_SYSINFO, this is not a true option but copy-paste remainder from AMD K8. Change-Id: Id8edc112f3bacebd1732304ac9ee6e77cc6263b7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4581 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-26AMD boards (non-AGESA): Cleanup post_cache_as_ram.c includesKyösti Mälkki
Change-Id: Ib3a69e3364418426438f88ba14e5cf744e2414fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4524 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-26AMD boards (non-AGESA): Cleanup earlymtrr.c includesKyösti Mälkki
Change-Id: I5f4bf9dbaf3470dc83d3e980bb6cab10801e15c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4523 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-09AMD boards: Fix includes for microcode updatesKyösti Mälkki
No ROMCC involved, no need to include .c files in romstage.c. Change-Id: I8a2aaf84276f2931d0a0557ba29e359fa06e2fba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4501 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-08-15Include boot_cpu.c for romstage buildsKyösti Mälkki
ROMCC boards were left unmodified. Change-Id: I3d842196b3f5b6999b6891b914036e9ffcc3cef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-06-24AMD: Drop empty root_complexKyösti Mälkki
There are no files to build left under AMD nortbridge/x/root_complex directories. For some cases, even the Kconfig file was no longer sourced. Remove all such references and empty files. For devicetree.cb treat component paths with "/root_complex" in them valid even when the directory does not exists. This is because AMD boards us this dummy chip component as the root node in their devicetree.cb. The generated devicetree file static.c remains unchanged. Change-Id: I9278ebb50a83cebbf149b06afb5669899a8e4d0b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3434 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename pci_domain -> domainStefan Reinauer
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-29Drop empty mainboard.cKyösti Mälkki
Change-Id: Idcf9349d96297b8cb0ea1e68769e02659ac16ab8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1933 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-29Drop empty mainboard_opsKyösti Mälkki
Change-Id: I24866142eebcb8fdbc7e21f5b2f364a8d1b264b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1932 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-28amdk8/amdfam10: Use CAR_GLOBAL for sysinfoPatrick Georgi
This gets rid of the somewhat unstructured placement of AMD's sysinfo structure in CAR. We used to carve out some CAR space using a Kconfig variable, and then put sysinfo there manually (by "virtue" of pointer magic). Now it's a variable with the CAR_GLOBAL qualifier, and build system magic. For this, the following steps were done (but must happen together since the intermediates won't build): - Add new CAR_GLOBAL sysinfo_car - point all sysinfo pointers to sysinfo_car instead of GLOBAL_VAR - remove DCACHE_RAM_GLOBAL_VAR_SIZE - from CAR setup (no need to reserve the space) - commented out code (that was commented out for years) - only copy sizeof(sysinfo) into RAM after ram init, where before it copied the whole GLOBAL_VAR area. - from Kconfig Change-Id: I3cbcccd883ca6751326c8e32afde2eb0c91229ed Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1887 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-27Remove AMD special case for LAPIC based udelay()Patrick Georgi
- Optionally override FSB clock detection in generic LAPIC code with constant value. - Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz - compile LAPIC code for romstage, too - Remove #include ".../apic_timer.c" in AMD based mainboards - Remove custom udelay implementation from intel northbridges' romstages Future work: - remove the compile time special case (requires some cpuid based switching) - drop northbridge udelay implementations (i945, i5000) if not required anymore (eg. can SMM use the LAPIC timer?) Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1618 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-16Fix PIRQ routing abstractionStefan Reinauer
intel_irq_routing_table is a local structure that should not be used globally, because it might not be there on all mainboards. Instead, the API has to be corrected to allow passing a PIRQ table in where needed. Change-Id: Icf08928b67727a366639b648bf6aac8e1a87e765 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1862 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16Drop CONFIG_HAVE_BUS_CONFIG, clean up KconfigStefan Reinauer
This patch is the beginning of a Kconfig cleanup series - drop CONFIG_HAVE_BUS_CONFIG and add get_bus_conf.c if it exists in the mainboard directory - drop duplicate ACPI_SSDTX_NUM from mainboard Kconfig if it only defines the defaul value of 0 - Add mptable.c, fadt.c, reset.c and ssdtX.asl when they exist, not based on some Kconfig magic Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ia14a7116dad6a724af7e531920fee9a51fd0b200 Reviewed-on: http://review.coreboot.org/1832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-14Use mainboard hook for HP DL165Kyösti Mälkki
The board incorrectly overrides the southbridge hook, so use the new mainboard hook instead. This change also activates the actual southbridge hook to enable decode of complete 4 MB flash memory region. Change-Id: I02c6fe89ae9ad4a7403f024fac875ebd88a8e142 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1831 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-06Drop redundant CHIP_NAME in mainboard.cKyösti Mälkki
Compose the name from Kconfig strings instead. As the field is for debug print use only, a minor change in the output should do no harm. The strings no longer include word "Mainboard". Change-Id: Ifd24f408271eb5a5d1a08a317512ef00cb537ee2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1635 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-08-08Cleanup coreboot memory table includesKyösti Mälkki
The includes removed here were previously required for struct lb_memory and lb_add_memory_range(). Change-Id: Ie6c0d4ef55c2225aa709cf3fbad30ff1080e3610 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1391 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2012-08-08Drop HAVE_MAINBOARD_RESOURCESKyösti Mälkki
These existed to provide a hook to add reserved memory regions in the coreboot memory table. Reserved memory are now added as resources. Change-Id: I9f83df33845cfa6973b018a51cf9444dbf0f8667 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1414 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-08-01Intel and GFXUMA: drop redundant use of lb_add_memory_range()Kyösti Mälkki
Use of uma_resource() in northbridge code created a memory resource marked as reserved. Such resources are removed from system memory in write_coreboot_table(). Change-Id: I14bfd560140d8d30ec156562f23072bfae747bde Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1238 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-07-26Drop mainboard chip.hStefan Reinauer
mainboard_config never worked right, at least not since we've had sconfig. Hence, drop mainboard/<vendor>/<device>/chip.h and fix up the mainboards that tried to use it anyways. Change-Id: I7cd403ea188d8a9fd4c1ad15479fa88e02ab8e83 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1359 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-08Clean up #ifsPatrick Georgi
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} + Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} + Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} + Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} + (and some manual changes to fix false positives) Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1004 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com>
2012-04-27Move top level pc80 directory to drivers/Stefan Reinauer
There is no reason for this to be a top level directory. Some stuff from lib/ should also be moved to drivers/ Change-Id: I3c2d2e127f7215eadead029cfc7442c22b26814a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/939 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-08Unify Local APIC address definitionsPatrick Georgi
We used several names for that same value, and hardcoded the value at some more places. They're all LOCAL_APIC_ADDR now (except for lapic specific code that still uses LAPIC_DEFAULT_BASE). Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/676 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17broadcom/bcm5785: Move HAVE_HARD_RESET to southbridgePatrick Georgi
No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: Id95660f088c8240606d45abf326cd5eefca30da3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/658 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-02-17amd/amd8111: Move HAVE_HARD_RESET to southbridgePatrick Georgi
No in-tree amd8111-using board has it not selected, so move selection from boards to southbridge. Change-Id: Iabbaa4cd2fd367ed6decec7ef5cdcbae3b264d52 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/654 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-02-09Remove no-op Makefiles under mainboard directoryKyösti Mälkki
Patch removes following files: src/mainboard/amd/serengeti_cheetah/Makefile.inc src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc src/mainboard/broadcom/blast/Makefile.inc src/mainboard/hp/dl145_g1/Makefile.inc src/mainboard/msi/ms9282/Makefile.inc src/mainboard/supermicro/h8dme/Makefile.inc src/mainboard/tyan/s2881/Makefile.inc src/mainboard/tyan/s2892/Makefile.inc src/mainboard/via/epia-m700/Makefile.inc Change-Id: I020776313abff1772be38afc896af51ca5ab6453 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/612 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-07Delete hard-coded driver includesKyösti Mälkki
Driver components are conditionally included in the build using the Kconfig options. Change-Id: I05417ee263a5b82e947600482dfb68f7a3f52d58 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/610 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-09Fixed whitespace and indentationOskar Enoksson
Code style fixes for the hp/dl145_g1 system board code. Change-Id: I3c1a175d954e2d340e82c03c9f984699dcff865e Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/428 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-07Added RAMINIT_SYSINFO and declared the necessary structsOskar Enoksson
Using RAMINIT_SYSINFO should be beneficial for this platform. It is also more clean/safe to put data in struct mb_sysconf_t. It's more consistent with other MB's and I've tested it thoroughly on my DL145. Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Change-Id: Ie90a134a1efc9605b3fe17a5b5008856226984be Reviewed-on: http://review.coreboot.org/236 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-01remove trailing whitespaceStefan Reinauer
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-28Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n. This might break a couple of boards on runtime, but so far, fixes were quite simple. There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be adapted. Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/320 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-17Re-worked devicetree.cb for DL145 G1Oskar Enoksson
After a lot of experimentation this commit improves some hardware features that were not recognized or incorrectly configured before. The only thing not tested is SCSI-option board (I dont have one). Misleading errors in comments have been corrected. (Note BTW that the DL145 G1 mainboard is identical to AMD Serenade which was supported in early versions of coreboot but was dropped for some reason.) Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Change-Id: Ibbd97fafad22196b1e18d0b257731490339f113e Reviewed-on: http://review.coreboot.org/237 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Refactor mptable generation some morePatrick Georgi
The last couple of lines of every mptable function were mostly identical. Refactor into common code, a new function mptable_finalize. Coccinelle script: @@ identifier mc; @@ ( -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); | -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); ) Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/246 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Get rid of fixup_virtual_wirePatrick Georgi
As stated in some code files, fixup_virtual_wire was established to avoid touching 200 invocations of the mptable code. Let Coccinelle do it: @@ type T; identifier v; @@ -void fixup_virtual_wire(T v) -{ ... } @@ expression A; identifier v; @@ -v = smp_write_floating_table(A); +v = smp_write_floating_table(A, 0); @@ expression A; identifier v; @@ -v = smp_write_floating_table(A, 0); -fixup_virtual_wire(v); +v = smp_write_floating_table(A, 1); Change-Id: Icad8a063380bf4726be7cebb414d13b574112b14 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/245 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Refactor lintsrc generationPatrick Georgi
We copied pretty much the same code for generating mptable entries for local interrupts (with some notable exceptions). This change moves these lines into a generic function "mptable_lintsrc" and makes use of it in many places. The remaining uses of smp_write_lintsrc should be reviewed and replaced by mptable_lintsrc calls where possible, and smp_write_lintsrc made static. This patch was generated using Coccinelle: @@ expression mc; expression isa_bus; @@ -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, isa_bus); @@ expression mc; expression isa_bus; @@ -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0); -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, isa_bus); @m@ identifier mc; expression BUS; @@ -#define IO_LOCAL_INT(type, intr, apicid, pin) smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, BUS, (intr), (apicid), (pin)); ... -IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); -IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, BUS); Change-Id: I97421f820cd039f5fd753cb0da5c1cca68819bb4 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/244 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-03TINY_BOOTBLOCK problem-fix on amdk8+amd8111 platformsenok71
The hp/dl145_g1 motherboard did not work since commit 1f7d3c5672ec90f8d71907b1a07c8a87fa461047 (svn 6124). That commit added TINY_BOOTBLOCK for amd8111 southbridge. The result was that the boot process stopped very early (no console output whatsoever). The same symptom was reported on other AMDK8 based boards with amd8111 southbridge chips. This commit seems to fix the bug. It adds a bootblock.c under src/northbridge/amd/amdk8 that calls enumerate_ht_chains. Probably the problem was that enum_ht_chains needs to be called before the southbridge bootblock.c function, not after. Change-Id: I74fb892aa39048e2d0e76c081b713f825d67f2d4 Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/235 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-04-20run uart_init() from console_init, just like the other console ↵Stefan Reinauer
initialization functions. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-08Enable mahogany_fam10 and Kino family 10h to run the SB HT link at the ↵Scott Duplichan
expected HT3 frequency and width by matching the BUID swap list to the production BIOS. In addition, the BUID swap list has been moved into the project-specific file romstage.c for the other 13 AMD family 10h projects as well. For projects using a desktop AMD family 10h processor, pasting in the mahogany_fam10 swap list will likely allow HT3 operation. This should be confirmed on real hardware before commiting any swap list change. A different swap list will be needed for server projects. For serengeti_cheetah_fam10, a reference BIOS swap list to try is: 0x00, 0x0A, 0x00, 0x06, 0xFF, 0x0A, 0x06, 0xFF. The patch makes these changes: 1) Remove the BUID swap list from ht_wrapper.c and put it in each of 15 romstage.c files where it is used (AMD family 10h projects). 2) Add a prototype to amdfam10.h. 3) Modify the swap list and test in real hardware for mahogany_fam10 and kino family 10h and confirm HT3 operation for the SB link. Abuild tested. Signed-off-by: Scott Duplichan <sc...@notabs.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01Use subsystem id from devicetree.cb instead of Kconfig and moveSven Schnelle
all boards to the new config scheme. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26Make AMD Fam10h CPU microcode updates optional in Expert modeXavi Drudis Ferran
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26Random fixes for TI pci1x2x / Nokia IP530 / others.Uwe Hermann
- nokia/ip530/devicetree.cb, southbridge/ti/pci1x2x/pci1x2x.c: - Fix SMSC FDC37B787 name (was a typo). - Disable PS/2 keyboard/mouse LDN, the IP530 doesn't have either. - Fix typo: s/PCI_DEVICE_ID_TI_1420/PCI_DEVICE_ID_TI_1520/. - All of these are confirmed by Marc Bertens on IRC. - Fix a few CHIP_NAME HP board names. - Random whitespace and coding-style fixes. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1