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2014-11-13nyan: Update 924MHz BCT w/latest qual'd cfg, use 924 as default speed for 2GBTom Warren
BUG=none BRANCH=nyan TEST=built and booted coreboot on my Nyan-rev1, browsed, ran Youtube vids, WebGL experiments, etc. Everything seemed OK. Original-Change-Id: I877680c9329ed96a0b602f0690acaa12079786d7 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/188550 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit b6ca59e9db26f7422fa43ade889c921257a36851) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If166938f241e2a4a8670bfce2df6591b4b71ff67 Reviewed-on: http://review.coreboot.org/7408 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13nyan: nyan_big: Mark the address range covering the SRAM as cachable.Gabe Black
The SRAM is very likely faster than going all the way out to DRAM for data, but I don't think it's part of the cores themselves and won't be as fast as the L1 caches. Enabling caching for this region reduces the time it takes to get to the payload by about 75% when serial output is disabled and the main part of display init is commented out. BUG=chrome-os-partner:25467 TEST=Built and booted on nyan. BRANCH=None Original-Change-Id: I7ff26dea9d50e7d9a76e598e5654488481286b35 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/188459 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit ac8b9b30490d511ca1b207af6845d50e08ac130f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If79dcd1b116f30b778788ba4fd45d362ff5d8e6e Reviewed-on: http://review.coreboot.org/7407 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13nyan: Add 4GB bct supportJimmy Zhang
Replace sdram entry 1 with valid configurations since nyan 4GB board uses RAM_CODE 1. BUG=none TEST=Flash and boot new image.bin. Console shows "RAMCODE=1" and "Total SDRAM (MB): 4096" BRANCH=none Original-Change-Id: Ia872bd7849f1b58075e1f97bf300e081293cb0d4 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/187450 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit f19e2ea3dd4d314b7540c7cf9a11d7af289d24d0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4914c3811b13c8cee0577101bc0c8ee32a0a5b81 Reviewed-on: http://review.coreboot.org/7406 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13nyan: big: Check dram_end when setting up caching in ROM stage.Gabe Black
When setting up caching on nyan and big, we would set the region after DRAM to the end of the address space as uncachable. DRAM may actually extend beyond the end of the address space, so that may result in address aliasing or other problems. This change adds a check to make sure there's actually space there. BUG=None TEST=Built for big. BRANCH=None Original-Change-Id: Ic0a98550222f9dfc0aeafd67a2dd1c0c8f4ece44 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/186769 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 1866a4d2a001beb97779b611b8b69c63175048f4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If1ca8b5bd4efab8962e03c0d9eaa70c0327ea6b5 Reviewed-on: http://review.coreboot.org/7405 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-12Copy u-boot sources as is and modify the tree to still buildVadim Bendebury
This patch brings in ipq806x source files from the vendor's u-boot tree as it was published in the 'cs_banana' release. The following files are being copied: arch/arm/cpu/armv7/ipq/clock.c => src/soc/qualcomm/ipq806x/clock.c arch/arm/cpu/armv7/ipq/gpio.c => src/soc/qualcomm/ipq806x/gpio.c arch/arm/cpu/armv7/ipq/timer.c => src/soc/qualcomm/ipq806x/timer.c arch/arm/include/asm/arch-ipq806x/clock.h => src/soc/qualcomm/ipq806x/clock.h arch/arm/include/asm/arch-ipq806x/gpio.h => src/soc/qualcomm/ipq806x/gpio.h arch/arm/include/asm/arch-ipq806x/gsbi.h => src/soc/qualcomm/ipq806x/gsbi.h arch/arm/include/asm/arch-ipq806x/iomap.h => src/soc/qualcomm/ipq806x/iomap.h arch/arm/include/asm/arch-ipq806x/timer.h src/soc/qualcomm/ipq806x/timer.h arch/arm/include/asm/arch-ipq806x/uart.h => src/soc/qualcomm/ipq806x/uart.h board/qcom/ipq806x_cdp/ipq806x_cdp.c => src/mainboard/google/storm/cdp.c board/qcom/ipq806x_cdp/ipq806x_cdp.h => src/soc/qualcomm/ipq8064/cdp.h drivers/serial/ipq806x_uart.c => src/console/ipq806x_console.c Note that local timer.c gets overwritten with the original version. To prevent a build breakage some shortly to be reverted modifications had to be made to src/soc/qualcomm/ipq806x/Makefile.inc and src/soc/qualcomm/ipq806x/cbfs.c. BRANCH=none BUG=chrome-os-partner:27784 TEST='emerge-storm coreboot' still succeeds Original-Change-Id: I3f50bfbec2e18a3b5d2c640cff353a26f88c98c1 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193722 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 3c9c2ede7e97e330cad2c2f3e557cc9bcdaecdcc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia7bc66cecfc16f1dd4a9f3cb9840cbe91878adf4 Reviewed-on: http://review.coreboot.org/7263 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-12Include IPQ8064 SBLs code in the coreboot bootblockVadim Bendebury
We want the coreboot build produce an image which can be run on the target, even if the remaining parts of the bootprom (recovery path, read-write stages, gbb, etc.) are not available yet. This is achieved by including the Qualcomm SBLs blob in the bootblock. CQ-DEPEND=CL:193518 BRANCH=None BUG=chrome-os-partner:27784 TEST=manual . run the following commands inside chroot to confirm expected image layout (no actual code is executed on the target yet): $ emerge-storm coreboot $ \od -Ax -t x1 -v /build/storm/firmware/coreboot.rom 2>/dev/null | head -1 000000 d1 dc 4b 84 34 10 d7 73 15 00 00 00 ff ff ff ff $ \od -Ax -t x1 -v /build/storm/firmware/coreboot.rom | grep 220000 220000 05 00 00 00 03 00 00 00 00 00 00 00 00 00 01 2a Original-Change-Id: I10e8b81c7bd90e4550a027573ad3a26c38c3808a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193540 (cherry picked from commit 64e193974ee448f78e0a5775a440094901590afb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Idbdbeb9d229eff94a7a94af5dc4844a295458200 Reviewed-on: http://review.coreboot.org/7262 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-12tegra124: Program PWM1 to drive panel backlightAndrew Chew
Repurpose config->pwm to mean the particular PWM device (we use PWM1 on nyan), and add code to program the PWM device. BUG=none TEST=emerge-nyan chromeos-coreboot-nyan, regenerate bootimage, and boot. See that the backlight comes up in the bootloader, and brightness can be adjusted via pwm_bl driver in the kernel. Original-Change-Id: I2db047e5ef23c0e8fb66dd05ad6339d60918d493 Original-Signed-off-by: Andrew Chew <achew@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185772 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> (cherry picked from commit 0dee98dd0c8510ecd630b5c6cb9ea49724dc8b55) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie53610f3afa30b2d8f484685fb0e8c0b12cd8241 Reviewed-on: http://review.coreboot.org/7402 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-12tegra124: Port a PWM clocking change to big.Gabe Black
The generic tegra124 code will use one of the PWMs to drive the backlight of the display, but the PWM clock was enabled only for nyan. This change enables it for big as well. BUG=none TEST=Built for Big BRANCH=None Original-Change-Id: I5171da7c41f4b4db931563ada3e8e4ebf74ec3d9 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/186767 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 687f3771fb3e6b340a818fa7594b3ac0630fdeaf) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ifd14a22a98e7fe273ec28c460b928b8a83c84b66 Reviewed-on: http://review.coreboot.org/7404 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-12tegra124: Enable PWM clock, and set up PWM1 pinAndrew Chew
Configure pin H1 for PWM1, and enable the PWM clock. BUG=none TEST=emerge-nyan chromeos-coreboot-nyan Original-Change-Id: I2f91ebd4666bd227686c08cedf3c1aa7abbe8215 Original-Signed-off-by: Andrew Chew <achew@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185770 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> (cherry picked from commit 069636d9299f64dd64466d45d2297593b37df4f2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic41515842fb883f44f228c77b4cd266e16124d99 Reviewed-on: http://review.coreboot.org/7400 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-12tegra124: nyan: Keep in memory structures below 4GB.Gabe Black
We'd been putting some data structures like the framebuffer and the cbmem at the end of memory, but that may not actually be addressable as identity mapped memory. This change clamps the addresses those structures are placed at so they stay below 4GB. BUG=None TEST=Booted on nyan. Went into recovery mode and verified that there was a recovery screen. Forced memory size to be 4GB and verified that the recovery screen still shows up. BRANCH=None Original-Change-Id: I9e6b28212c113107d4f480b3dd846dd2349b3a91 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185571 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 63ea1274a838dc739d302d7551f1db42034c5bd0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I970c1285270cb648bc67fa114d44c0841eab1615 Reviewed-on: http://review.coreboot.org/7397 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-12nyan: Use asm volatile instead of plain asm so it doesn't get optimized out.Gabe Black
If an asm blob isn't marked as volatile, gcc is free to throw it out if it doesn't think it produces any values that are actually used. To prevent that from happening, add volatile to some asm blobs in the nyan romstage code. BUG=None TEST=Booted on nyan rev1. BRANCH=None Original-Change-Id: I819e068e738e94ea749fcb72bba2eee080e1dfb1 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185610 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 76c09581d6ca4dc6c2f9048f599822939f439d11) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0b32197abf0ddc5f454f9c2415a65d98c60ca48b Reviewed-on: http://review.coreboot.org/7396 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-11-10arm: Redesign, clarify and clean up cache related codeJulius Werner
This patch changes several cache-related pieces to be cleaner, faster or more correct. The largest point is removing the old arm_invalidate_caches() function and surrounding bootblock code to initialize SCTLR and replace it with an all-assembly function that takes care of cache and SCTLR initialization to bring the system to a known state. It runs without stack and before coreboot makes any write accesses to be as compatible as possible with whatever state the system was left in by preceeding code. This also finally fixes the dreaded icache bug that wasted hundreds of milliseconds during boot. Old-Change-Id: I7bb4995af8184f6383f8e3b1b870b0662bde8bd4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183890 (cherry picked from commit 07a35925dc957919bf88dfc90515971a36e81b97) nyan_big: apply cache-related changes from nyan This applies the same changes from 07a3592 that were applied to nyan. Old-Change-Id: Idcbe85436d7a2f65fcd751954012eb5f4bec0b6c Reviewed-on: https://chromium-review.googlesource.com/184551 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 4af27f02614da41c611aee2c6d175b1b948428ea) Squashed the followup patch for nyan_big into the original patch. Change-Id: Id14aef7846355ea2da496e55da227b635aca409e Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> (cherry picked from commit 4cbf25f8eca3a12bbfec5b015953c0fc2b69c877) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/6993 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-09src: Too many terminators ';;' at end of stmts, stop SkynetEdward O'Callaghan
Change-Id: I3e9b7e0e5558a6942067dcea04b83fe3bccbbaf9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7362 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-08bd82x6x: Move to common FADT.Vladimir Serbinenko
Change-Id: I04ed600796c55f5af4f0a07687f676e6484a9830 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7200 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-10-28mainboard/google/butterfly: Fix usage of GNU field designator extEdward O'Callaghan
Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: I167d2c9ad3f690de41fee51dd7800ce76b328e41 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7231 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-28mainboard/google/stout: Fix usage of GNU field designator extEdward O'Callaghan
Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: Id5c5d68048169b0cd400926cead2d1835194d1a5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7210 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-28rambi: switch MCLK from 19.2Mhz to 25MhzKein Yuan
With following settings 1.Coreboot 25Mhz 2.Maxim codec configured with MCLK=25Mhz 2.I2C 400Khz fixed 4.Including Enable/Disable SHDN bit when LRCLK starts/Stops 5.Removed PLL toggle workaround routine. audio playing is smooth before/after S3, no noise when recording so change MCLK from 19.2 back to 25Mhz. BUG=chrome-os-partner:26948 BRANCH=firmware-rambi-5216 TEST=test audio play and record on Rambi, works fine. Change-Id: I5602feb39721344feab837ff4a3a18309a47a6a6 Signed-off-by: Kein Yuan <kein.yuan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/193881 Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit bfe1d535aa2f20a32e163abeb99f3d657e2b43ab) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7219 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-10-28baytrail: Remove unused devicetree fieldsShawn Nematbakhsh
We're no longer configuring hotplug + backlight settings from devicetree, so remove these entries + fields. BUG=chrome-os-partner:27304 TEST=Compile only. BRANCH=rambi+squawks Change-Id: I7e27fbc070a9ea774e7dcbe551d61b1b1682a47f Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193831 (cherry picked from commit 4ab13fd3aa2634673bb099bdfd714a21adc3caa0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7218 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-10-28rambi: always show dev/rec screens on eDP connected panelKein Yuan
bit: 7 6 5 4 3 2 1 0 LFP2 EFP2 EFP3 CRT2 LFP EFP TV CRT so int 15 0x5f35 need to return 0x8(LFP/eDP) instead of 0x2(TV). BUG=chrome-os-partner:26365 BUG=chrome-os-partner:27505 BRANCH=rambi TEST=Booted with and without HDMI connected monitor. DEV screen always showed on eDP panel on Rambi. Change-Id: I8f876e78383424f517689eb25e9229a27739957b Original-Change-Id: I77edbeb3c86549f90302b4296b5a2f50313ca675 Signed-off-by: Kein Yuan <kein.yuan@intle.com> Reviewed-on: https://chromium-review.googlesource.com/193303 Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit dd375462147f182331f336ba826108e58b4e0a47) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7216 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-22tegra/nyan*: sdram updatesTom Warren
nyan_big: Add 204MHz BCT for bringup, use 1.2V for VDD_CPU Reviewed-on: https://chromium-review.googlesource.com/183939 (cherry picked from commit a6df76afb5342b805baca749abb8265e15748dc1) nyan_big: Add initial 792MHz BCT Reviewed-on: https://chromium-review.googlesource.com/183975 (cherry picked from commit 61d0122fdce6dc9479666bb0a5bc079c6389f78a) nyan_big: use RAM_CODE[3:2] for ram code Reviewed-on: https://chromium-review.googlesource.com/184076 (cherry picked from commit 35e5c5e473f871cdc897473a31586afbececd716) tegra124: support tri-state Board Id Reviewed-on: https://chromium-review.googlesource.com/183855 (cherry picked from commit 1a9d1bd73aa2cd0c36203b247976ad0d00a360e4) nyan*: Fix SPI pinmux configuration Reviewed-on: https://chromium-review.googlesource.com/184281 (cherry picked from commit ac4106b673c285af66d72392bd4a8522aba98489) nyan_big: Add 4GB 204/792MHz BCTs Reviewed-on: https://chromium-review.googlesource.com/184159 (cherry picked from commit 5ff002d09f8db0543b58962f6c0d24627fb0937e) tegra124: Add function for obtaining DRAM size via MC regs Reviewed-on: https://chromium-review.googlesource.com/184535 (cherry picked from commit d4580c46de649903a266a99eb11c9126ba385b48) tegra124/nyan*: Obtain DRAM size dynamically Reviewed-on: https://chromium-review.googlesource.com/184431 (cherry picked from commit a7db71744771decc04cf1966efba70bf4897cfa3) tegra124: Rearrange iRAM layout to allow more space for romstage Reviewed-on: https://chromium-review.googlesource.com/184240 (cherry picked from commit 6bdaabbc068146a4516c724b71d31bb777dabcfc) tegra124: Fix MemoryType field name in SDRAM parameters. Reviewed-on: https://chromium-review.googlesource.com/185113 (cherry picked from commit 9caccd1e86a8c683402fab87d9f3a49b87496e97) nyan_big: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/183624 (cherry picked from commit a1cbc00aa80ec1ea52e833a8e31c8e4b27160e70) tegra124: move FB_SIZE_MB to a more appropriate location Reviewed-on: https://chromium-review.googlesource.com/184930 (cherry picked from commit ddea486fd4410394417c4e59039d46a324918bdc) nyan: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/185114 (cherry picked from commit 1ff51b580b28553919f91b11b443251b048cf26b) tegra124: Save SDRAM parameters to PMC registers for LP0 Reviewed-on: https://chromium-review.googlesource.com/182928 (cherry picked from commit 7476b4bd0ecdc312476cce871d22f57915a0bd86) tegra124: Rewrite SDRAM parameter saving code to be more efficient Reviewed-on: https://chromium-review.googlesource.com/184388 (cherry picked from commit 25084bd0407624e4b2ff82388c32af1198c501a6) nyan: Slightly change the way SDRAM parameter files are set up Reviewed-on: https://chromium-review.googlesource.com/185286 (cherry picked from commit a31887b804f23e031c395113db582cd71f3d1b6d) Squashed 16 commits for SDRAM support on nyan and nyan_big. Change-Id: I07419985376277083d62400dd14fe8273f6d5ca8 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6949 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22baytrail/rambi: S3 support and other updatesKein Yuan
baytrail: Change all GPIO related pull resistors from 10K to 20K Reviewed-on: https://chromium-review.googlesource.com/187570 (cherry picked from commit 762e99861dd1ae61ddcf1ebdec8e698ede54405e) baytrail: workaround kernel using serial console on resume Reviewed-on: https://chromium-review.googlesource.com/188011 (cherry picked from commit b0da3bdb5b6b417ad6cab0084359d4eae1cb4469) baytrail: allow dirty cache line evictions for SMRAM to stick Reviewed-on: https://chromium-review.googlesource.com/188015 (cherry picked from commit 50fb1e6a844e1db05574c92625da23777ad7a0ca) baytrail: Optionally pull up TDO and TMS to avoid power loss in S3. Reviewed-on: https://chromium-review.googlesource.com/188260 (cherry picked from commit e240856609b4eed5ed44ec4e021ed385965768d6) rambi: always load option rom Reviewed-on: https://chromium-review.googlesource.com/188721 (cherry picked from commit d8a1d108548d20755f8683497c215e76d513b7a9) baytrail: use new chromeos ram oops API Reviewed-on: https://chromium-review.googlesource.com/186394 (cherry picked from commit f38e6969df9b5453b10d49be60b5d033d38b4594) rambi: always show dev/rec screens on eDP connected panel Reviewed-on: https://chromium-review.googlesource.com/188731 (cherry picked from commit 7d8570ac52f68492a2250fa536d55f7cbbd9ef95) baytrail: stop e820 reserving default SMM region Reviewed-on: https://chromium-review.googlesource.com/189084 (cherry picked from commit 6fce823512f5db5a09a9c89048334c3524c69a24) baytrai: update MRC wrapper header Reviewed-on: https://chromium-review.googlesource.com/189196 (cherry picked from commit 36b33a25b6603b6a74990b00d981226440b68970) rambi: Put LPE device into ACPI mode Reviewed-on: https://chromium-review.googlesource.com/189371 (cherry picked from commit 5955350cd57fd1b3732b6db62911d824712a5413) baytrail: DPTF: Enable mainboard-specific PPCC Reviewed-on: https://chromium-review.googlesource.com/189576 (cherry picked from commit 27fae3e670244b529b7c0241742fc2b55d52c612) baytrail: Add config option for PCIe wake Reviewed-on: https://chromium-review.googlesource.com/189994 (cherry picked from commit 1cc31a7c021ec84311f1d4e89dd3e57ca8801ab5) rambi: Enable PCIe wake Reviewed-on: https://chromium-review.googlesource.com/189995 (cherry picked from commit c98ae1fee54cfb2b3d3c21a19cdbbf56a0bfa1e6) Squashed 13 commits for baytrail/rambi. Change-Id: I153ef5a43e2bede05cfd624f53e24a0013fd8fb4 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6957 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-18lynxpoint: Consolidate common GNVS initVladimir Serbinenko
Change-Id: Ie8e4fffcec308d1cd5e696605e78671f3ababf40 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7054 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-17bd82x6x: Consolidate common GNVS initVladimir Serbinenko
Change-Id: Iea035f80695623e4e8d53eea7e3ec294d868fb5b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7053 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-17Add board_info for all Google/Intel boards mitting the fileStefan Reinauer
Change-Id: Iac53462ab3621d96ba15e2fde2800212584246db Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7072 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-16smbios: Mark laptops as suchVladimir Serbinenko
Change-Id: I179a4cede2f826f72a400208748798737216c01a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7071 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-10-16bd82x6x: Move common bd82x6x S3 detect to bd82x6x code.Vladimir Serbinenko
Change-Id: I9ba1fa5f9ad38cb619466c6199eacd219bc53281 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6921 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-16sandybridge: Move common northbridge finalize to northbridge code.Vladimir Serbinenko
Change-Id: I6d4178e5aaffc1330b0953b0601bf6b448250a8e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6920 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-01storm: Add generic support skeleton for stormFurquan Shaikh
Skeleton for storm mainboard Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/190724 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit ba371d410768fae169da929a23c40139d26a55d3) Removed 'select ARCH_ARM' and added 'select BOARD_ROMSIZE_KB_1024' to the Kconfig. Change-Id: I55c0ad6a47515ba4124b99a69d5776db2365f06e Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6975 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2014-09-29google/panther: add board_info.txtMatt DeVillier
Change-Id: Iec0397a981c31c8af3def04b8c170884f79a50cc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/6871 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-29google/panther: Be safe about invalid thermal readingsStefan Reinauer
In case we get an invalid thermal reading, let's run the fan at full speed rather than at low speed. This might impact the user experiance slightly in cases where the bad reading does not happen while the system is hot, but it will increase stability in the cases where the system is actually overheating. Also, set the critical temperature below tjmax, because otherwise thermal shutdown by the OS will never be triggered. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Iab262f1f17a5dff875c596d9e8d50e4e50ee90f9 Reviewed-on: https://chromium-review.googlesource.com/188556 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 721fc2361ea9c6fea75409be57726294ce840f03) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6962 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-09-25Peppy/Falco: always use native graphicsRonald G. Minnich
The products having shipped, and living in their own branch, we might as well enable native graphics since: 1. it works 2. it removes a blob and the only good blob is a dead blob 3. it's faster 4. when we have problems, we can diagnose them more easily 5. when we get to newer kernels the boot time will magically get faster as the driver realizes graphics is running. Where else do you get a 3-4 second speedup for free? Change-Id: Iad937320e7f46b1de7ab00dace04115a7f182ed1 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/181225 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 7b567d87a9fcf6736e90e730bd052e4465d57bdf) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6912 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-09-25snow: Rename snow to daisy.Gabe Black
The name snow goes by in many places in chromeos is daisy. Snow is technically a variant of daisy and should really be called daisy_snow, but for historical reasons the daisy board with no variant was used instead. To make it easier to work with within chromeos, this change renames the snow board to daisy. Change-Id: I569b31bf417db55be91832f15271bea4bc30f163 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/183553 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 13f24d967251c18dce2a00bcea915f448c4c6aa7) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6929 Tested-by: build bot (Jenkins)
2014-09-25peppy and falco: set panel power timings in northbridge, using devicetree, ↵Ronald G. Minnich
not mainboards Historically we had set panel timing in the mainboard gma code. This goes back to the replay-attack video startup. We can let the haswell gma code set these values from the device tree settings. Change-Id: If32150d2857241ca2d2c88880086f49d25815d76 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/180521 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 406eab3ca6a9bc59382866817786bf96bbb19d56) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6911 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-25pit: Rename pit to peach_pit.Gabe Black
The name pit goes by in many places in chromeos is peach_pit, where peach is the base name and pit is the name of this particular variant. To make it easier to work with within chromeos and to make the board names a little less ambiguous, this change renames the pit board to peach_pit, and from Pit to Peach Pit. Change-Id: I51c89ba3785cf4cb9769a989b1cac71bcd1b0a05 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/183552 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit cbbe1e9f04e34436a1bbae28628e0b5630d41054) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6928 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-24big: Create a nyan_big mainboard which is a copy of nyan.Gabe Black
The nyan_big mainboard is very similar to nyan, but will be different in a few ways. For instance, the BCT will be different, and the GPIOs may need to be configured slightly differently. This change also adds prefixes to the kconfig variables in "choice" blocks for both boards since having multiple instances of choice blocks with the same options confuses kconfig even if all of the instances have mutually exclusive dependencies. Change-Id: I290a32e47fc118bd4b86d543df617ad324325dbc Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/183532 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d1a453fe1aa68b3d12936dd48cc6c94b54f81579) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6927 Tested-by: build bot (Jenkins)
2014-09-22google/{falco,peppy}/gma.c: Do not include non-existent "hda.h"Paul Menzel
Commit 75c83870 (azalia: Shrink boilerplate) [1] removed the header file `hda_verb.h`. This header is still included in the mainboard’s `gma.c`, causing the following build error, when native graphics initialization is enabled. CC mainboard/google/falco/gma.ramstage.o src/mainboard/google/falco/gma.c:34:22: fatal error: hda_verb.h: No such file or directory This was not caught, as native graphics initialization is not enabled for the build tests. It turns out that the array `mainboard_cim_verb_data` is not used in `src/mainboard/intel/wtm2/hda_verb.h`, so fix the problem by removing the inclusion. [1] http://review.coreboot.org/6840 Change-Id: I91e4f00a3030bdef0278102df2783258389bca13 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6946 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-22google/link, intel/wtm2: Do not include non-existent "hda.h" in i915.cPaul Menzel
Commit 75c83870 (azalia: Shrink boilerplate) [1] removed the header file `hda_verb.h`. This header is still included in the mainboard’s `i915.c`, causing the following build error, when native graphics initialization is enabled. CC mainboard/intel/wtm2/i915.ramstage.o src/mainboard/intel/wtm2/i915.c:34:22: fatal error: hda_verb.h: No such file or directory This was not caught, as native graphics initialization is not enabled for the build tests. It turns out that the array `mainboard_cim_verb_data` is not used in `src/mainboard/intel/wtm2/hda_verb.h`, so fix the problem by removing the inclusion. [1] http://review.coreboot.org/6840 Change-Id: Ic902581c6809a1069e169cc874678146a24d75f3 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6945 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-22haswell: Move to per-device ACPIVladimir Serbinenko
Change-Id: Ic724dcf516d9cb78e89698da603151a32d24e978 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6814 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-22tegra124/nyan: memory and display updatesAndrew Bresticker
tegra124: use pll_c_out1 as sclk parent Reviewed-on: https://chromium-review.googlesource.com/180865 (cherry picked from commit 418337a5bde70df6a770222201c51bf3e8892d5f) tegra124: take LP cluster out of reset Reviewed-on: https://chromium-review.googlesource.com/180866 (cherry picked from commit 74cdc68ea9b29da9af313635787e82bacb9e23e3) tegra124: norrin: display code clean up Reviewed-on: https://chromium-review.googlesource.com/181003 (cherry picked from commit 63843ec61b3b47ffc985edcb589771591c5c9f17) tegra124: Change the display hack to use window A Reviewed-on: https://chromium-review.googlesource.com/182001 (cherry picked from commit ef245e42eb17b2eb0e8712f252353a95ee6fc01a) tegra124: norrin: Initialize frame buffer Reviewed-on: https://chromium-review.googlesource.com/182090 (cherry picked from commit b7c1d1b3c9519cbbe1615737aed4c4c0efed2167) nyan: do not enable pull-ups on SPI1 (EC) data pins Reviewed-on: https://chromium-review.googlesource.com/181063 (cherry picked from commit 2f55188501ebcae9e01b12831f152d4520c7047c) tegra124: Add source for the LP0 resume blob. Reviewed-on: https://chromium-review.googlesource.com/183152 (cherry picked from commit a00d099bf710c297320d7edff7f7c608283d1b0b) tegra124: Revise Memory Controller registers structure definition. Reviewed-on: https://chromium-review.googlesource.com/182992 (cherry picked from commit ae83564cdd1d46c8166df1a95703e8cb1060c0a1) tegra124: Add more PMC register details. Reviewed-on: https://chromium-review.googlesource.com/183231 (cherry picked from commit d62ed2c19693284f10c2a12f4295091de3ace829) tegra124: Add SDRAM configuration header file from cbootimage. Reviewed-on: https://chromium-review.googlesource.com/182613 (cherry picked from commit 193ed2a104af38f6c41a332a649ce06a3238e0a4) tegra124: Revise sdram_param.h for Coreboot. Reviewed-on: https://chromium-review.googlesource.com/182614 (cherry picked from commit 311b0568c5de627435a5b035a7a1e40ecc2672f8) tegra124: Fix EMC base address. Reviewed-on: https://chromium-review.googlesource.com/183602 (cherry picked from commit 587c8969292ccecfa29c7720bcf24c704ed4ac4e) tegra124: Add EMC registers definition. Reviewed-on: https://chromium-review.googlesource.com/183622 (cherry picked from commit 67a8e5c7e87a1cc6bf006ad806751b549ffd3d5a) tegra124: Never touch MEM(MC)/EMC clocks in ramstage. Reviewed-on: https://chromium-review.googlesource.com/183623 (cherry picked from commit 8e3bb34d4ae37feae89b4a39850b2988a334d023) tegra124: use RAM_CODE[3:2] for ram code Reviewed-on: https://chromium-review.googlesource.com/183833 (cherry picked from commit 0154239467064ffcbdb82fc4c6b629f5d0c3568d) tegra124: Allow setting PLLM (clock for SDRAM). Reviewed-on: https://chromium-review.googlesource.com/183621 (cherry picked from commit a534e5b7c61d655eedd409dbd7780a4f90d40683) tegra124: SDRAM Initialization. Reviewed-on: https://chromium-review.googlesource.com/182615 (cherry picked from commit 5a60ae93b0603ee0d4806132be0360f3b1612bce) tegra124: Get RAM_CODE for SDRAM initialization. Reviewed-on: https://chromium-review.googlesource.com/183781 (cherry picked from commit a5b7ce70525d7ffef3fac90b8eb14b3f3787f4d8) Squashed 18 nyan/tegra commits for memory and display. Change-Id: I59a781ee8dc2fd9c9085373f5a9bb7c8108b094c Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6914 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-09-22snow/pit: include chromeos.c in romstageIsaac Christensen
When CONFIG_CHROMEOS is enabled, both systems currently fail to build romstage due to undefined symbols. Change-Id: I0edcb141b9a79fad6b1a629bf77cae656c3d6319 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6873 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-19baytrail/rambi: spi, charger, and audio updatesAaron Durbin
baytrail: combine SPI configuration in romstage Reviewed-on: https://chromium-review.googlesource.com/185140 (cherry picked from commit 4e7f0e8ae1138e478ae7106d54719cf05e13b402) baytrail: lock down registers before handoff Reviewed-on: https://chromium-review.googlesource.com/185200 (cherry picked from commit 82cce4d2b46ccc554b71efa179b5d95756e2ad5e) baytrail: invoke SMM finalization on handoff Reviewed-on: https://chromium-review.googlesource.com/185201 (cherry picked from commit 1b50affb1fdda52a5986c9429713930ed517a86a) rambi: don't invoke SMM finalization Reviewed-on: https://chromium-review.googlesource.com/185202 (cherry picked from commit 6eff475dae7f4536eb846ccf6d51fce262b8ffef) rambi: remove handling of APM_CNT_FINALIZE Reviewed-on: https://chromium-review.googlesource.com/185203 (cherry picked from commit 9fc310d7e2730466cc7fcc84999502a2d4d08bab) baytrail: don't increment boot count on S3 resume Reviewed-on: https://chromium-review.googlesource.com/185381 (cherry picked from commit 940a0fa4df1ce335229eb6f80143b93a84ba358c) rambi: enable HDA device Reviewed-on: https://chromium-review.googlesource.com/184574 (cherry picked from commit 334f2a5c7c6540e744b6aaf7e1da0b55e1368196) baytrail: lock down spi controller according to mainboard Reviewed-on: https://chromium-review.googlesource.com/185631 (cherry picked from commit 696ece68cb6d522c248e800f168e675e4b4a7317) rambi: implement mainboard_get_spi_config() to lock dow spi controller Reviewed-on: https://chromium-review.googlesource.com/185632 (cherry picked from commit 1d9ba15858fd421a4fe5a47f7171273128e89524) baytrail: introduce ssus_disable_internal_pull() Reviewed-on: https://chromium-review.googlesource.com/185740 (cherry picked from commit 9d6056dd70b27183dab6a4656f4f9612ae870a4d) rambi: fix write-protect gpio reading at romstage Reviewed-on: https://chromium-review.googlesource.com/185741 (cherry picked from commit c64627689b1afec59be6fdab323d5492046f0bc7) baytrail: DPTF: implement charger current limit Reviewed-on: https://chromium-review.googlesource.com/185759 (cherry picked from commit 287e8936613a7a83281ff692b20383dacf7fcaf6) rambi: Enable charger participant and define states Reviewed-on: https://chromium-review.googlesource.com/185760 (cherry picked from commit 2f62a11927ecf10cb2c76a9f5d368d4050404137) baytrail: increase command wait timeout Reviewed-on: https://chromium-review.googlesource.com/185874 (cherry picked from commit 962a79ef72169b5d52fc746d1889d3b652fd9bcc) baytrail: make caching MRC data more robust Reviewed-on: https://chromium-review.googlesource.com/185875 (cherry picked from commit b5e10ad47b9e4f330caaee4faf69702f24d6bdd8) baytrail: upgrade MRC wrapper header Reviewed-on: https://chromium-review.googlesource.com/186391 (cherry picked from commit 8c1a62f1f4261d4f38aacbbb353c9d6218ec2885) rambi: instruct MRC to use weaker memory ODT settings Reviewed-on: https://chromium-review.googlesource.com/186420 (cherry picked from commit b9329126ca08d20ce1d8c5db0fcabd39140c7292) rambi: Move touch wakeup resource GPIO to separate device Reviewed-on: https://chromium-review.googlesource.com/186932 (cherry picked from commit ba44e2e04f9469c629cb61a911c8cd339f52b0ef) baytrail: Set some MSRs related to turbo power Reviewed-on: https://chromium-review.googlesource.com/186933 (cherry picked from commit 76b25df5a31914ae58d47d17af448216011e425c) baytrail: change power consumption number for ACPI_C3/C6FS. Reviewed-on: https://chromium-review.googlesource.com/186934 (cherry picked from commit 5192e2464fbb88ea6fc117070240c9733e34f065) baytrail: Fix use of ConcatenateResTemplate() in ACPI LPE device Reviewed-on: https://chromium-review.googlesource.com/186928 (cherry picked from commit 8d1ab5de1d43b0790d140f6d0e36a990a5049ece) baytrail: Disable P-state HW coordination on 4-core SKU Reviewed-on: https://chromium-review.googlesource.com/187575 (cherry picked from commit c19c0f1d7cb3cb2635766c186ba9598933424a78) baytrail: DPTF: Enable mainboard-specific _PDL Reviewed-on: https://chromium-review.googlesource.com/187576 (cherry picked from commit 5412ac5c07bee22017a0ee6d1e2433917b98ea87) rambi: Apply DPTF tuning parameters Reviewed-on: https://chromium-review.googlesource.com/187577 (cherry picked from commit 932a5a3803ceaf430ad2934b371ac0886c25efca) rambi : change lpe_codec_clk_freq to 19.2 Reviewed-on: https://chromium-review.googlesource.com/187594 (cherry picked from commit f64cb1ae77076ad5ec994670f4a83dc561ea80c4) Squashed 25 commits for baytrail/rambi. Change-Id: Ibe628ac974d117a09361f7f3131a488911ddd27d Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6933 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2014-09-18samus: Enable XHCI mode by defaultDuncan Laurie
- Enable xhci_default setting in devicetree - Enable usb_xhci_on_resume setting for PEI Change-Id: I2a3965a222ce571a2ad43f568fc2d0ecb94a77bc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180673 (cherry picked from commit c5ef875f6d148964b8ad62a3fe79916c758dbc57) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6908 Tested-by: build bot (Jenkins)
2014-09-18rambi/baytrail: ACPI, GPIO, audio, misc updatesShawn Nematbakhsh
rambi: Change RAM_ID GPIOs to GPIO_INPUT Reviewed-on: https://chromium-review.googlesource.com/182934 (cherry picked from commit 8afd981a091a3711ff3b55520fe73f57f7258cc0) baytrail: initialize rtc device Reviewed-on: https://chromium-review.googlesource.com/183051 (cherry picked from commit 1b80d71e4942310bd7e83c5565c6a06c30811821) baytrail: Set SOC power budget values for SdpProfile 2&3 Reviewed-on: https://chromium-review.googlesource.com/183101 (cherry picked from commit 87d49323cac4492c23f910bd7d43b83b3c8a9b55) baytrail: Set PMC PTPS register correctly Reviewed-on: https://chromium-review.googlesource.com/183280 (cherry picked from commit 1b520b577f2bf1b124db301f57421665b637f9ad) baytrail: update to version 809 microcode for c0 Reviewed-on: https://chromium-review.googlesource.com/183256 (cherry picked from commit 8ed0ef4c3bed1196256c691be5b80563b81baa5e) baytrail: Add a shared GNVS init function Reviewed-on: https://chromium-review.googlesource.com/183332 (cherry picked from commit 969dffda1d3d0adaee58d604b6eeea13a41a408c) baytrail: Add basic support for ACPI System Wake Source Reviewed-on: https://chromium-review.googlesource.com/183333 (cherry picked from commit a6b85ad950fb3a51d12cb91c869420b72b433619) baytrail: allow configuration of io hole size Reviewed-on: https://chromium-review.googlesource.com/183269 (cherry picked from commit 95a79aff57ec7bf4bcbf0207a017c9dab10c1919) baytrail: add in C0 stepping idenitification support. Reviewed-on: https://chromium-review.googlesource.com/183594 (cherry picked from commit 8ad02684b25f2870cdea334fbd081f0ef4467cd4) baytrail: add option for enabling PS2 mode Reviewed-on: https://chromium-review.googlesource.com/183595 (cherry picked from commit c92db75de5edc2ff745c1d40155e8b654ad3d49f) rambi: enable PS2 mode for VNN and VCC Reviewed-on: https://chromium-review.googlesource.com/183596 (cherry picked from commit 821ce0e72c93adb60404a4dc4ff8c0f6285cbdf9) baytrail: add config option for disabling slp_x stretching Reviewed-on: https://chromium-review.googlesource.com/183587 (cherry picked from commit f99804c2649bef436644dd300be2a595659ceece) rambi: disable slp_x stretching after sus fail Reviewed-on: https://chromium-review.googlesource.com/183588 (cherry picked from commit 753fadb6b9e90fc8d1c5092d50b20a2826d8d880) baytrail: ACPI_ENABLE_WAKE_SUS_GPIO macro for ACPI Reviewed-on: https://chromium-review.googlesource.com/183597 (cherry picked from commit 78775098a87f46b3bb66ade124753a195a5fa906) rambi: fix trackpad and touchscreen wake sources Reviewed-on: https://chromium-review.googlesource.com/183598 (cherry picked from commit 3022c82b020f4cafeb5be7978eef6045d1408cd5) baytrail: Add support for LPE device in ACPI mode Reviewed-on: https://chromium-review.googlesource.com/184006 (cherry picked from commit 398387ed75a63ce5a6033239ac24b5e1d77c8c9f) rambi: Add LPE GPIOs for Jack/Mic detect Reviewed-on: https://chromium-review.googlesource.com/184007 (cherry picked from commit edde584bb23bae1e703481e0f33a1f036373a578) rambi: Set TSRx passive threshold to 60C Reviewed-on: https://chromium-review.googlesource.com/184008 (cherry picked from commit 1d6aeb85fd1af64d5f7c564c6709a1cf6daad5ee) baytrail: DPTF: Add PPCC object for power limit information Reviewed-on: https://chromium-review.googlesource.com/184158 (cherry picked from commit e9c002c393d8b4904f9d57c5c8e7cf1dfce5049b) baytrail: DPTF: Add _CRT/_PSV objects for the CPU participant Reviewed-on: https://chromium-review.googlesource.com/184442 (cherry picked from commit e04c20962aede1aa9e6899bd3072daa82e8613bd) rambi: Move the CPU passive/critical threshold config to DPTF Reviewed-on: https://chromium-review.googlesource.com/184443 (cherry picked from commit dda468793143a6d288981b6d7e1cd5ef4514c2ac) baytrail: Fix XHCI controller reset on resume Reviewed-on: https://chromium-review.googlesource.com/184500 (cherry picked from commit 0457b5dce1860709fcce1407e42ae83023b463cd) baytrail: update lpe audio firmware location Reviewed-on: https://chromium-review.googlesource.com/184481 (cherry picked from commit 0472e6bd45cb069fbe4939c6de499e03c3707ba6) rambi: Put LPSS devices in ACPI mode Reviewed-on: https://chromium-review.googlesource.com/184530 (cherry picked from commit 52bec109860b95e2d6260d5433f33d0923a05ce1) baytrail: initialize HDA device and HDMI codec Reviewed-on: https://chromium-review.googlesource.com/184710 (cherry picked from commit 393198705034aa9c6935615dda6eba8b6bd5c961) baytrail: provide GPIO_ACPI_WAKE configuration Reviewed-on: https://chromium-review.googlesource.com/184718 (cherry picked from commit 44558c3346f5b96cf7b3dcb25a23b4e99855497b) rambi: configure wake pins as just wake sources Reviewed-on: https://chromium-review.googlesource.com/184719 (cherry picked from commit ee4620a90a131dce49f96b2da7f0a3bb70b13115) baytrail: I2C: Add config data to ACPI Device Reviewed-on: https://chromium-review.googlesource.com/184922 (cherry picked from commit ffb73af007e77faf497fbc3321c8163d18c24ec8) Squashed 28 commits for rambi and baytrail. Change-Id: If6060681bb5dc9432a54e6f3c6af9d8080debad8 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6916 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-18slippy: remove FUI supportRonald G. Minnich
There's no reason to keep maintaining support on this mainboard, since nobody has one. Change-Id: I5c7c8ea4640170ba231fec82a94a54ee1876b845 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/180503 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit e291d82acbc8bf0d1372e11ac100a7dd340a0040) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6913 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-17spi: add Kconfig variable for dual-output read enableDavid Hendricks
Add a Kconfig variable so that driver code knows whether or not to use dual-output reads. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I31d23bfedd91521d719378ec573e33b381ebd2c5 Reviewed-on: https://chromium-review.googlesource.com/177834 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit de6869a3350041c6823427787971efc9fcf469b8) tegra124: implement x2 mode for SPI transfers on CBFS media This implements x2 mode when reading CBFS media over SPI. In theory this effectively doubles our throughput, though the initial results were almost negligibly better. Using a logic analyzer we see a pattern of 12 clocks, ~70ns delay, 4 clocks, ~310ns delay. So if we want to see further gains here then we'll probably need to tune AHB arbitration and utilization to eliminate bubbles/stalls when copying from APB DMA. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I33d6ae30923fc42b4dc7103d029085985472cf3e Reviewed-on: https://chromium-review.googlesource.com/177835 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 29289223362b12e84da5cbb130f285c6b9d314cc) nyan: turn on dual-output reads for SPI flash Nyan's SPI chip is capable of dual-output reads, so let's use it. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I51a97c05aa25442d8ddcc4e3e35a2507d91a64df Reviewed-on: https://chromium-review.googlesource.com/177836 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 62de0889a9cfc5686800645d05e21e272e4beb5c) Squashed three commits to enable dual output spi reads for nyan. Also fixed the spi_xfer interface that has been updated to use bytes instead of bits. Change-Id: I750a177576175b297f61e1b10eac6db15e75aa6e Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6909 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-13intel/gma: consolidate vbt codeVladimir Serbinenko
Change-Id: I80b7facfb9cc9f642dd1c766884dc23da1aab2c8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6800 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-13arm: Move exception_init() close to console_init()Julius Werner
This patch adds stub implementations of exception_init() to all archs so that it can be called from src/lib/hardwaremain.c. It also moves/adds all other invocations of exception_init() (which needs to be rerun in every stage) close to console_init(), in the hopes that it will be less likely overlooked when creating future boards. Also added (an ineffective) one to the armv4 bootblock implementations for consistency and in case we want to implement it later. Change-Id: Iecad10172d25f6c1fc54b0fec8165d7ef60e3414 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176764 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 2960623f4a59d841a13793ee906db8d1b1c16c5d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6884 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-09-13tegra124/nyan: display, clock, and other updatesJulius Werner
tegra124: Set Tx FIFO threshold value to recommended setting Reviewed-on: https://chromium-review.googlesource.com/175200 (cherry picked from commit c8f086711c6ae2db70fc8e0d84b54f5952fbe0ad) tegra124: add CLK_X definitions Reviewed-on: https://chromium-review.googlesource.com/175220 (cherry picked from commit 3f8a844bd2f151e06d82d1a7fac4492c6bc9417d) tegra124: fix incorrect struct member in clk_rst.h Reviewed-on: https://chromium-review.googlesource.com/175270 (cherry picked from commit 967193d5984a086c297988caa580b61cb4d0414c) tegra124: add the _x clocks to clock_enable_clear_reset Reviewed-on: https://chromium-review.googlesource.com/175539 (cherry picked from commit df4c515d73b02061e5c98f51efd50e04b10d63f5) tegra124: add clock support code for graphics. Reviewed-on: https://chromium-review.googlesource.com/175162 (cherry picked from commit b8eb6ab4cdc5a583636c10fa05f947a244f94819) tegra124: Clean up some #defines for DMA Reviewed-on: https://chromium-review.googlesource.com/175631 (cherry picked from commit 1a0a900f2d060916c9878781b82113b16a7945d9) tegra124: enable flow control for APBDMA in SPI driver Reviewed-on: https://chromium-review.googlesource.com/175630 (cherry picked from commit 873e6f9e95f6cb0162fa06216682fbc71ab0202d) nyan: move clock setup for the display out of dca_init Reviewed-on: https://chromium-review.googlesource.com/175656 (cherry picked from commit 32dd9947a60298ff9488c911629802c257ed6afc) tegra124: more display PLL setup and clock hardcode removal. Reviewed-on: https://chromium-review.googlesource.com/175732 (cherry picked from commit 80402876b5daa9e9389fd4fab5f539d89c37fa7f) tegra124: move dp.c from tegra to tegra124 Reviewed-on: https://chromium-review.googlesource.com/175830 (cherry picked from commit e98be569b0ba7f4d565ce677343a317db08344e0) tegra124: clean up tabbing; nyan: add a comment and setting to devicetree.cb Reviewed-on: https://chromium-review.googlesource.com/175889 (cherry picked from commit 4e513196b0014c5a82079f3aa87c2efbeb645484) tegra: get rid of struct members that are not used Reviewed-on: https://chromium-review.googlesource.com/176023 (cherry picked from commit 032b8a0c9fe0152ebc27344e93128865ecb918a6) tegra124: Increase SCLK (AVP) to 300MHz Reviewed-on: https://chromium-review.googlesource.com/175489 (cherry picked from commit 7e082f2c2f030950d652f1f87f637e15dee38552) tegra124: Address old main CPU starting review feedback. Reviewed-on: https://chromium-review.googlesource.com/175933 (cherry picked from commit 1d76ac71bd839dff9198e65132ec25212dd55ffd) tegra124: Revise clock source configuration for irregular peripherals. Reviewed-on: https://chromium-review.googlesource.com/176109 (cherry picked from commit 1021c215190602a2b8c1ab97d6c8313d89597d99) nyan: add timestamps in romstage Reviewed-on: https://chromium-review.googlesource.com/176172 (cherry picked from commit cd626aa10b56cd4da6ebda36fe487e44b08f3935) tegra124: Allow enabling clock output for external peripherals. Reviewed-on: https://chromium-review.googlesource.com/176108 (cherry picked from commit ea9fb6393ee80da77c9fbc30f605859c7009c9ed) nyan: Enable and configure clocks for I2S and audio codec. Reviewed-on: https://chromium-review.googlesource.com/176104 (cherry picked from commit 1fb659b3e73285ff8218c0f229734edd3b979ca4) tegra124: Fix typo in pinmux name. Reviewed-on: https://chromium-review.googlesource.com/176215 (cherry picked from commit c7915ad41a3f1d1452aa6d6d287aaa8eb9e85c34) nyan: Add pinmux settings for audio peripherals. Reviewed-on: https://chromium-review.googlesource.com/176212 (cherry picked from commit 37412f3201590e47a06d4678fa833164d370b41c) nyan: De-array-ify the PMIC setup code. Reviewed-on: https://chromium-review.googlesource.com/176903 (cherry picked from commit 86ab1ce9fbf6d5362af1ee37de1394412366f247) nyan: Add a kconfig for building for the original nyans in pixel cases. Reviewed-on: https://chromium-review.googlesource.com/176904 (cherry picked from commit 1d05fd5bc40d727826510ec81496ce4a49e257ed) nyan: Set the CPU voltage differently depending on which PMIC is in use. Reviewed-on: https://chromium-review.googlesource.com/176905 (cherry picked from commit 31507f6a575220737ee5683b312cd162600f89cc) nyan: Increase the CPU voltage to 1.2V. Reviewed-on: https://chromium-review.googlesource.com/176906 (cherry picked from commit fe4795e66b515c2523df09a8800ecac9a3f63557) tegra124: Flesh out/tidy up the flow controller constants. Reviewed-on: https://chromium-review.googlesource.com/177085 (cherry picked from commit b50d315506a5ab9c81b6bbaf8cf580dbb3e78794) tegra124: When leaving the bootblock/AVP, really stop the AVP. Reviewed-on: https://chromium-review.googlesource.com/177086 (cherry picked from commit 06c10df889d4d935bc99792df860d93766ae44dd) nyan: Set SPI4 speed to 33MHz Reviewed-on: https://chromium-review.googlesource.com/177038 (cherry picked from commit c98de65482fabdb5c76944fe3bf762191b3a0a55) nyan: Do console_init() in romstage Reviewed-on: https://chromium-review.googlesource.com/176763 (cherry picked from commit 0bec32e09eab28bc5ea49b7896a8b6f489143b03) nyan: Add a prompt to the CONFIG_NYAN_IN_A_PIXEL option. Reviewed-on: https://chromium-review.googlesource.com/177486 (cherry picked from commit 7cbb801d000dac4b39f76266ebef2585fe48faba) nyan: Separate the SDRAM BCT config for the two nyans, and turn down norrin. Reviewed-on: https://chromium-review.googlesource.com/177487 (cherry picked from commit 6b119685f6626d79d924af9f856ebb90af45a73f) tegra124: Bump up HCLK and PCLK Reviewed-on: https://chromium-review.googlesource.com/177563 (cherry picked from commit c25337dac8c3ecdd8ffe5b4d11acebb216132405) nyan: Add some code for reading the board ID. Reviewed-on: https://chromium-review.googlesource.com/177488 (cherry picked from commit 5fccbce99e7db312e2e3caf806c438c9b04c0a8f) nyan: Use the board ID to decide how to initialize the PMIC. Reviewed-on: https://chromium-review.googlesource.com/177489 (cherry picked from commit 677bdb9df55248da3a0c6be0089098f6d6807d3c) nyan: Create kconfig variables for each SDRAM config. Reviewed-on: https://chromium-review.googlesource.com/177580 (cherry picked from commit d7ddcf262a321f06289c4f2b2a6b43982dd96377) tegra124: Mux some unused pins away from UARTA, and pull up the serial RX line. Reviewed-on: https://chromium-review.googlesource.com/177637 (cherry picked from commit bd533cc109b0acf3495b04fa6622e250ba454fe9) tegra124: Initialize the MCR when setting up the UART. Reviewed-on: https://chromium-review.googlesource.com/177638 (cherry picked from commit 38c84786fc3e8fab913aebca176ac7b038cb0be6) tegra124: fix SPI AHB burst length Reviewed-on: https://chromium-review.googlesource.com/177564 (cherry picked from commit f29235263202c9b4a3dbb65da5727c8eefe44315) tegra124: remove unneeded debug print in SPI code Reviewed-on: https://chromium-review.googlesource.com/177833 (cherry picked from commit 34a50040268dbde1c326d315f8042a3905ddfb06) nyan: Set up the SOC and TPM reset pin. Reviewed-on: https://chromium-review.googlesource.com/177965 (cherry picked from commit b81a5bd15a2979ee009b9f7bc4a39a304e6a759a) tegra124: Allow some time for packets to appear in Rx FIFO Reviewed-on: https://chromium-review.googlesource.com/177832 (cherry picked from commit 8f70a25b1eea865a448525749ac18393f5b9ad84) nyan: PMIC: Slam default init values for SDOs/LDOs in AS3722 Reviewed-on: https://chromium-review.googlesource.com/178226 (cherry picked from commit c536b0d82fd6fffbc0e2448e0d19d3f06df5d86a) nyan: change devicetree for the new display settings. Reviewed-on: https://chromium-review.googlesource.com/177958 (cherry picked from commit 43abed730f222c8a685c250a58c981268994a65d) nyan: Switch USB VBUS GPIOs from outputs to pulled-up inputs Reviewed-on: https://chromium-review.googlesource.com/178914 (cherry picked from commit e47b6a609b9d23694a466b56960d9d14ca5d6242) Tegra124: nyan: Disable VPR Reviewed-on: https://chromium-review.googlesource.com/179327 (cherry picked from commit 441aa276446141f1b92ed8fb98c9578597487f4d) tegra124: norrin: fix display issue Reviewed-on: https://chromium-review.googlesource.com/179745 (cherry picked from commit c1c1ae69f6058ed901f532e2c532d1e6ba1f81fb) tegra124: Add iRAM layout information. Reviewed-on: https://chromium-review.googlesource.com/179814 (cherry picked from commit d00f135c93a52ad4dced2edecb74e2dfc54bb2fa) tegra124: Run bootblock and ROM stage out of DRAM. Reviewed-on: https://chromium-review.googlesource.com/179822 (cherry picked from commit 2d3ec06ec39a489d02e798bb22bce4d7465b20ce) nyan: clean up a comment regarding video Reviewed-on: https://chromium-review.googlesource.com/180161 (cherry picked from commit 03b5e88a66b9c96df2ef3d9ce5ba4a62a8bb2447) tegra124: norrin: the first step to clean up display code Reviewed-on: https://chromium-review.googlesource.com/180135 (cherry picked from commit 9d0c12dfef28a1161604df9b3fcc113049b2747d) Squashed 49 commits for tegra124/nyan. Change-Id: Id67bfee725e703d3e2d8ac17f40844dc193e901d Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6883 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-13azalia: Shrink boilerplateVladimir Serbinenko
Change-Id: Ib3e09644c0ee71aacb067adaa85653d151b52078 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6840 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-12tegra124/nyan: various fixes and additionsHung-Te Lin
Tegra124: SDMMC: Configure base clock frequency. Reviewed-on: https://chromium-review.googlesource.com/173841 (cherry picked from commit d3157e9a380cfb018cc69a1f23f277c3c5b680a6) Tegra124: SDMMC: Configure pinmux for MMC 3/4. Reviewed-on: https://chromium-review.googlesource.com/174011 (cherry picked from commit 55af9a86a56d6bc0ce9bcff4fd5226a60ae2033b) tegra124: Move DMA-related #defines and definitions to header Reviewed-on: https://chromium-review.googlesource.com/174444 (cherry picked from commit 9d917927a5b7151958289469b9049ac91efa41e3) tegra124: Assign console address for kernel. Reviewed-on: https://chromium-review.googlesource.com/174486 (cherry picked from commit 36e9370f30bd173879958d164156997841ec4e9c) nyan: Fix up the gpio indices in chromeos.c. Reviewed-on: https://chromium-review.googlesource.com/174418 (cherry picked from commit fba4ae1080c19f11abe1205b871ada14db996c61) Nyan: turn on the backlight. Reviewed-on: https://chromium-review.googlesource.com/174533 (cherry picked from commit 12649c9611981dd8d6567ba0238c8b8247c52215) tegra124: Fix the disp1 source field. Reviewed-on: https://chromium-review.googlesource.com/174701 (cherry picked from commit eed380e09075e1eef0bde7d1bb15c4343f30bfe0) nyan: set up the aux channel i2c interface Reviewed-on: https://chromium-review.googlesource.com/174620 (cherry picked from commit ea81cb44a1c11cd78643c69ac818304cd393749e) tegra124: fix typos in the clock code. Reviewed-on: https://chromium-review.googlesource.com/174684 (cherry picked from commit 72365c33693db4eb6e01032938221f592b7e5a02) tegra124: Revamp clock source/divisor configuration Reviewed-on: https://chromium-review.googlesource.com/174804 (cherry picked from commit 3f31a634f69595bcc6a473301d1492c97a767809) tegra: Add gpio_output_open_drain() function Reviewed-on: https://chromium-review.googlesource.com/174650 (cherry picked from commit bc1c28926810e722e9b82339ea0585d083e3fa8c) tegra124: add nvidia-generated files Reviewed-on: https://chromium-review.googlesource.com/174610 (cherry picked from commit 7706f3200f7fc11b7a443f336bff6a37afa94652) nyan: Ignore the dev mode GPIO. Reviewed-on: https://chromium-review.googlesource.com/174837 (cherry picked from commit 9513e608f3063fdb3e9d8bd04e6e5fe35a5bfcee) Tegra124: Add support for the ARM architectural timer. Reviewed-on: https://chromium-review.googlesource.com/174835 (cherry picked from commit 25a91fcf7e79cc450caa59bc6b65f954bb96ac6c) nyan: Initialize the ARM architectural timer in the RAM stage. Reviewed-on: https://chromium-review.googlesource.com/174836 (cherry picked from commit 581f592c12de91c0cf8279ede2850e38dd0cd2e8) tegra124: nyan: Move mainboard level clock stuff into the mainboard source. Reviewed-on: https://chromium-review.googlesource.com/174843 (cherry picked from commit 5ab100b0bad22814261f9b755b59394562c9145a) tegra124: add some explanatory text about U7.1 computations. Reviewed-on: https://chromium-review.googlesource.com/173910 (cherry picked from commit 822cad0ceeceeb5160c8216e05eec13fd04a6413) Set the EC SPI clock source to PLLP and divide down to around 5MHz Reviewed-on: https://chromium-review.googlesource.com/173954 (cherry picked from commit c0e22d76d3887ca1f727443a47db38dec12c0b74) nyan: Move non-essential configuration out of bootblock and into ram stage. Reviewed-on: https://chromium-review.googlesource.com/174844 (cherry picked from commit dad7f68c76f7b83edacd8b22c9dbd3f0ff027397) tegra124: clocks: Save some IOs in clock_enable_clear_reset. Reviewed-on: https://chromium-review.googlesource.com/174845 (cherry picked from commit 81b977a2758d42471667e2cbe31f160dfda5bca4) tegra124: re-write SPI driver w/ full duplex support Reviewed-on: https://chromium-review.googlesource.com/174446 (cherry picked from commit 51c9a34240d6a068780a7d1c27b032b56b2d3e54) tegra124: move SPI-related structures from .c to .h Reviewed-on: https://chromium-review.googlesource.com/174637 (cherry picked from commit 36760a4463c2c33f494ca7ea5a36810fa4502058) tegra124: add frame header info to SPI channel struct Reviewed-on: https://chromium-review.googlesource.com/174638 (cherry picked from commit e24773eb946e2c4cb5e828f055d45d92bd1a4f9f) tegra124: re-factor tegra_spi_init() Reviewed-on: https://chromium-review.googlesource.com/174639 (cherry picked from commit 88354b996459a702c36604f5f92c24e63df8de7e) nyan: Set CrOS EC frame header parameters for SPI Reviewed-on: https://chromium-review.googlesource.com/174710 (cherry picked from commit 29173ba5863eebb2864a8384435cde2f0d5ca233) tegra124: Add Rx frame header support to SPI code Reviewed-on: https://chromium-review.googlesource.com/174711 (cherry picked from commit 1d1630e770804649ef74d31db194d3bde9968832) tegra124: add support for the Serial Output Resource (sor) Reviewed-on: https://chromium-review.googlesource.com/174612 (cherry picked from commit 3eebd10afea4498380582e04560af89126911ed9) nyan: tegra124: Enable I, D and L2 caches in romstage. Reviewed-on: https://chromium-review.googlesource.com/173777 (cherry picked from commit 74512b7ecfbd50f01a25677307084699ee8c6007) tegra and tegra124: Bring up graphics Reviewed-on: https://chromium-review.googlesource.com/174613 (cherry picked from commit 7e944208a176cdac44a31e2a9961c8bd5dc4ece8) nyan: Move the DMA memory region. Reviewed-on: https://chromium-review.googlesource.com/174953 (cherry picked from commit c66e22859252eaebceb07a3118ac61f4cf6289eb) tegra124: Increase CBFS cache buffer size Reviewed-on: https://chromium-review.googlesource.com/174950 (cherry picked from commit 6dbb4e5f0d66c68df45ac73e3f223b856b715026) tegra124: Add USB PLL, PHY and EHCI setup code Reviewed-on: https://chromium-review.googlesource.com/174651 (cherry picked from commit ecd5c398ff6748a7d40089019471357b58d3a6ea) tegra124: add in some undocument clock source and PLL registers Reviewed-on: https://chromium-review.googlesource.com/174948 (cherry picked from commit 73fcc4981da6e4415b514eaafb42bc265ab0cd9a) tegra124: small cleanups of the code Reviewed-on: https://chromium-review.googlesource.com/174995 (cherry picked from commit 7256aba07e9567ef8d73f05e1f80c4d45fd57bda) Squashed 34 commits for tegra124 / nyan support. Change-Id: I050c7ad962e0d24550b0b33c9318e89c80d01f00 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6870 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2014-09-12panther: update chromeos.cIsaac Christensen
The google mainboards were updated to unconditionally include chromeos.c except for panther. Change-Id: I35bbd56326ee0f94ee542bae28f9c23980e9a9ed Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6874 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-11tegra124/nyan: rougly stable code baseGabe Black
nyan: Clock setup. Reviewed-on: https://chromium-review.googlesource.com/172106 (cherry picked from commit 3697b6454c0aceebcf735436de90ba2441c9b7b1) tegra124: Call into the mainboard bootblock init if one exists. Reviewed-on: https://chromium-review.googlesource.com/172581 (cherry picked from commit 3a0cd48a0d1a9ce6b32ed614cd81fb81f5f82aec) nyan: Add a mainboard specific bootblock. Reviewed-on: https://chromium-review.googlesource.com/172582 (cherry picked from commit a83d065d660a26fe71ed79879c25f84a1b669f69) nyan: tegra124: Redestribute the clock code between the mainboard and soc. Reviewed-on: https://chromium-review.googlesource.com/172583 (cherry picked from commit ea703137fc37befa7d5a65afc982e298a0daca1b) nyan: Initialize the i2c pins and controllers. Reviewed-on: https://chromium-review.googlesource.com/172584 (cherry picked from commit 9c10a3074ef834688fea46c03551c2e3e54e44a8) nyan: Initialize the PMIC. Reviewed-on: https://chromium-review.googlesource.com/172585 (cherry picked from commit f6be8b0e607e05b73b5e4a84afcf04c879eee88a) tegra124: add a chip.h and use it in NYAN Reviewed-on: https://chromium-review.googlesource.com/172773 (cherry picked from commit 4dd5f1f091f2dcae5ce38203bb86c62994609f8f) tegra: Reorder GPIO register accesses to avoid glitching Reviewed-on: https://chromium-review.googlesource.com/172730 (cherry picked from commit 61bedbf0f839e19b284d21af2ad10f2ff15e17d5) tegra: Turn GPIO wrappers into macros to make them easier to write Reviewed-on: https://chromium-review.googlesource.com/172731 (cherry picked from commit 94550fdfa5a8005d2e6a313041de212ab7ac470c) tegra: Change GPIO functions to allow variable arguments Reviewed-on: https://chromium-review.googlesource.com/172916 (cherry picked from commit e95ccd984f718a04b6067ff6ad5049a2cd74466d) tegra124: Implement starting up the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/172917 (cherry picked from commit 7c5169a197310e18a3df0f176c499669e3c2bda3) tegra: Simplify the I2C constants. Reviewed-on: https://chromium-review.googlesource.com/172953 (cherry picked from commit 130a07c86dfa5ba5ac4580f29db927c91f045c76) tegra124: Fix SPI base addresses Reviewed-on: https://chromium-review.googlesource.com/173322 (cherry picked from commit da808e46919ebd3b9f2377a5889f0d5f10b92357) tegra124: Scrub the clock constants. Reviewed-on: https://chromium-review.googlesource.com/172954 (cherry picked from commit 9305ff0696a6d556a97f928b8683770833a309a4) tegra124: add DMA support Reviewed-on: https://chromium-review.googlesource.com/172951 (cherry picked from commit 4d2a5a56b922ac37d2326d7b139697567aac37b8) tegra124: add basic SPI driver Reviewed-on: https://chromium-review.googlesource.com/172952 (cherry picked from commit 5f861f13c7fd2dd881f3cbd0f1b4d4a9994ce429) tegra124: Add an assembly stub which is run first on the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/173541 (cherry picked from commit e142b9572a89f43fe984c4fc87e3203f380ff4de) nyan: tegra124: Set up dynamic cbmem. Reviewed-on: https://chromium-review.googlesource.com/173542 (cherry picked from commit b6e1a70103446abb5c3440f145617e6566879c6f) tegra124: Add an soc.c which sets up the chip operations and memory resource. Reviewed-on: https://chromium-review.googlesource.com/173543 (cherry picked from commit af49a5bd1f589cf053c4808510138aae26e20db4) tegra124: extend chip.h to include video settings Reviewed-on: https://chromium-review.googlesource.com/173600 (cherry picked from commit 87687633a2116f58fad7333b3b639cee9089ad29) tegra124 and nyan: fill in the devicetree a bit more, add defines Reviewed-on: https://chromium-review.googlesource.com/173684 (cherry picked from commit c107eaca3dea42be89f61690d0d6cb2181acb147) tegra124: clean-ups for SPI driver Reviewed-on: https://chromium-review.googlesource.com/173599 (cherry picked from commit 1e2f9fd442ea336bf0663c3c8ea51f771e21beb7) tegra124: add a #define for DMA alignment size Reviewed-on: https://chromium-review.googlesource.com/173638 (cherry picked from commit f9dc2a8d8016fa7db974fb6cb01c3275e26832af) tegra124: Add FIFO transmit functions to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173639 (cherry picked from commit 97e61f36ad96ce2f9b12a7ef765ee73d3f4285f7) tegra124: clean-ups for DMA driver Reviewed-on: https://chromium-review.googlesource.com/173598 (cherry picked from commit 750c0a5d6942748dd21f3a3f884ad94a561e86e0) tegra124: early display and display code. Reviewed-on: https://chromium-review.googlesource.com/173622 (cherry picked from commit 651c7ab96b1f136865e4673a120de7afc1218558) tegra124: Move transfer size handling to spi_xfer() Reviewed-on: https://chromium-review.googlesource.com/173680 (cherry picked from commit 4a9b7b47b3c09d70063ea843054ffef98f554621) tegra124: strict error detection and reporting for SPI Reviewed-on: https://chromium-review.googlesource.com/173681 (cherry picked from commit c056fa954e1dab40a56faec6c50385763a2eb010) tegra124: add thread-friendly delays to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173648 (cherry picked from commit c1a321c8f61942801627f895c5db74c518e2aa8e) Tegra124: Take the SPI1 controller out of reset and enable its clock. Reviewed-on: https://chromium-review.googlesource.com/173787 (cherry picked from commit c026a3fb861e157f1e17a121fc2ef70b903f36f2) tegra124: add two more clock setting values Reviewed-on: https://chromium-review.googlesource.com/173772 (cherry picked from commit 7d79d7dd9f0c1fd7127a7ba41652d809ccff7a57) nyan: Set up the ChromeOS related GPIOs and SPI bus 1 which goes to the EC. Reviewed-on: https://chromium-review.googlesource.com/173788 (cherry picked from commit ff172bfe30f75983a1e8efa2ead0a4519583d0a8) tegra124: Add some stub functions to the Tegra SPI driver. Reviewed-on: https://chromium-review.googlesource.com/173789 (cherry picked from commit 8bc527aa4afd301c046b0e844c7fa400630af0d2) tegra124: Build source files into the various stges needed by CONFIG_CHROMEOS. Reviewed-on: https://chromium-review.googlesource.com/173790 (cherry picked from commit 86a6423b668ca912295c47d8c6e3ef6c6f8c6084) nyan: Implement the code which reads GPIOs for ChromeOS. Reviewed-on: https://chromium-review.googlesource.com/173791 (cherry picked from commit 4c394dfbce762574fc79edcb6e4ac6bf346e48a3) nyan: Enable the CHROMEOS and ChromeOS EC related kconfig options. Reviewed-on: https://chromium-review.googlesource.com/173792 (cherry picked from commit 2845a4487159aa4b1dba58d977f52c449574fc8e) Tegra124: SDMMC: Take the SDMMC 3 and 4 out of reset and ungate their clocks. Reviewed-on: https://chromium-review.googlesource.com/173793 (cherry picked from commit c238b87bcd9d35afd828476d6ee88322ac5d0f88) tegra124: fix clear_fifo_status() in SPI driver Reviewed-on: https://chromium-review.googlesource.com/173738 (cherry picked from commit f415d2c0aaffc0f1a3592551a2db782d538f8f4f) ARM: Include stdint.h in cpu.h. Reviewed-on: https://chromium-review.googlesource.com/173774 (cherry picked from commit f1930faea3f14b2a2560a6c4058ef38532b6f1a6) tegra124: When setting up the main CPU, set its CPSR appropriately. Reviewed-on: https://chromium-review.googlesource.com/173775 (cherry picked from commit bc2ba9c15cfd22aeaca4f80b1d13a8b5e0178ead) tegra124: fix wrong names in clk_rst.h Reviewed-on: https://chromium-review.googlesource.com/173955 (cherry picked from commit 19dd9c85e4a3d1f77b23828bcbdd4bd8c2688b8d) tegra124: Fix up the PLLX divider table. Reviewed-on: https://chromium-review.googlesource.com/173778 (cherry picked from commit 3362cf3a7d6f5eaec879dda42323345922f6df17) tegra124: clock: Get rid of cpcon and dccon. Reviewed-on: https://chromium-review.googlesource.com/173779 (cherry picked from commit 08626ffac4a7e9ea3d4738af87e9e4cced7be2c7) Tegra124: SPI: Set and unset CS in spi_claim_bus and spi_release_bus. Reviewed-on: https://chromium-review.googlesource.com/173953 (cherry picked from commit a2df8f3a9c9c54c62d6ff37d3baff1d30ee6d355) armv7: expose dcache_line_bytes() in cache API Reviewed-on: https://chromium-review.googlesource.com/173975 (cherry picked from commit 6727f65702c7668fcb33848b4113bc3d3cc04e12) libpayload: expose dcache_line_bytes() in ARM cache API Reviewed-on: https://chromium-review.googlesource.com/174099 (cherry picked from commit 9387b02dff85b42944d95c3bccf59059c93fb4a9) armv4: add a stub for dcache_line_bytes() Reviewed-on: https://chromium-review.googlesource.com/173976 (cherry picked from commit 924f61ea895b9268c716791466637009bbac6469) tegra124: Base early UART on CLK_M to enable debugging of PLL init code Reviewed-on: https://chromium-review.googlesource.com/174339 (cherry picked from commit 8d9387432f0a0d9b257b040304238e543cced1aa) tegra124: Add additional PLLs and redesign the divisor table Reviewed-on: https://chromium-review.googlesource.com/174380 (cherry picked from commit f6a5f5c4562f1ca733505717c175be00413f2384) Squashed 49 commits for tegra124/nyan that included a lot of churn on different pieces. Change-Id: I00e8f5b74e835e01b28ca2e9c4af3709c9363d56 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6869 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-11Move nehalem/sandy/ivy to per-device acpiVladimir Serbinenko
Change-Id: I3d664ab575bf9c49a7bff9a395fbab96748430d0 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6802 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-09-11mainboard/google/parrot: fix ACPI interrupt storm on lid switch changeAndrew Litt
This fixes the ACPI interrupt storm on Parrot that happens when closing the lid or entering suspend by lid close (seen in /sys/firmware/acpi/interrupts/gpe1F). This patch inverts the interrupt trigger level every time the interrupt is received so that it doesn't fire until the next state change. http://askubuntu.com/questions/310196 is a good example of what this is trying to solve. Change-Id: I8b095914e9330c3217a4ceb058613fa952f4a234 Signed-off-by: Andrew Litt <ajlitt@splunge.net> Reviewed-on: http://review.coreboot.org/6858 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-10samus: Fix 8GB SPDDuncan Laurie
The 8GB variant is x16 with 11 column bits and 4Gb density. Change-Id: I3aa647aba88dbc928fefd826cbd01e4fa8273660 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176640 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit d18462f6fc0d40328e9619525240778ea6b1a426) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6856 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-10samus: GPIO updates for Proto1bDuncan Laurie
Move NFC_INT to GPIO9 Swap CODEC_INT to GPIO46 and WLAN_DISABLE_L to GPIO42 Swap ACCEL_INT to GPIO45 and PP1800_CODEC_EN to GPIO43 Enable PP1800_CODEC_EN, CODEC_LDOENA, CODEC_RESET_L Old-Change-Id: I5547d34f1b7953808375aa5fe5e0a9640ae7e05e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175291 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5bb4bc59e37ee4fe9a0556e08a53402c822e5bd6) samus: Misc fixes from proto1b bringup - NFC interrupt is expected in the kernel as a GPIO now, so set it back to that type - NFC FW update GPIO should be low - Accel/Codec interrupts were still set as GPIO type, they should be set as PIRQ type Old-Change-Id: I354c848ae7b158943f4745872b82a49e17e67e2f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176513 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 75a0944f320c80618f12732a23344ce40010a688) Squashed two small patches for samus. Change-Id: I7ec56191fe2b7f19e470df175ad0bbe320a442f5 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6852 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-10nyan: Add a stub mainboard.Gabe Black
Old-Change-Id: Icdde4cf5e1abb3ae1ad14279ebc129919ba30074 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170837 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit e9d87534ccacb42d508f1902786470798a2dbaea) nyan: Add a "special-class" for aggregating BCT files into bct.cfg. The config file which cbootimage processes to create a BCT could come from multiple different files, individually selected based on config options, and/or split up into different files for organizational purposes. This change adds a special-class which collects those files and concatenates them all together in a bct.cfg which can be processed more easily by other parts of the build. While the BCT files themselves are potentially very board specific, for instance ones that hold memory timing information, this bit of code which collects them is not. It has to be in each board file instead of alongside the CPU, however, to ensure that the special class is set up before another Makefile tries to use it. If we end up with lots of Tegra based boards which duplicate this code over and over, we might want to revisit how this works. Old-Change-Id: I58e1373434f89e69298990ea4643a19d8afdc309 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170922 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 3ae44178b7084037a75e16ce161b1432abf4246a) nyan: Add bct files for nyan. There's a config option which selects between the emmc and spi config files depending on what the firmware is intended to boot from. These are copied from the files installed by the tegra-bct-nyan ebuild, except that the spi config file has been modified so that there's only one copy of the BCT and so that it only has one configuration. This is to save space in the final image. Old-Change-Id: Ibf1b895bb3ed060d394fc6ffcec67b6972bb21e3 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170923 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 6bbcffe04e8ae73c86bc05c577a67f909857e1c0) Squashed three commits required to get nyan building since some patches were out of order. Added a select to the nyan mainboard Kconfig to have a rom size of 1024K to match the saved config on the chromium side. Change-Id: I346dbb02d216adfea9707e40adf0a4d1e0fabf36 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6669 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-08Haswell/falco/peppy/slippy: continue to clean up FUI.Ronald G. Minnich
As a first step towards removing hardcodes from the FUI support, change the haswell call to i915_lightup to panel_lightup, and pass the intel_dp * as a parameter. Get rid of the scalar arguments and make them part of intel_dp. Get rid of file-scope variables and use the ones in the intel_dp struct. In falco, use functions that peppy uses. Drop slippy support for FUI, it's a dead board; if this is ok I'll remove the files next. And, incidentally, fix the broken RGBX constant and change it to BGRX. Change-Id: I46ef5a9ed8433382d042066ee3542af04cfc319a Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/174932 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 1e1ed410b445c8e2b7411e163d9d6f61499dc3f6) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6833 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-09-08FALCO: stop using the slippy graphics codeRonald G. Minnich
It's time to start cleaning up the falco graphics code, but it needs to have its own files, not slippy's. Change-Id: I7dbe27eafbf247b5c7806819bf0059d8b10e842c Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/172501 Tested-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 262a0c16a39871d14972a92bff2dbc24de2ca3f0) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-08samus: Disable SMBus controllerDuncan Laurie
Nothing is connected to this port. Change-Id: If3e466a3053fa694a511c2335c16381f77f56f47 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174089 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5ddb6a444d5c3141868eaf618ecb014b0262a796) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6827 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-09-08samus: Tweaks from bringupDuncan Laurie
- GPIO29 is no longer connected so we don't need the SMI workaround on the entry to sleep states. - Disable touchscreen wake source until the kernel driver is working so it does not wake immediately. - Update a few GPIOs and disable the codec for now as it is leaking into the 1.8V DDR rail. Change-Id: Ia67b17eb4a097627befd8f39aadc939da1bf3d40 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174122 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 0fdc9a83a434378499f825d072ce0adba5ffda59) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6829 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-08samus: Fix up memory SPD informationDuncan Laurie
The LPDDR3 memory is x32 and dual rank with 14 row bits. In addition the memory is actually elpida, even though they are owned by micron it is confusing to label it as such. And the ram strap options were inverted from what I expected so the memory table needs to be updated. Change-Id: Ia29a23e8140d884fb84f940806f041b40562aab9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174121 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 0d63d36b8035165f95db798ed40488519e622a65) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6828 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-08samus: Add onboard device configurationDuncan Laurie
Change-Id: Ib7b6688982e9f74cffe40d11d4a9ec69acd55d37 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174088 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 41624b073fb59b1372ee5a8eba3ed64c7e633311) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6826 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-08samus: Change thermal behavior to match other haswell platformsDuncan Laurie
Change-Id: Ia835f16b156949f1841210c4a469223d5df28a54 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174087 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 8e51d1d74cdcadde9cbf10e8321d601b099c46bc) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6825 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-05Consolidate intel vga int15 hooksVladimir Serbinenko
Change-Id: I9366dded98bf15f6da44ce893dd10698ba09fd55 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6820 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-05azalia: Use convenience macros throughoutVladimir Serbinenko
Change-Id: Ic044bf155bfcf93fa7cf3afd7287b7d0b615ef6d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6839 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-01google/link: Use common i915_reg.h.Vladimir Serbinenko
Checked by comparing binaries and seeing no differences other than build info. Change-Id: Ie702c540a18b50d6da0379f7c4e65adf3e4f18d4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6819 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-01stout: Kill dead i915 filesVladimir Serbinenko
Not referenced anywhere. Change-Id: I6529f2ecbc34a2fa9ca720fea1224670eb98bdcd Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6815 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-31samus: Change SPD to indicate LPDDRDuncan Laurie
There is some magic new SPD SDRAM type 241 to indicate LPDDR. I cannot find it specificed in any JEDEC document but it is what the reference code uses. Change-Id: I21d7a943784435cb336ecdba7ca5eac0bf5fcd92 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171900 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 0a1385515c62fd1e534b12568df8aaf2170e06f4) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6777 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-08-29samus: Add ACPI MADT interrupt override for GPIO IRQ 14Duncan Laurie
This interrupt needs to be specified in the MADT before it can be used by the kernel driver. Change-Id: Ic920a792a203cb06cd4529815680584a21532106 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171902 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit a330fddb62cb6346ad66ceb5b5c32b66aecd81e2) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6778 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-29samus: Add coreboot boardDuncan Laurie
Add the coreboot board files for samus - Based on Bolt - GPIO setup based on 0.91 schematic - Support both memory types - No HDA verb table for this platform - Some GPIO interrupts are shared and need to be passed to OS Change-Id: I8dbd7639456c631a0115b03a493d94b5e2361ab5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171694 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 249a74c628264e3d4ce754803ede31238404b4d5) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6775 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-28Peppy/Haswell: move more support functions from mainboard to the intel i915 ↵Ronald G. Minnich
driver Move (and rename to make it clearer) the function that computes display parameters from the dpcd and edid. Change-Id: Idfbb56fd312b23c742c52abca1a34ae117a8fece Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/171366 Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 8f2b3bafee7cb05db8fae1c52fc9e1ee64e5e35d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6768 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-26armv7: Move Exynos from 'cpu' to 'soc'.Hung-Te Lin
The Exynos family and most ARM products are SoC, not just CPU. We used to put ARM code in src/cpu to avoid polluting the code base for what was essentially an experiment at the time. Now that it's past the experimental phase and we're going to see more SoCs (including intel/baytrail) in coreboot. Change-Id: I5ea1f822664244edf5f77087bc8018d7c535f81c Reviewed-on: https://chromium-review.googlesource.com/170891 Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit c8bb8fe0b20be37465f93c738d80e7e43033670a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6739 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-26Peppy, Haswell: refactor and create set_translation_table function in ↵Ronald G. Minnich
haswell/gma.c The code to set the graphics translation table has been in the mainboards, but should be in the northbridge support code. Move the function, give it a better name, and enable support for > 4 GiB while we're at it, in the remote possibility that we get some 8 GiB haswell boards. Change-Id: I72b4a0a88e53435e00d9b5e945479a51bd205130 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/171160 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit d5a429498147c479eb51477927e146de809effce) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6741 Tested-by: build bot (Jenkins)
2014-08-25intel/gma: Clarify code and use dedicated init for Google PeppyRonald G. Minnich
Peppy had some issues with FUI. We decided it was time to create peppy-specific gma.c and i915io.c files. Using yabel and the i915tool, we generated a replay attack, then interpolated against the slippy i915io.c to get something working. Also, in preparation for moving code out of the mainboard gma.c to generic driver code, we got rid of some hardcodes in the mainboard gma.c that have no business being there. The worst were the computation of gmch_[m,n] and it turns out that we had some long-standing bugs related to confusion about 'bpp'. I've killed the word bpp everywhere I could because there are at least 3 things that correspond to bpp. We now have framebuffer, pipe, and panel bpp. The names are long because I want to avoid all the mistakes we've all been making in the last year :-) Sadly, that means a lot of changes not just peppy-related, but they are simple and in a good cause. The test pattern generation is driven by a global variable in mainboard/peppy/gma.c. I've found in the past that it's very useful to have a function like this available, as one can activate it while using a jtag debugger: halt at the right place in ramstage, set the variable to 1, continue. It's not enough code to worry about always including. The last hard-codes for M and N registers are gone, and the function to set from generic intel_dp.c code works. To avoid screen trash on a dev mode boot, which we liked but nobody else did :-), we now take the time to put a pleasing background color that sort of doubles as a power LED. Rough timing is ramstage start is at 2.2, and dev setup is done at 3.3. These new platforms are depressingly slow to boot. Rom init alone is taking 1.9 seconds. 13 years ago it was 3 seconds from power on to bash prompt. These CPUs are at least 10x faster and take much longer to get going. Future work, once we get this through, is to move more functions to the intel driver, and combine the mainboard i915io.c into the mainboard gma.c. That separation only existed because i915io.c was generated by a tool, and it had lots of ugliness. Most ugliness is gone. Old-Change-Id: I6a6295b423a41e263f82cef33eacb92a14163321 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/170013 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com> (cherry picked from commit 8cdaf73e3602e15925859866714db4d5ec6c947d) snow: Fix a typo in devicetree.cb that was breaking the snow build. A typo in a recent change broke the snow build. Old-Change-Id: I93074e68eb3d21510d974fd8e9c63b3947285afd Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171014 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 154876c126a6690930141df178485658533096d2) Squashed a fix into the initial patch and updated nehalem/gma.c to have a non-static gtt_poll. Change-Id: I2f4342c610d87335411da1d6d405171dc80c1f14 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6657 Tested-by: build bot (Jenkins)
2014-08-22Remove dead video.aslVladimir Serbinenko
Change-Id: Iadaa6172347ebb7d367d1faa6ed9462fff07d7e6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6730 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18trustzone: Pull trustzone init out of cpu.c and do it in romstage.Gabe Black
Trustzone needs to be initialized/disabled both on boot and on wake, so it needs to be done before ramstage which doesn't run on wake. cpu.c isn't compiled into romstage and fixing that causes other problems, so the trustzone functions were split out. Change-Id: I8fc630237ebec1f02a91600f8baf3d4e9ea66d0e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/169817 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 055ed0e28476123b0bd666109af90baf40aadcee) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6666 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18exynos5: Implement support for USB 3.0 DRD PHYs/controllersJulius Werner
This patch adds support for the DesignWare3 USB 3.0 DRD controller and PHY to the Exynos5250 and Exynos5420 CPUs. It also adds code to the Google Snow and Pit boards to turn these controllers on where applicable. Change-Id: Idcca627363a69f1d65402e1acb9a62b439f077ff Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169452 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit e9809ae12ef8b8bd6cd61d3f604cb9e4718cf7eb) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6642 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18azalia: Move shared variable to separate fileVladimir Serbinenko
Change-Id: Icf46ad1397c67478887c80a627b8f4eb0a67e542 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6695 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-18mainboard/XXX/YYY/dsdt.asl: Whitespace fixMartin Roth
Use tab between "COREBOOT", and comment. This fix was requested in 90957f88 - "mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000" Change-Id: If9fb6158cca95341ab57db1125e85648b616b72c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6601 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-15intel/cpu: rename car.h to romstage.hAaron Durbin
This header has nothing to do with cache-as-ram. Therefore, 'car' is the wrong term to use. It is about providing a prototype for *romstage*. Change-Id: Ibc5bc6f3c38e74d6337c12f246846853ceae4743 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6661 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-14pit: snow: Fix snow, fix up pit write protect.Gabe Black
A recent change to support early firmware selection on ARM broke snow and was incompletely implemented on pit. This change fixes snow by applying the remaining part of the change that had been applied to pit, and also hooks up real values in the get_write_protect_state function. Change-Id: Ifef7ad1bf399f79353daec3dd46973f2b2022e37 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/169120 Reviewed-by: David Hendrix <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 841773e048cd9cfbb64782059c24e29c467f17c8) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6635 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-14Intel: Add common header file for CAR setupEdward O'Callaghan
When passing '-ffreestanding' the 'main' romstage.c may no longer necessarily be considered the entry point. From the C specification in 5.1.2.1 Freestanding environment; "In a freestanding environment (in which C program execution may take place without any benefit of an operating system), the name and type of the function called at program startup are implementation-defined." Clang complains about these being missing as Clang is somewhat more strict about the spec than GNU/GCC is. An advantage here is that a different entry-point type-signature shall now be warned about at compile time. Change-Id: I467001adabd47958c30c9a15e3248e42ed1151f3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5872 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-14exynos5: Refactor crazy old U-Boot base address macros awayJulius Werner
All this samsung_get_base_address_of_device_with_a_really_long_name() boilerplate makes my eyes bleed... I think there are so much cleaner ways to do this. Unfortunately changing this ends up touching nearly every Exynos5 file, but I hope you agree that it's worth it (and the sooner we get it over with, the better... I can't bring myself to make another device fit into that ugly scheme). This also removes the redundant EXYNOS5 base address definitions from the 5420 directory when there are EXYNOS5420 ones, to avoid complete confusion. The new scheme tries to use EXYNOS5 for base addresses and exynos5 for types that are common between the two processors, and EXYNOS5420/exynos5420 for things that have changes (although I probably didn't catch all differences). Change-Id: I87e58434490ed55a9bbe743af1f9bf2520dec13f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167579 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 66c87693352c248eec029c1ce83fb295059e6b5b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6632 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-13Falco: Patch to setup FUI (coreboot initializations) for falcoFurquan Shaikh
For now using the same gma.c and i915io.c files as for slippy Change-Id: Ieb09d0152d525aa090eeb86ebfa253d450d22820 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64373 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 3e119c7e22cb82677754413e56a125f4a372ad54) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6603 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-13Falco: Patch to enable correct port clock selection for dpFurquan Shaikh
This is required only for haswell since the register configs have changed. Also, created mainboard specific header file Original-Change-Id: I61bf8d7cef1f204735a2f72225c48d6e44a99945 Signed-off-by: Furquan Shaikh <furquan@google.com> Conflicts: src/mainboard/google/slippy/gma.c src/mainboard/google/slippy/i915io.c Conflicts: src/mainboard/google/slippy/gma.c Change-Id: I77f2542ca8228358f59aafd99c0d13168ab47fb5 Reviewed-on: https://gerrit.chromium.org/gerrit/66853 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 77f9d1ddd4376e2a290d466f0669a43997492c8e) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6602 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2014-08-13Falco/Slippy: Patch to refactor haswell/gma.c and ↵Furquan Shaikh
mainboard/google/slippy/i915io.c A large portion of documented registers have been initialized using macros. Only a few undocumented registers are left out. i915io.c looks lot more cleaner by removing redundant calls. However, some more work is required to correctly identify which calls are not required. All the io_writes are replaced by gtt_writes. Change-Id: I077a235652c7d5eb90346cd6e15cc48b5161e969 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66204 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 39f3289f68b527575b0a120960ff67f78415815e) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6600 Tested-by: build bot (Jenkins)
2014-08-13chromeos: On ARM platforms VBNV lives in the ECStefan Reinauer
This patch renames the x86 way of doing things to explicitly mention CMOS (which is not available on our ARM platforms) and adds an implementation to get VBNV through the Chrome EC. We might want to refine this further in the future to allow VBNV in the EC even on x86 platforms. Will be fixed when that appears. Also, not all ARM platforms running ChromeOS might use the Google EC in the future, in which case this code will need additional work. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ice09d0e277dbb131f9ad763e762e8877007db901 Reviewed-on: https://chromium-review.googlesource.com/167540 Reviewed-by: David Hendrix <dhendrix@chromium.org> Tested-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 8df6cdbcacb082af88c069ef8b542b44ff21d97a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6616 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-13arm: libpayload: Add cache coherent DMA memory definition and managementJulius Werner
This patch adds a mechanism to set aside a region of cache-coherent (i.e. usually uncached) virtual memory, which can be used to communicate with DMA devices without automatic cache snooping (common on ARM) without the need of explicit flush/invalidation instructions in the driver code. This works by setting aside said region in the (board-specific) page table setup, as exemplary done in this patch for the Snow and Pit boards. It uses a new mechanism for adding board-specific Coreboot table entries to describe this region in an entry with the LB_DMA tag. Libpayload's memory allocator is enhanced to be able to operate on distinct types/regions of memory. It provides dma_malloc() and dma_memalign() functions for use in drivers, which by default just operate on the same heap as their traditional counterparts. However, if the Coreboot table parsing code finds a CB_DMA section, further requests through the dma_xxx() functions will return memory from the region described therein instead. Change-Id: Ia9c249249e936bbc3eb76e7b4822af2230ffb186 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167155 (cherry picked from commit d142ccdcd902a9d6ab4d495fbe6cbe85c61a5f01) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6622 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12Haswell: Lower TJ_MAX to 100C. Adjust critical temps to match.ChromeOS Developer
Change-Id: I3326b6e3c412b6360af37030cefd13d95b704e70 Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180750 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1978b0f91b2e91d2251721c7c6981d51a6930b61) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6615 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12exynos5420: minor clean-up memory related stuffDavid Hendricks
This cleans up a few minor things (mostly #defines) of the memory code for exynos5420, pit, and kirby. Specifically: - CONCONTROL.empty is read-only, so don't try to set it and also get rid of the unneeded DMC_CONCONTROL_EMPTY_ENABLE #define. - MEMBASECONFIG* overlaps members of the mem_timings struct and are mainboard-dependent anyway, so get rid of 'em. - DMC_MEMCONTROL_TP_DISABLE corresponds to a reserved bit. It may have been deprecated. - Same with TIMING* #defines. - Clarify DDR_MODE_* usage and use mem->mem_type when appropriate. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ideb21efcc97b24f7e115e90051c20daef4480f17 Reviewed-on: https://chromium-review.googlesource.com/167500 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 650dba32cb217414c422907398f68e784e5720e8) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6614 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-12exynos5420/pit: re-factor membaseconfig0/1 usageDavid Hendricks
membaseconfig0/1 are utterly dependent on the mainboard's particular DRAM setup. This defines their values in the mem_timings struct for pit. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Ifd782d1229b2418f8ddbf0bcb3f45cc828ac34b0 Reviewed-on: https://chromium-review.googlesource.com/167488 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 80eebd5bc0dbb9fabf81f46c25dcd5c5d5747579) exynos5420: necessary updates for DRAM This updates DRAM usage for Exynos5420 so that we can actually use 3.5GB: - Memory chips used with Exynos5420 may have 16 row address lines. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I86d1a96d0d1a028587f7655f8de5a2e52165e9d2 Reviewed-on: https://chromium-review.googlesource.com/167489 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 04bbaf5d8e125166dd689f656d5b37776be01fb1) Squashed two related commits. Change-Id: I4e45bc8a446715897ec21b0160701152fa6b226b Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6613 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12exynos5420: ddr3: Switch from 4G setup to 2G setup on exynos5420David Hendricks
This changes the number of chip selects that we configure from 2 to 1. On current setups with (x16 memory 4Gbit chips) that means that we're at 2GByte. Technically we should add a second setting in the ares_ddr3_timings and select between the two of the based on board strappings. That would make the CONFIG_RUN_TIME_BANK_NUMBER work properly. I've changed the ddr3_mem_ctrl_init() so it should handle that, but I'm not actually doing the board strapping read right now. This change means that accesses to 0xA0000000 - 0xFFFFFFFF on 2G systems will no longer put the system in a messed up state (leading to a hang). It also prevents some of the weird boot behavior that we've seen that comes and goes depending on U-Boot alignment. See <http://crosbug.com/p/20577>. This patch was ported from: https://gerrit.chromium.org/gerrit/66117 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ib4cfe420aac30bd817438f06d01e8671afc4a27d Reviewed-on: https://chromium-review.googlesource.com/167210 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 0ea574243058068702e3f6bc7355098745d16880) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6612 Tested-by: build bot (Jenkins)
2014-08-12Exynos5420: ddr3: fine tuning the DDR3 timing valuesDavid Hendricks
Fine tuning DDR timings value for better stability * Changed Data Driver Strength from 34 ohms to 30 ohms, expected to enhance signal integrity. * Changed DQ signal from 0xf to 0x1f000f, to keep default value safe. * Changed mrs[2] and added new mrs direct command for setting WL/RL without resetting DLL. * Added explicit reset value write in phy_con0 instead of just setting a bit, to ensure that reset happens. * Added DREX automatic control for ctrl_pd in none read memory state. This is ported from: https://gerrit.chromium.org/gerrit/61405 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I59e96e6dede7b49c6572548aca664d82ad110bb1 Reviewed-on: https://chromium-review.googlesource.com/66995 Reviewed-by: ron minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit ec34b711c6d270672c56d45c370ca14c0aa27ca3) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6611 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-12exynos5: Refactor board-specific parts out of USB PHY codeJulius Werner
This patch moves around some of the existing Exynos5 USB 2.0 PHY code to make it cleaner in preparation of the 3.0 PHYs. It moves the VBUS GPIOs (which are completely board-specific) into the mainboard code and makes sure to only initialize PHYs on the boards that actually need them. It also removes the USB 3.0 PLL hack that was needed on Snow from the Pit and Kirby boards (which do not have that PLL anymore). Change-Id: Ia35f47a765acff60481f0907f7448ec4f78e0937 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66887 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit c3b1a8b687b535f4d5ac1b3bd2a4760151698fdb) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6609 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12exynos5420: Make USB A-A booting work with early data cacheJulius Werner
Apparently the IROM doesn't like data caches... the recently added dcache-in-bootblock makes A-A booting fail, and flushes/invalidations alone don't seem to fix it. It's pretty fast anyway, so we just disable the cache again for the duration of the IROM call. Also removes a superfluous invalidation line from the bootblock code... dcache_mmu_enable/disable already take care of that. Old-Change-Id: I35580d15664c7b4197d4ed14028720147adbf918 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66602 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit e9c28a6a7a88c8286e62764ee5ad2694da2e822f) exynos5: Implement booting from SDMMC media This patch augments the alternative CBFS media source implementation for Exynos5250 and Exynos5420 to allow booting from SDMMC devices (such as an SD or uSD card reader, if available). It also moves MMC initialization for the Snow, Pit and Kirby boards from romstage to ramstage (mainboard_init) to prevent it from interfering with the IROM during SDMMC boot. Old-Change-Id: Ic4adef80c28262d084a53c28ec59aa7ac3af50c8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66154 (cherry picked from commit 08de13b72432c076e3327c048df93d89d52b0ecc) snow and pit: turn on FET4 (for SD card) at bootup Explictly enable FET4 on Snow and Pit. Historically we haven't needed to do this because: * On snow there's a bypass around FET4 which effectively eliminates it. Even if we don't turn on FET4 the SD card is still powered. Turning on FET4 doesn't hurt though and is technically correct. * On pit the EC turns on FET4 on cold bootup. On pit we run into a problem if the kernel turns off FET4 like in <https://gerrit.chromium.org/gerrit/#/c/65332/> and then we get a software reset or warm reset. In this case the EC won't know to turn it back on. This was ported from: https://gerrit.chromium.org/gerrit/#/c/65673 Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I57337f12b38889e6afee8577cf8807ec4c41e91c Reviewed-on: https://gerrit.chromium.org/gerrit/66786 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit e910117047d898b6b1d0dc965ef2ec0237d17646) Squashed three commits for alternate cbfs SD support. Change-Id: Idbd1fd4776cbf8cb20d03e6b691104cd8540a1ec Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6530 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-10bolt: Set GPIO29 as input in S0, output+high in S3/S5Duncan Laurie
This resolves WiFi issues after suspend/resume. It needs related SPI descriptor soft strap change to enable SLP_WLAN as a GPIO instead of owned by the ME. Change-Id: I03f4458d1e52a913770d391061baa6cfa41e8558 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170577 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit cf1fe0524ad4793c8c422dc3fed3007b7fc96038) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6533 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-10falco: Add support for Samsung memoryDuncan Laurie
New SPD and update to the SPD map. Add both a 4GB and 2GB option. 4GB = RAM_ID{1,1,0} 2GB = RAM_ID{1,1,1} Original-Change-Id: I37318c1b5a6ee84b7c55da00d326f10fe8af6f1e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 7eb5a4ef1062a34e883c3f356ab0dc00ba07910d) Change-Id: I0f35a7f5191fefeb5910a2d28aea153516d9a11d Reviewed-on: https://chromium-review.googlesource.com/171693 Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit b02fa777aa5935021b2c69f7345dffd111cbd118) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6545 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-10Falco/Slippy: Patch to remove redundant graphics initializationsFurquan Shaikh
gma_fui_init repeats the initializations already performed in gma_setup_panel. These redundant initializations reset any gtt settings done before this call. Hence, they had to be done again after call to gma_fui_init. However, the call gma_fui_init is not required at all. Does not affect the behavior of suspend/resume. Old-Change-Id: Idfb9f9930624694b878ddc0fe8648b3c8dd80e55 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65997 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit c376aea1b89c9a829874d5c657693993a3bb1f13) Falco/Slippy: Patch to fix garbage on screen during graphics initialization in normal mode Depending on the init_fb parameter: 1) For normal mode, first page is filled with zeroes and setgtt is used make all GTT entries point to this same page 2) For developer/recovery mode, we init the gtt to consecutive pages Old-Change-Id: I281b0b7efe01f7892e98b19ff9a63c04b087bd2c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65633 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 97c99dfe52ef3a87d387fdbf27ad3a28ad81c722) Squashed two graphics related commits for Falco/Slippy. Change-Id: I7ddb92672c026fe66f9fb0caba9d8fdc3f8a9d0a Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6536 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-08falco: Remove RTD2132 chip and setup from devicetreeDuncan Laurie
This disables the spread spectrum clock and avoids errata. Old-Change-Id: I04eb767f1587bb64a215a92b66cd05e099d29964 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66673 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit a7bf0d818c431221f4d014e3a0130bec8db7406e) falco: Remove RTD2132 driver from kconfig Original-Change-Id: I89ad9fbfbc58878602ed85ada918524426b5bc77 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66946 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1d732eb5e4743546b8ed50c8c44965a687f61ab2) Conflicts: src/mainboard/google/falco/Kconfig Old-Change-Id: I317a0741779e272ad72b7272ef6f4a67abd66698 Reviewed-on: https://chromium-review.googlesource.com/167311 Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit ffa6c89fbac04b4b6fceafd4ba97d39a285c4aa3) Squashed two commits and corrected the subject line from 2312 to 2132. Change-Id: If4f1e59999b70efe2de45522ba78051d9ed88dd7 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6527 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 03:54:07 +0000