summaryrefslogtreecommitdiff
path: root/src/mainboard/google
AgeCommit message (Collapse)Author
2022-08-07mb/google/brya/variants/agah: update dptf settingTony Huang
1. Add active policy 2. Set critical policy trigger point to 105C 3. Correct TSR location BUG=b:240634844 TEST=emerge-draco coreboot values provided and verified by thermal team Change-Id: I0d91bad03cbdeea5c84b533580ac98072ce0110b Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-08-07mb/google/brya/acpi: Fix PERST# handling in GC6 exitTim Wawrzynczak
PERST# is supposed to be de-asserted in GC6 exit, but the original patch used the CTXS Method, which drives a GPIO low, instead of STXS, because PERST# is active-low. This patch fixes that. BUG=b:214581763 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib0adb8efe5e2cc733ae2228614c58c124ba3f11b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-07mb/google/brya/var/ghost: Disable LID_SHUTDOWNCaveh Jalali
The lid sensor is on a daughterboard which can cause unintended shutdowns when not connected. Disable lid sensor based shutdown behavior in depthcharge until we have a better solution. BUG=b:240005819 BRANCH=firmware-brya-14505.B TEST=booted ghost, no longer shuts down due to missing lid sensor Change-Id: I69f70255dee1b69e05b112c0174f5f52d1368837 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-07mb/google/brya/acpi: Fix NVJT subfunction IDsTim Wawrzynczak
The POWERCONTROL and PLATPOLICY NVJT subfunctions were incorrectly set to 2 and 3, respectively. While looking at the ACPI code, Nvidia noticed these are supposed to be 3 and 4, also respectively, so this patch fixes that. BUG=b:214581763 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0f808aba7072b943ee2fad20e06ff39a9b54903d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-06mb/google/rex: Add memory config for rexTarun Tuli
Configure the rcomp, dqs and dq tables based on the schematic dated July 17/2022 and Intel Kit #573387. TEST=Built successfully Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I092f42db252052382d377a4ae48dc25f73080a3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66202 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-05mb/google/brya/var/vell: Set GPP_B2 NC for RGB keybaordRobert Chen
When GPP_B2 output high, there is a leakage path. This patch fix it by setting the pin NC. BUG=b:233959105 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I3c833d5d62c715960dcb27494a0b9b93c91e8f2f Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-08-03mb/google/skyrim: Enable PSP verstageKarthikeyan Ramasubramanian
Enabling required config items to execute verstage in PSP. BUG=b:217414563 TEST=Build and boot to OS in Skyrim with PSP verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Iee14dc80cb6691acb5cb59a21da5a3dff69f7dd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66135 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-03mb/google/geralt: Implement SKU ID and RAM codeRex-BC Chen
- Retrieve the SKU ID for Geralt via CBI interface. If that failed (or no data found), fall back to ADC channels for SKU ID. - The RAM code is implemented by the resistor straps that we can read and decode from ADC. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I31626e44bd873a3866c9bd1d511b476737f15a20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66275 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-03mb/google/geralt: Configure GPIOsRex-BC Chen
Configure ChromeOS specific GPIOs: - Open-drain pins to high-z mode: GPIO_EC_AP_INT_ODL, GPIO_GSC_AP_INT_ODL and GPIO_WP_ODL. - GPO mode: GPIO_AP_EC_WARM_RST_REQ, GPIO_EN_SPKR and GPIO_XHCI_INIT_DONE. This patch is based on MT8188G_GPIO_Formal_Application_Spec_V0.3. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I84d3f62ec8a3966fe1982d5d4cf6ff270450d4bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/66274 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-03mb/google/geralt: Configure TPMRex-BC Chen
Initialize I2C bus 1 for TPM control. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: If5807c9bb39260315ecbc55305def483bd2b8c51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66273 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-03mb/google/dedede/var/beadrix: Update SoC gpio pin of DMICTeddy Shih
Update SoC GPIO setting of unused DMIC channel according to beadrix schematics. GPP_S2 : NF2 -> NC (DMIC1_CLK) GPP_S3 : NF2 -> NC (DMIC1_DATA) BUG=b:203113413, b:237224862 BRANCH=None TEST=on beadrix, validated by beadrix's DMIC working properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Ibe2f432cd74b546218ff4ee6e428e9eed9ac611f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-03mb/google/dedede/var/drawcia: Add Wifi SAR for oscinoShon Wang
Add wifi sar for oscino BUG=b:240373077 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Cq-Depend: chrome-internal:4893022 Change-Id: I44cbe8ee08d6136ed116623046893c9749795e50 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66176 Reviewed-by: Ivan Chen <yulunchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-03mb/google/dedede/var/beadrix: Update SoC gpio pin of BC1.2Teddy Shih
Update SoC GPIO setting of adding BC1.2 SLGC55545 according to beadrix schematics. GPP_A18 : NC -> NF1 (USB_OC0_N) BUG=b:214393595, b:226294980 BRANCH=None TEST=on beadrix, validated by beadrix's Type A working properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I746931582cc12f49f7f1c667563350ebac8ddfa1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-03mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9755 for kuldaxDavid Wu
Enable DRIVERS_GENESYSLOGIC_GL9755 support for kuldax. BUG=b:232858957 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I1b2c0bff8497d727c697ea6287078055a39bd1f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-08-03mb/google/brya/variants/agah: set tcc_offset to 3Tony Huang
Set tcc_offset value to 3 in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUG=b:240600260 TEST=emerge-draco coreboot verified by thermal team Change-Id: I3044643d52f1d6e883beb3ec87a77f32d086f46c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-08-03mb/google/herobrine: Add support to enable displayVinod Polimera
This change adds support to enable edp gpios, display init for herobrine. BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Monitor name: LQ140M1JW49 Change-Id: I01dbe23afbb3d41d87f24cb7dcfa456cb7f133fb Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64885 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-02mb/google/dedede/var/pirika: Add Elan touchscreen supportFrankChu
Enable I2C2 and register touchscreen ACPI device for pirika. BUG=b:236564261 TEST=touch screen is functional. Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Id2fd5606b7126eabc1c88bf516198ff00b5d75dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-02mb/google/brya/var/ghost: Enable AMP powerEric Lai
Follow latest schematic, GPP_A17 is used to enable AMP power. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=Check I2C scan can see the AMP return ACK. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ia6c52302a12ddec68303714ac07e96a65a8f8fb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-08-02mb/google/geralt: Enable Chrome ECRex-BC Chen
Initialize SPI bus 0 for Chrome EC control. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I6de5ea8a0273a3b0c725e4cdbcf69f4db74c5db7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-02mb/google/nissa/craask: Add eMMC DLL tuning valueSimon Yang
Configure eMMC DLL tuning values for Craask board. BUG=b:238985924 TEST="Use the value to boot on Nivviks and Craask successfully." Change-Id: I14f3e2329404cca94e14034d1fb52fcb99a2ddc9 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66218 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-08-02mb/google/rex: Enable CSE Lite SKUSubrata Banik
The first CSE Lite SKU is available, therefore enable the Kconfig option to have the CSE reboot the system into its RW FW during a cold boot. BUG=b:240228892 TEST=TBD Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I00ef4176cf08cbeed06e446cfe68f06cb1ea27b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66287 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01mb/google/herobrine: Add PCIe domain supportVeerabhadrarao Badiganti
Add PCIe domain support for herobrine by enabling it in the devicetree. BUG=b:182963902,b:216686574,b:181098581 TEST=Verified on Qualcomm sc7280 development board with NVMe card (Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is getting detected in response to 'storage init' command in depthcharge CLI prompt. Output logs: ->dpch: storage init Initializing NVMe controller 1e0f:0001 Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0 * 0: NVMe Namespace 1 1 devices total Also verified NVMe boot path, that is depthcharge is able to load the kernel image from NVMe storage. Change-Id: Ied8fbbc8d20698ee081d93ba184b7d0291bb6a76 Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65137 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01mb/google/brya: Disable the Package C-state demotionZhixing Ma
Disabling the Package C-state demotion feature for brya baseboard as a work around to the S0ix issue and also this doesn't have any impact on the power and performance measured and verified by the PNP team. This feature will be enabled after its functionality is verified with no issues and also based on its impact on PNP. BUG=none BRANCH=firmware-brya-14505.B TEST=Boot and verified that S0ix issue is resolved. Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: Id3941c8870d41b25488c8ac5d38534fa94664d4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-30mb/google/brask/variants/moli: Add DPTF setting in MoliRaihow Shi
DPTF Policy and temperature sensor values from thermal team. BUG=b:236294162 TEST=emerge-brask coreboot Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Iebcfb74c4bc719e6d8d8d9317435becd912eaf85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-07-29mb/google/rex: Perform display configuration overrideSubrata Banik
This patch enables display port configuration as per the Rex schematics. TEST=Able to dump FSP UPD to ensure the override is successful. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9e81d037416e46e52cb72344425d6d8725dae192 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-07-29mb/google/nissa/var/pujjo: Enable OZ711LV2LN SD card controllerStanley Wu
Pujjoflex support OZ711LV2LN SD card controller, Select the Bayhub LV2 driver for OZ711LV2LN SD card. BUG=b:215487382 TEST=Build FW and checking SD card work as expected in OS. Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I6759fde1eaf24599a1fdb364d6e78f4e4e12f311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-29mb/google/rex: Add LP5 RAM IDsTarun Tuli
Create RAM IDs for: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D2DS-026 WT:B 1 (0001) MT62F2G32D4DS-026 WT:B 2 (0010) BUG=b:240289148 TEST=emerge-rex coreboot Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Ib24e07bca363984db3484aa500f7d6ea4817e517 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-07-29mb/google/geralt: Initialize RTC and clk_buf in romstageRex-BC Chen
TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I869c0879d09e00cf66882adb728c9ccb6ac57e03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66183 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-29mb/google/rex: Enable CNVi BT CoreSubrata Banik
This patch override `CnviBtCore` FSP UPD. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I90c9b360969aada0b0e031d62b48476fac5cee0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-29mb/google/brya/var/ghost: Enable CS42L42 codecEric Lai
Add CS42L42 support in device tree. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=Check cs42l42 driver can probe successfully in kernel. cs42l42 i2c-10134242:00: Cirrus Logic CS42L42, Revision: B1 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I861f47c12f4cebb016a4cfbe225f97d34d55e233 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-07-29mb/google/brya/var/ghost: Update all I2C buses speed to fastEric Lai
Remove the parameter and set I2C bus speed to fast. Will fill the tuning value after real tuning. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Iba7fe4551959617ecfa49719c1124bf85d624c31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-07-29mb/google/brya: Create gaelin variantRaymond Chung
Create the gaelin variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:239514438 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_GAELIN Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Change-Id: I7f1ff8690c7c57f8960e004d0490d5cede8667f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-07-29mb/google/dedede/var/drawcia: Enable weida touchscreenShon Wang
Add weida touchscreen support for drawcia. BRANCH=dedede TEST=Build and verify that touchscreen works on drawcia. Change-Id: Ic76f3529771c6eeeafef7ca50fc400065aac2211 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65471 Reviewed-by: Ivan Chen <yulunchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-07-28mb/google/nissa/var/joxer: Correct i2c address for touchscreenMark Hsieh
set i2c address to 0x14 for Goodix touchscreen BUG=b:239180430 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I11a2d9c684bc511b3942f88f74a2495e796bc3c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-28mb/google/brya/acpi: Add L23 entry/exit sequences during dGPU GCOFFTim Wawrzynczak
When the dGPU is entering GCOFF, the link should first be placed into L2/L3 as appropriate for the design, then when exiting, the link should be placed back into L0. This patch fixes that oversight. BUG=b:239719056 TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia3bdfe5641216675e06ebe82ffe58bf8c049b26b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-28mb/google/brya/var/agah: Modify GPP_A8 programmingTim Wawrzynczak
The EEs noticed this pin was misbehaving; it was accidentally set to a low output, but should be open-drain (NC). This patch fixes that. BUG=b:237837108 TEST=verified by EEs Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie76a951320c49b9fbc1f23b96f04c9f86ad44d42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-28mb/google/brya/var/agah: Modify GPP_F14 programmingTim Wawrzynczak
For some yet unknown reason, when this GPIO is locked, there is an interrupt storm for IRQ #9 apparently caused by GPE 0x66. GPP_F14 is set to GPE 0x64 on the ADL platform, so this doesn't quite make sense. This patch removes the lock and fixes this IRQ storm, but the root cause is not identified yet. BUG=b:236997604 TEST=`grep ' 9:' /proc/interrupts` shows a reasonable value now Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I3d1c66fac80a173798ae33e48b1776d9f4fb5eaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/66201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-07-28mb/google/brya/var/agah: Optimize dGPU GCOFF entryTim Wawrzynczak
After staring at lots of scope shots, the EE has determined that a few modifications to the GCOFF sequence can be made: - Remove delay between PERST# assertion and GPU_ALLRAILS_PG deassertion - Remove delay after ramping down FBVDD This patch implements these minor changes. BUG=b:240199017 TEST=verified by EE Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7d492b3e65a231bc5f64fe9c3add60b5e72eb072 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-28mb/google/brya/var/agah: Update ASPM settings for dGPUTim Wawrzynczak
After some debugging, it has been determined that the ASPM L0s substate is functional, but there is still some problem with ASPM L1 substates, so this patch updates ASPM status for the dGPU from disabled to L0s only. BUG=b:240390998 TEST=tested with nvidia tools Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I584bdbf26eda20246034263446492bf4daf5f3b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-28mb/google/brya/var/anahera{4es}: Add H54G68CYRBX248 supportWisley Chen
Generate SPD id for hynix H54G68CYRBX248 BUG=b:239899929 BRANCH=firmware-brya-14505.B TEST=run part_id_gen to generate SPD id Change-Id: I96babe340678ca9b82b06d3193b93a7676f23fef Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-28mb/google/brya/var/redrix{4es}: Add H54G68CYRBX248 supportWisley Chen
Generate SPD id for Hynix H54G68CYRBX248 BUG=b:239888704 BRANCH=firmware-brya-14505.B TEST=run part_id_gen to generate SPD id Change-Id: I9412b988bcdb0c744e016f3add6dacda8185d6db Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-28mb/google/brya/var/ghost: Correct CNVi pinsEric Lai
GPP_F0 to GPP_F4 is for CNVi and should be NF1. GPP_F5 is for CNVi CLK_REQ, and should be NF3 CRF_XTAL_CLKREQ. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=CNVi wifi can get probed in kernel. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ice3fde3a457f6f5c058c0a7d3ca2e63775bda96c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
2022-07-28google/trogdor: Add new variant Pazquel360Yunlong Jia
This patch adds a new variant called Pazquel360 \ that is identical to Pazquel for now. BUG=b:239987191 TEST=make Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I0a9ca4a59fb44256d0d8fcdbdf2a7db533c84412 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Bob Moragues <moragues@google.com>
2022-07-28mb/google/rex: Initial setup for ramstage/early gpio configTarun Tuli
This adds the initial gpio configuration for the rex initial variant. BUG=b:238165977 TEST=Boots and no errors on simics Change-Id: I55ab31c7943e22df9cec8db4a9f0c3ab6f065ae1 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65952 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-27mb/google/brya/crota: Remove MAC address passthru supportFranklin Lin
ChromeOS connection manager (shill) already has support for dock MAC address passthrough, therefore remove the code to pass a dock's MAC address in ACPI. BUG=b:235045188 TEST=build coreboot Signed-off-by: Franklin Lin <franklin_lin@wistron.corp-partner.google.com> Change-Id: I78320a7c6b0fd5392e24b63bff234229a3f4b9bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/66040 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-27mb/google/brya/var/ghost: Update memory DQ mapEric Lai
Follow latest schematic 6/27 to update the DQ map. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I8d0de04a001cab53a245185707ebc9da7a501ec4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66122 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-07-27mb/google/nissa/var/craask: Add DPTF passive and critical policiesTyler Wang
Add critical, passive policy, and pl values from thermal team. BUG=b:239495499 TEST=Build and test on MB, system can boot to OS. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I8beb3b57ff56c6fe413bb0e3dd43d693aee08e36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66125 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-07-27mb/google/nissa/var/pujjo: Enable PCIe port 4 for WLANLeo Chou
Pujjo support WLAN device, enable PCIe port 4 for WLAN device BUG=b:239899932 TEST=Build and boot on pujjo Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ic8b7240941cf87a4f27963d50fffe28875114a81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66073 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-27mb/google/cherry: Introduce mainboard_needs_pcie_initYu-Ping Wu
Implement mainboard_needs_pcie_init() for cherry as a callback for mt8195 SoC to determine whether to initialize PCIe. When the SKU id is unknown or unprovisioned (for example at the beginning of the factory flow), we should still initialize PCIe. Otherwise the devices with NVMe will fail to boot. BUG=b:238850212 TEST=emerge-cherry coreboot BRANCH=cherry Change-Id: I2ed0ceeb37d2924ca16485fb2d130959a7eff102 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-07-26mb/google/brask/var/kuldax: correct Type-A USB3 port0/1 tx_de_empDavid Wu
1. Set Type-A USB3 port0/1 tx_de_emp to 0x2B to fix the USB3 Gen2 RX signal integrity issue. 2. Disable unused USB port. BUG=b:238230292 TEST=build FW and check Type-A USB3 port0/port1 RX pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I8356ca30a965e5774a1556c5cb81e1586c55496c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-26mb/google/nissa/var/joxer: Configure descriptor for eMMC or UFSReka Norman
Joxer will have both eMMC and UFS SKUs, which require different settings in the descriptor. So update the descriptor at run-time based on fw_config. By default, the descriptor is configured for UFS. This configuration still boots fine on eMMC SKUs, it just might cause problems with S0ix. This is a temporary workaround. It will be removed once we've implemented a proper solution for configuring the descriptor differently for different SKUs. BUG=b:238234376 TEST=Make an identical change for nivviks. On both nivviks (eMMC) and nirwen (UFS), check that it boots and that the logs show the descriptor being configured as expected. Change-Id: I14232eb773936f2ecd183687208d332136935601 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-07-25mb/google/rex: Set GPIO Tier-1 GPEs in devicetreeKapil Porwal
Set GPE route as GPE0_DW0 -> GPP_A GPE0_DW1 -> GPP_E GPE0_DW2 -> GPP_F BUG=b:224325352 TEST=Verified in emulator that there is no regression Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I5e3e09cfc06d2556ea32cca23b3dae114a510498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-25mb/google/rex: Override LP5 CCC configSubrata Banik
This patch overrides `Lp5CccConfig` UPD as per the CCC mapping data captured from the Rex schematics dated 07/16. BUG=b:224325352 TEST=Able to build Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia1d9e3665cff74a803e730c76f62773996efb3dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/66049 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-25mb/google/nissa/var/pujjo: Add new supported memory partLeo Chou
Add pujjo new supported memory parts in mem_parts_used.txt. Generate SPD id for this part. Micron MT62F1G32D4DR-031 WT:B BUG=b:239776504 TEST=Use part_id_gen to generate related settings Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I95eb194ecbd5d39f66eb566132e75af056899325 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66039 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-07-25mb/google/rex: Add memory configuration board strapsSubrata Banik
This patch reads various memory configuration GPIOs to fill in below details: 1. variant_memory_sku() 2. variant_is_half_populated() BUG=b:224325352 TEST=Able to build Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I23bad8c78523cb56008e6d67e7776e57e42fbeb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-07-23mb/google/rex: Add GBB related configsSubrata Banik
This patch adds more GBB related configs. Select `HAS_RECOVERY_MRC_CACHE` config. Additionally, move VBOOT_LID_SWITCH config under VBOOT config. TEST=Able to build the Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I28976200cbd70dc23f58868ee89c0ac700793be9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66007 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-07-23mb/google/brya/var/skolas4es: Correct _PLD valuesNick Vaccaro
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C2 | | A0 C0 | MLB DB | C1 | | +----------------+ BUG=b:216490477 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I96202b9ac9586975e960d6577d279c995c67f34e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66031 Reviewed-by: Won Chung <wonchung@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-23mb/google/skyrim/var/skyrim: Add two supported memory partsAmanda Huang
Add two memory parts and generate the associated DRAM part ID. 1) Hynix H9JCNNNBK3MLYR-N6E 2) Hynix H58G56AK6BX069 BUG=b:228415394 TEST=none Change-Id: I0f5ca291e02e209032e2533f4b2d4241b5e62e42 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-07-23mb/google/nissa/var/xivu: Disable WFC and pen garage based on fw_configIan Feng
Use fw_config Bit 0 and Bit 1 to control: Bit 0 = 0 --> enable WFC Bit 0 = 1 --> disable WFC Bit 1 = 0 --> enable pen garage wake Bit 1 = 1 --> disable pen garage wake BUG=b:238045498 TEST=emerge-nissa coreboot chromeos-bootimage Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I85bc4753bfd16fd460286aa2b3bb5f3341049f61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-22mb/google/brya/var/skolas4es: add WFC definitions to fw_configNick Vaccaro
Reserve bits 15 and 16 in the fw_config to be used to specify WFC population status. Possible values for field WFC bits include: option WFC_ABSENT 0 option_WFC_MIPI_OVTI5675 1 option WFC_MIPI_OVTI8856 2 BUG=b:239613517 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot' and make sure it compiles successfully. Change-Id: If797b79f0d094816eeb3df7bfded06e92e4e6a32 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-22mb/google/rex: Add TPM device to Kconfig and devicetreeKapil Porwal
Add TPM device for Rex. Device details: I2C Controller/Bus = 4 I2C Slave Address = 0x50 GPE = GPE0_DW1_03/GPP_E03 BUG=b:224325352 TEST=Verified in emulator that there is no regression Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ifa3a5b503a203e3900049f27a54025156e22a285 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66014 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22Revert "mb/google/brya/var/kinox: Configure TDC current"Dtrain Hsu
This reverts commit 58f68fb0cb8e9824256a115d1ebdc840c281e987. Reason for revert: ODM thermal team request that change IA/GT TDC current back to 20A. BUG=b:237230877 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I6a5cfdc18afb6fe43a3d630e5fa3d77c19640fc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.corp-partner.google.com> Reviewed-by: Vinay Kumar <vinay.kumar@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
2022-07-22mb/google/rex: Enable EC_GOOGLE_CHROMEEC_BOARDID KconfigTarun Tuli
Enables the EC_GOOGLE_CHROMEEC_BOARDID feature so we can read board_id() on rex. TEST=Verified builds succeed and code is linked Change-Id: Id202019519fc4a05c80374bc97663e59fdca3d76 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66018 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-22mb/google/geralt: Add eMMC and SD card configurationsAndy-ld Lu
Geralt reference design has both eMMC and SD card interfaces, so we configure both in mainboard_init() in ramstage. TEST=boot to kernel using emmc successfully. BUG=b:236331724 Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.corp-partner.google.com> Change-Id: I200a065ab96584d824153480e594e19baae97f9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65976 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22mb/google/geralt: Implement regulator interfaceHui Liu
Control regulator more easily with regulator interface. TEST=measure 3.0V in VMCH and VMC. BUG=b:236331724 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I9727475774b3b9a8dcd49e5e60e133f9d745b407 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65875 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22mb/google/brya/var/ghost: Split ghost4adl into 3 variantsJack Rosenthal
We plan to make 3 firmwares which differ only by Kconfig options and can share a common variant directory. ghost4adl: Board with an ADL chip. ghost4es: Board near identical but has RPL-ES chip. ghost: Will have final RPL silicon. Since they will only differ by Kconfig options and Intel binary blobs, let's not duplicate the variant directory but instead share it in common. BUG=b:239456576 BRANCH=firmware-brya-14505.B TEST="make menuconfig", verify layout of board selection Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I94f2048bbe6675a807f8eba986a1ded0a4167733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-22mb/google/brask/variants/moli: set customized_leds for RTL8111KRaihow Shi
Follow the LED modification request in ADL_Moli_SC_MB_2022_0601.pdf and set the customized_leds to 0x0482 based on 7.4 Customizable LED Configuration in "REALTEK+RTL8111K-CG+SPEC+0116" for RTL8111K in moli. BUG=b:218985167 TEST=emerge-brask coreboot and check RTL8111K LED behaviour Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ia154d15ecf14b32a4d589abf27b9573693339a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65958 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22mb/google/brya/var/brya0: add WFC definitions to fw_configNick Vaccaro
Reserve bits 15 and 16 in the fw_config to be used to specify WFC population status. Possible values for field WFC bits include: option WFC_ABSENT 0 option_WFC_MIPI_OVTI5675 1 option WFC_MIPI_OVTI8856 2 BUG=b:239613517 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot' and make sure it compiles successfully. Change-Id: I23bdaf7feaff2e6a4979c3da789ab877e6ac3af2 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-22mb/google/kahlee: Increase VRAM from 16 to 32 MiBMatt DeVillier (AMD)
While adequate for ChromeOS, 16MiB VRAM is insufficient for current mainline Linux and Windows amdgpu drivers to operate properly. Under Linux, the driver fails to allocate a framebuffer and causes multiple kernel panics. Under Windows, the driver fails to load due to insufficient resources available. Revert the VRAM allocation to the previous amount of 32MiB. This change reverts commit 87dcd0061af4 ("mainboard/google/kahlee: Reduce VRAM to 16MB") Test: build/boot Linux 5.17.x on google/liara, verify framebuffer allocation succeeds and no kernel panic reported. Change-Id: I1967a203fed80456a20af00943eba21bc1c0577b Signed-off-by: Matt DeVillier (AMD) <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66022 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22mb/google/brya/acpi: Poll more frequently in GPPLTim Wawrzynczak
The full dGPU power-on sequence, when executed from ACPI, is taking roughly 15ms or so, which puts it close to the maximum of 20ms required from the Nvidia spec. Changing the polling period to 100 us instead of 1 ms drastically reduces the time required for this sequence, now taking typically 7 ms or so. This gives a lot more margin during the power on sequence. BUG=b:238466724 TEST=Sequence verified by EE on a scope Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I3ba676c5fac983a0c1ad1d60c3863d06ed33fa27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66020 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-22herobrine: Create Zoglin variantShelley Chen
Zoglin is like Hoglin, but with a smaller flash size, which requires us to create a new variant. BUG=b:239851866 BRANCH=None TEST=Make sure BOARD_GOOGLE_ZOGLIN builds Change-Id: Id1401a052061dcfc1d1ee41b88ce4a11fd9f3d01 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-21mb/google/brya/var/baseboard/skolas: set BOARD_ROMSIZE_KB_32768Nick Vaccaro
Skolas baseboard needs to set BOARD_ROMSIZE_KB_32768, so this change sets it. BUG=b:239628052 BRANCH=firmware-brya-14505.B TEST="emerge-brya coreboot" and verify that the following configs are set as: CONFIG_BOARD_ROMSIZE_KB_32768=y CONFIG_COREBOOT_ROMSIZE_KB_32768=y CONFIG_COREBOOT_ROMSIZE_KB=32768 CONFIG_ROM_SIZE=0x02000000 Change-Id: I0846b8e69c8b65e010eef9a8f4a88606197cd0c6 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-21mb/google: Use boolean type for "enable" argument for regulatorRex-BC Chen
Because 0 and 1 are the only possible values, 1. Change input argument "enable" of mainboard_enable_regulator to bool. 2. Change return value of mainboard_regulator_is_enabled() to bool. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Iae09c5fedf8f7394bfbb677e5aee37ed061304fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65997 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21mb/google: Replace some strings in regulator.cRex-BC Chen
From comments of CB:65875, we replace *_vol to *_voltage. s/mainboard_set_regulator_vol/mainboard_set_regulator_voltage/ s/mainboard_get_regulator_vol/mainboard_get_regulator_voltage/ TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Iadf0408e8914d6e32915464f93979978c4634eaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/65994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-21mb/google/geralt: Initialize PMICs in romstageBo-Chen Chen
TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I71cc69c74dd618f441140790af351095ead3f6f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65759 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21mg/google/corsola: Enable TI50_FIRMWARE_VERSION_NOT_SUPPORTEDYu-Ping Wu
Ti50 hasn't implemented version reading yet. To avoid the confusing error message Did not recognize Cr50 version format enable TI50_FIRMWARE_VERSION_NOT_SUPPORTED to make clear that this feature is not supported. BUG=b:234533588 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I18dd4b5bc05c2af06627275968e49aba048ba05e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-07-21mb/google/rex: Pulling GPIO programming early to get debug msgSubrata Banik
This patch moves the early GPIO programming from `bootblock_mainboard_init` to `bootblock_mainboard_early_init`. It will help to get the early debug prints as below. TEST=Without this CL the initial report platform information was missing as below: [DEBUG]  VBOOT: Loading verstage. [DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x1c04000. [DEBUG]  FMAP: base = 0xfe000000 size = 0x2000000 #areas = 33 [DEBUG]  FMAP: area COREBOOT found @ 1c09000 (4157440 bytes) [INFO ]  CBFS: mcache @0xfef84a00 built for 18 files, used 0x414 of 0x2000 bytes [INFO ]  CBFS: Found 'fallback/verstage' @0x24d240 size 0x133d0 in mcache @0xfef84d50 With this CL the complete bootblock serial msg is coming. [NOTE ]  coreboot-.mtl.po.ww29.5 Fri Jul 15 21:47:36 UTC 2022 bootblock starting (log level: 8)... [DEBUG]  CPU: Genuine Intel(R) 0000 @ [DEBUG]  CPU: ID a06a0, MeteorLake A0, ucode: f0270108 [DEBUG]  CPU: AES supported, TXT supported, VT supported [DEBUG]  MCH: device id 7d14 (rev 00) is MeteorLake P [DEBUG]  PCH: device id 7e01 (rev 00) is MeteorLake SOC [DEBUG]  IGD: device id 7d55 (rev 00) is MeteorLake-P GT2 [DEBUG]  VBOOT: Loading verstage. [DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x1c04000. [DEBUG]  FMAP: base = 0xfe000000 size = 0x2000000 #areas = 33 [DEBUG]  FMAP: area COREBOOT found @ 1c09000 (4157440 bytes) [INFO ]  CBFS: mcache @0xfef84a00 built for 18 files, used 0x414 of 0x2000 bytes [INFO ]  CBFS: Found 'fallback/verstage' @0x24d240 size 0x133d0 in mcache @0xfef84d50 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3e092cd749359e54fe518de21671275af4b03062 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65986 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-07-20mainboard/google/guybrush: Update Wake-On-LAN functionalityRobert Zieba
The generic wifi driver currently contains a lot of intel specific functionality that results in it not working properly on AMD platforms. This commit updates the base device tree to use the generic PCIe driver instead. BUG=none TEST=Ran on nipperkin device, dumped SSDT and checked wakeup sources Change-Id: Iafbc68c1ae33ccc260889f0b39fc5fe8a59d7aca Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65990 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20mainboard/google/skyrim/baseboard: Enable Wake-On-LAN functionalityRobert Zieba
The generic wifi driver currently contains a lot of intel-specific functionality that interferes with enabling wake-on-lan. This commit changes the device tree to use the generic PCIe driver which better supports this functionality. BUG=b:237682766 TEST=Booted on skyrim device and verified that wake on LAN works Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I5d15d33fd0a152eb3bf2bfe78e802483a701e750 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65800 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20mb/google/brya/var/agah: Adjust I2C speedTony Huang
Adjust I2C speed for codec, TPM, touchpad. BUG=b:237691531 TEST=Built and verified adjusted I2C speed < 400KHz Change-Id: I203d137d61019235ddf38ef74607427db2a7e975 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-20arch/arm64,arm: Prepare for !SEPARATE_ROMSTAGEArthur Heymans
Prepare platforms for linking romstage code in the bootblock. Change-Id: Ic20799b4d6e3f62cd05791a2bd275000a12cc83c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-20google/herobrine: Add Evoker variantSheng-Liang Pan
BUG=b:238571507 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: Ie596e5c4b72de84d16571043db4291bbd0825c78 Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Bob Moragues <moragues@chromium.org>
2022-07-20soc/amd/sabrina, mb/google/skyrim: Call espi_switch_to_spi1_padsKarthikeyan Ramasubramanian
Skyrim uses second SPI pads for ESPI. Switch to it initialize ESPI in verstage. BUG=b:217414563 TEST=Build Skyrim BIOS image. Ensure that ESPI init is successful in PSP verstage. Change-Id: I6e3462e95c50d256b6c159ae1d854dd69a538bb0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-20mb/google/skyrim: Regenerate SPD part IDsKarthikeyan Ramasubramanian
Now that the speed is limited to 5500 Mbps for all memory parts used in Skyrim, regenerate the part IDs. Remove any custom generated part IDs and the associated SPDs. BUG=b:238074863 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I6d8326208580a971e781887a7ec83355bb085c7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65709 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20mb/google/brya/acpi: Add support for D Notify event from the Chrome ECTim Wawrzynczak
The agah EC code includes a driver to keep track of the current D Notify level that the GPU should be at. When it changes, it will send a host event to the ACPI FW, which will then pass that Notify on to the kernel driver. This patch adds support for that feature, which is described in the Nvidia Software Design Guide. BUG=b:229405562 TEST=add Printf() calls to the ACPI, and work through the various scenarios on the EC that will cause D Notify levels to change; this will cause the Printfs() to show up in the kernel log. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I5cd8bd7d177ea10a165613ed0726a6d6fd86c226 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-19mb/google/nissa/var/craask: Change craask to use 16M SPI flashTyler Wang
BUG=b:236175568 TEST=Build and test on MB, system can boot to OS. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I779355dcc69eed08703bcb8bb943dcfeeb1fdea1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-19mb/google/brya/var/skolas: fix comment for I2C connectionsEran Mitrani
For brya/skolas, I2C1 is cr50, and I2C3 is Touchscreen BUG=None BRANCH=firmware-brya-14505.B TEST=None Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I4058e0f33b2bb6227a0af92941ed4e2eb56ba542 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-19mb/google/dedede/var/beadrix: Update memory part and generate DRAM IDTeddy Shih
This change adds memory part used by variant beadrix to mem_part_used.txt and generates DRAM ID allocated to the part. BUG=b:236750116 BRANCH=None TEST=Run part_id_gen to generate SPD id Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I3f29609d9fe5143b0bfe4b78279d0780cd7e5097 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-07-19mb/google/rex: Refactor baseboard/variant gpio pad configurationSubrata Banik
This patch tries to simplify the baseboard/variant GPIO programming starting with Google/Rex. The idea is to let each variant maintain its own complete GPIO PAD configuration table instead of having a back-and-forth call between baseboard and variants. With this patch coreboot performing GPIO programming is now much simpler where the common code block calls into respective variants and gets the gpio table prior to the pad configuration. BUG=b:238165977 (Simplify baseboard/variant GPIO programming starting with Google/Rex) TEST=Able to build and boot the Google/Rex board. AP firmware log with DEBUG_GPIO kconfig lists the early GPIOs being configured from the `rex0` variant. gpio_padcfg [0xd3, 08] DW0 [0x44000300 : 0x40000400 : 0x40000400] gpio_padcfg [0xd3, 08] DW1 [0x00000020 : 0x00000000 : 0x00000020] gpio_padcfg [0xd3, 08] DW2 [0x00000000 : 0x00000000 : 0x00000000] gpio_padcfg [0xd3, 08] DW3 [0x00000000 : 0x00000000 : 0x00000000] gpio_padcfg [0xd3, 09] DW0 [0x44000300 : 0x40000400 : 0x40000400] gpio_padcfg [0xd3, 09] DW1 [0x00000021 : 0x00000000 : 0x00000021] gpio_padcfg [0xd3, 09] DW2 [0x00000000 : 0x00000000 : 0x00000000] gpio_padcfg [0xd3, 09] DW3 [0x00000000 : 0x00000000 : 0x00000000] Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8ec5c6991ec90a3884464e7f15f33327bfe4839a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-19mb/google/brask/variants/moli: correct USB3 port2 tx_de_empRaihow Shi
Set USB3 port2 tx_de_emp 0x2B by "11th Gen Intel Core Processors for IoT Platforms EDS Addendum_rev1.6" then fix the USB3 port2 Gen2 RX failed. BUG=b:236661824 TEST=emerge-brask coreboot and check USB3 port2 RX pass Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I7a5add20f055a8d871c6b4f33734fb8a397cba76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65848 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-19soc/amd/sabrina/fsp_m_params: add UPD pointer parameter to mb callbackFelix Held
This allows the mainboard code to change FSP-M parameters depending on parameters that are only known at run time and not at build time. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3e0e196a5d861acd7635c59db44ecf1970b73ce2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-07-18google/herobrine: Support hardware watchdog loggingKshitiz Godara
Add support for hardware watchdog event logging BUG=b:221393157 TEST=Validated on qualcomm sc7280 development board by manually triggering watchdog event and event was logged at next bootup. Signed-off-by: Kshitiz Godara <quic_kgodara@quicinc.com> Change-Id: I94971ab583f49c8a5ac232833215dbdad3a4d272 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65528 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-16mb/google/brya/var/osiris: Add wifi sar tableDavid Wu
1. Add wifi sar table for osiris 2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG BUG=b:234951991 TEST=build FW and checked SAR table can load by WiFi driver. Cq-Depend: chrome-internal:4871098 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I301dce3229a24dd72b12b84d9eb7606abe10cbba Reviewed-on: https://review.coreboot.org/c/coreboot/+/65869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-07-16mb/google/brya/var/brya: fix comment for I2C connectionsEran Mitrani
For brya, I2C1 is cr50, and I2C3 is Touchscreen BUG=None BRANCH=firmware-brya-14505.B TEST=None Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Id564d5ede43e745c607ddfd851ff03557d76ddec Reviewed-on: https://review.coreboot.org/c/coreboot/+/65793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-15mb/google/nissa/var/pujjo: Remove unsupport HDA device settingStanley Wu
Pujjo only support RTL1019 amp device, remove MX98360A device setting BUG=b:238716919 TEST=Build and boot on pujjo Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I92ba66e8656ea36511f88cf867f51ba95168592e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-15mb/google/brya/var/agah: Disable ASPM for dGPUTim Wawrzynczak
Since ASPM is not verified as fully functional yet, and the board is still in development, this patch disables ASPM for the dGPU. BUG=b:236676400 TEST=boot to OS in agah, lspci -vvv shows ASPM is disabled Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I525eeb18c57d45fd55335b63a59262066afc9567 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-07-14mb/google/nissa/var/joxer: Update Joxer config to latest schematicMark Hsieh
init overridetree.cb based on the latest schematic. BUG=b:237628218 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I22778cc2582abdc2e62d98c6b049a0fa4dd467e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-14mb/google/volteer/eldrid:add new generic DDR4 SPDs for EldridJohnny Li
Update DDR4 SPDs to Eldrid to include the following: DRAM Part Name ID to assign H5AG36EXNDX019 0 (0000) BUG=b:236739240 BRANCH=Volteer TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: I2c372fa40899aa750d335825cf3880bc52a612a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65819 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-14mb/google/brya/var/ghost4adl: Add EC_IN_RW_ODEric Lai
Follow latest schematic to add EC_IN_RW_OD. BUG=b:238786599 BRANCH=firmware-brya-14505.B TEST=emerge-ghost coreboot Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I701a940992895b2058b8ddfc444a2e7b7b9531ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/65806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-07-14mb/google/brya/var/ghost4adl: Add SSD power sequence and remove weakEric Lai
Add SSD power sequence and remove the redundant weak. BUG=b:238786597 BRANCH=firmware-brya-14505.B TEST=emerge-ghost coreboot Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I0c1ce311d54fb92b27b17f50beda813fe66ad118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-21 14:44:08 +0000