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2015-10-03sandybridge ivybridge: Treat native init as first class citizenAlexandru Gagniuc
This is a sad story. We have three different code paths for sandybridge and ivybridge: proper native path, google MRC path, and, everyone's favorite: Intel FSP path. For the purpose of this patch, the FSP path lives in its own little world, and doesn't concern us. Since MRC was first, when native files and variables were added, they were suffixed with "_native" to separate them from the existing code. This can cause confusion, as the suffix might make the native files seem parasitical. This has been bothering me for many months. MRC should be the parasitical path, especially since we fully support native init, and it works more reliably, on a wider range of hardware. There have been a few board ports that never made it to coreboot.org because MRC would hang. gigabyte/ga-b75m-d3h is a prime example: it did not work with MRC, so the effort was abandoned at first. Once the native path became available, the effort was restarted and the board is now supported. In honor of the hackers and pioneers who made the native code possible, rename things so that their effort is the first class citizen. Change-Id: Ic86cee5e00bf7f598716d3d15d1ea81ca673932f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11788 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-09-30vboot: provide a unified flow for separate verstageAaron Durbin
The vboot verification in a stage proper is unified replacing duplicate code in the tegra SoC code. The original verstage.c file is renamed to reflect its real purpose. The support for a single verstage flow is added to the vboot2 directory proper. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built glados. Change-Id: I14593e1fc69a1654fa27b512eb4b612395b94ce5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11744 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-28glados: Provide nau8825 platform data via _DSDBen Zhang
BUG=chrome-os-partner:41280 BRANCH=none TEST=Audio jack insert/eject detection and headset buttons work on glados with the nau8825 driver in chromeos-3.18 and the staging kernel skl2. Change-Id: I813a985b4a39249a2cdbe45117acbdb7710bfa29 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7a5b3dafd407fea2376dff5c3dcde50dff4704fb Original-Change-Id: Ic24a0c444761d0f3a35c268078e70d9aacca4c80 Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293610 Original-Reviewed-by: Anatol Pomazau <anatol@google.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11720 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-28glados: Fix typo for WLAN ACPI device nameDuncan Laurie
Fix the typo of _DDR to be _DDN. BUG=chrome-os-partner:40635 BRANCH=none TEST=build glados with iasl-20150717 Change-Id: I8d61a6653c3109890d04e54f0d694703b9c9f2bf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d4a2b2583bdbf9afd7b306359338d4c49bbb44ad Original-Change-Id: I7b7905a217d34a8a78b8280c898f1074ecbe3cf6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302164 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11717 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-24coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin
While the romstage code flow is not consistent across all mainboards/chipsets there is only one way of running ramstage from romstage -- run_ramstage(). Move the timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage(). BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. TS_END_ROMSTAGE still present in timestamp table. Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11700 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-23google: veyron: CBFS_SIZE to match the available size for Coreboot in ChromeOSPaul Kocialkowski
When building for ChromeOS, it is expected that Coreboot will only occupy the first MiB of the SPI flash, according to the veyron fmap description. Otherwise, it makes sense to use the full ROM size. Change-Id: I168386a5011222866654a496d8d054faff7a9406 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11117 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-22coreboot: introduce commonlibAaron Durbin
Instead of reaching into src/include and re-writing code allow for cleaner code sharing within coreboot and its utilities. The additional thing needed at this point is for the utilities to provide a printk() declaration within a <console/console.h> file. That way code which uses printk() can than be mapped properly to verbosity of utility parameters. Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11592 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-17glados/kunimitsu: remove the implementation of mainboard_add_dimm_inforobbie zhang
This is a follow-up patch to https://chromium-review.googlesource.com/#/c/286877, after fsp support is landed in v1.5. BUG=chrome-os-partner:42975 BRANCH=none TEST=execute "mosys memory spd print all" on glados and kunimitsu Change-Id: I949e287372b190affac36a0efde8a30402eecdc8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 71a2e1838ff8bbaa358c167dad905b63d23c43fa Original-Change-Id: I64103af4f8456a053a955845a067062122f47af3 Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/298967 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11657 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17glados: Enable wake-on-wifiDuncan Laurie
- Assign GPE DW0 to GPP_B block - Enable GPP_B16 as ACPI_SCI for wake - Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW Note that current designs cannot wake from Deep S3 via wifi. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados: 1-disable deep s3 in devicetree.cb 2-enable magic packet with "iw phy phy0 wowlan enable magic-packet" 3-powerd_dbus_suspend to go to S3 4-wake system with magic packet Change-Id: I989768615e9da8ecf6354852d2db7aae8069aa82 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 894354c5bfd499b911b7f89310c48b503dbaadc2 Original-Change-Id: I9a7a317fc2eccc70fdb4862843de1a654fbc2eee Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298231 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11650 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17glados: Remove code to set USB charge behavior on sleepDuncan Laurie
The EC doesn't support these commands so sending them is not working. We have had a default policy of wake on USB for a long time now and this runtime config isn't really needed any longer. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: Ib789ae3a7ba56a11dfb5918cb40bfa2f044d1dc3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ed7391942afed94bfc7ad04880d4c2b865e5655 Original-Change-Id: I6fe10952f32673a447001b832ac6c6b04b22aef0 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298233 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11652 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16glados: Enable ALS connected to ECDuncan Laurie
Glados has an ambient light sensor connected to the EC which is presented to the OS as a standard ACPI0008 device. BUG=chrome-os-partner:43493 BRANCH=none TEST=test ALS functionality on glados P2 board Change-Id: I4a4913a1b407720d85f6e630b674e550bf5e36df Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aee2b2446ca45039f1b4866feb83754861dba054 Original-Change-Id: I61f3f31ba077f63b36aa0cd9707e128e65c9ea7d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298251 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11644 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-10glados: Remove functions from acpi_tables.cDuncan Laurie
Remove the acpi_tables.c functions so these functions can move to SOC init code. The file itself is included by x86/arch code and must exist for the build to succeed. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I18e6a0be5eac053598b613b30b622c4963417919 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: af04eb112adf58578c8d2c9d3d182d4c2024abb2 Original-Change-Id: Ibe026d493c25d771357ea39e4b956629fbb799ac Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297758 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11579 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Add Board ID supportDuncan Laurie
Add support for reading board id and populating it in the coreboot tables so it is exposed to payloads. BUG=chrome-os-partner:40635 BRANCH=none TEST=boot on glados and look for reported board ID Change-Id: Iba93a913b67e3b3230aded289c2e25585dec1195 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 472cb7bc84136a1a8b284d661868e64eca4ec004 Original-Change-Id: I478dc0b2f96310b7adbd84701e70598a57306628 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297746 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Enable DPTFDuncan Laurie
- Add ACPI code for DPTF support with placeholder thresholds - Do not have custom PDL for mainboard - Do not have enable charger control for DPTF as there is already a complicated charge profile in the EC. We may still want to enable this but it would need to be tuned to work well with the EC profile. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I8cd2e0ea9c322ea92c101995e8e706f063428a45 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 55d3614441d6701a6d6f0f9d1ade94364ef2594a Original-Change-Id: Ie4587572742d3bcdba7c008fc195213ac50c9d9e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297745 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11569 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Misc code cleanupsDuncan Laurie
- romstage.c is using gpio_configure_pads so it should really include soc/gpio.h instead of relying on it to come from "gpio.h" - consistent formatting of array initializers in pei_data.c - remove pei_data->ec_present flag as this is unused in skylake - fix printk level in spd/spd.c to be BIOS_INFO instead of BIOS_ERR - clean up acpi_slp_type usage in ec.c, remove unnecessary post codes, and cleaner console output message. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I0f76a560dc2c4197e66999752c52573ff0278430 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 67c29f900b7709b73bd0d1e0da26f96cca32828b Original-Change-Id: Ia2a320acf879fa85e9f6b06265cfe38e50e51e46 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297744 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11568 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Remove thermal.hDuncan Laurie
The constants defined in thermal.h are never used since there is no defined thermal zone. Remove it to result in less code to worry about in board ports. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: Idb716b47875b20e2110741ae9c154cc52307fbcf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 01be180b14b5381a8d339dab6c28428c7ac40c10 Original-Change-Id: Ibb710abc301b18d5632f4e01765ea0374b2fe787 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297743 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11567 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Change include headers to relative pathDuncan Laurie
To make it easier to port glados to a new board name change the include headers to use relative path name instead of including the mainboard name. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I6d184adab5b6b2df970ddd3998d3413f1330c12e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 11dd6b73f298cf4867f4a089478132d5e543ea90 Original-Change-Id: Ia8de127fb176784acbbee975e8b950f8c9824c5c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297742 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11566 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09glados: Select EC PD and call early EC initDuncan Laurie
Select the EC PD support in kconfig and call the EC early init code that will reboot into RO for recovery mode. BUG=chrome-os-partner:40635 BRANCH=none TEST=boot on glados in recovery mode Change-Id: Ifa1e2afd91a247c3830d8e705d9d34fb02239fe4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 135ef6e0e2c4864be1c25a9761e04cfe17aec51e Original-Change-Id: Iac8c092453bfbd94210462be0b377fb77410941d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297749 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11573 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09samus: Use EC PD kconfig instead of manual PD rebootDuncan Laurie
Use the new kconfig entry to select the EC PD chip and have it be rebooted before the EC automatically insetad of being done manually by the board. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-samus coreboot Change-Id: I9e7baffec500a83af1fcf9b1e43d418489172918 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 53b086725d9d595e8eff7e1e35b9ba8db17ca199 Original-Change-Id: I9c9a7dd2ba2b78d681b448839f2c5d15ba9dfe60 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297748 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11572 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08rk3288: Allow board-specific APLL (CPU clock) settingsDavid Hendricks
This changes the API to rkclk_configure_cpu() such that we can pass in the desired APLL frequency in each veyron board's bootblock.c. Devices with a constrainted form facter (rialto and possibly mickey) will use this to run firmware at a slower speed to mitigate risk of thermal issues (due to the RK808, not the RK3288). BUG=chrome-os-partner:42054 BRANCH=none TEST=amstan says rialto is noticably cooler (and slower) Change-Id: I28b332e1d484bd009599944cd9f5cf633ea468dd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d10af5e18b4131a00f202272e405bd22eab4caeb Original-Change-Id: I960cb6ff512c058e72032aa2cbadedde97510631 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297190 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11582 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08veyron: Unify identical mainboardsJulius Werner
This patch removes a lot of code duplication between the virtually identical Veyron Chromebook variants by merging the code into a single directory and handling the different names solely within Kconfig. This also allows us to easily add all the other Chromebook variants that have only been kept in Google's firmware branch to avoid cluttering coreboot too much, making it possible to build these boards with upstream coreboot out of the box. The only effective change this will have on the affected boards is removing quirks for early board revisions (since revision numbers differ between variants). Since all those quirks concerned early pre-MP revisions, I doubt this will bother anyone (and the old code is still available through the Google firmware branch if anyone needs it). It will also expand a recent fix in Jerry that increased an LCD power-on delay to make it compatible with another kind of panel to all boards, which is probably not a bad idea anyway. Leaving all non-Chromebook boards as they are for now since they often contain more extensive differences. BRANCH=None BUG=None TEST=Booted Jerry. Change-Id: I4bd590429b9539a91f837459a804888904cd6f2d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 10049a59a34ef45ca1458c1549f708b5f83e2ef9 Original-Change-Id: I6a8c813e58fe60d83a0b783141ffed520e197b3c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296053 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11555 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08glados: Clean up devicetree.cbDuncan Laurie
Clean up the PCI device list comments to be consistent between the skylake mainboards. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I0080ab21db006365f34995db06480dae68ac547d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fa21f77cbaafbc9ca0b98d6951df92c4349fa28d Original-Change-Id: Ie70f94dcc12da141d82b4445643cc0cbe08bb766 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297338 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11561 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08glados: Fix incorrect comment format in devicetree.cbDuncan Laurie
The devicetree.cb compiler can't handle C style /**/ comments, they need to be shell-style #. Due to a last minute formatting change in my commit to enable USB ports this broke the glados build. BUG=chrome-os-partner:44662 BRANCH=none TEST=emerge-glados coreboot Change-Id: I46ee4e5a94d61eefbd2c9a1ba3cafcb6a9e7d71b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8fa92f77b3ef13ede1029292d886351ab5ed87d2 Original-Change-Id: Ibff02a4fd6132def81006a2c6502d34bd4b72823 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296301 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11553 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08glados: Disable unused USB portsDuncan Laurie
Enable only the USB ports that are connected on-board or to an external port, all others will be disabled. BUG=chrome-os-partner:44662 BRANCH=none TEST=build and boot on glados, ensure expected USB ports still work Change-Id: I8c999e3b17478effc39cf078f8420f63413d091b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b86268c70f86991f8c2cdd6763f8efe2ce7f9163 Original-Change-Id: I2fce2c401d07639892c4a0c01527173d3f0b2557 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296035 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11548 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08glados: Update 4GB DIMM SPD for 1866Duncan Laurie
Enable 1866 timings in the 4GB Hynix SPD. BUG=chrome-os-partner:44394 BRANCH=none TEST=emerge-glados coreboot Change-Id: Ibb84f77565d46894afe2153f5951e17a450413fc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f64d76a5f0b0095be96317674caf8542c3155423 Original-Change-Id: Ic5312176c21afc4569f723f5b7f00283b09262d7 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295174 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11528 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-04bootmode: add display_init_required()Aaron Durbin
Some of the Chrome OS boards were directly calling vboot called in some form after contorting around #ifdef preprocessor macros. The reasoning is that Chrome OS doesn't always do display initialization during startup. It's runtime dependent. While this is a requirement that doesn't mean vboot functions should be sprinkled around in the mainboard and chipset code. Instead provide one function, display_init_required(), that provides the policy for determining display initialization action. For Chrome OS devices this function honors vboot_skip_display_init() and all other configurations default to initializing display. Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11490 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-01chromeec: Move keyboard backlight code into Chrome EC directoryDuncan Laurie
Since more boards are starting to use the EC provided keyboard backlight interface move the code to a common place and allow it to get included in mainboards. Change-Id: I3f307bbce1a96cdd1c8224b1e89a63d6fedef738 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/11478 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-30Kconfig: Don't 'select' options based on PAYLOAD_SEABIOSAlexandru Gagniuc
This is just wrong. PAYLOAD_SEABIOS tells us nothing about whether or not the payload will actually be SeaBIOS: 1. PAYLOAD_SEABIOS, but payload changed with cbfstool 2. !PAYLOAD_SEABIOS, but an elf payload was added which is SeaBIOS et. cetera. Change-Id: I4c17e8dde20bf21537f542fda2dad7d3a1894862 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11293 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Damien Zammit <damien@zamaudio.com>
2015-08-29google/glados: Remove unnecessary check for mainboard_ec_init()Martin Roth
mainboard_ec_init() wasn't getting run due to an invalid Kconfig symbol. This check isn't required as the Kconfig option for the EC is forced to be enabled, and the function should always be run. BRANCH=none BUG=none TEST=Rebuilt glados mainboard. Change-Id: I2c4a33d80533a19b02b83b3aaa6a3386e927f1c7 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: edd8c7a0666208b35ee81f57ec2626390958dfb7 Original-Change-Id: I2a92fd28347455c09ecf2119788ca9b6a97a11de Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295143 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11435 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29google/glados: configure gpio pads prior to SiliconInit()Aaron Durbin
Move the gpio pad configuration prior to SiliconInit() in case there are dependencies of the pads being configured in prior to SiliconInit(). BUG=chrome-os-partner:43522 BUG=chrome-os-partner:43492 BRANCH=None TEST=Built and booted glados. Change-Id: I84f8e965bf205a4945b14a63fa8074953750f785 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 5cce5347449f69ac6cf7030ea3b91d3f8b4cc7f9 Original-Change-Id: I18cd33a455d5635a866abb76142cab516b04f446 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294642 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11420 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29google/glados: fix kepler probingAaron Durbin
On proto2 boards the kepler device has its reset line pulled up to one of its IO rails with a zener in between. This results in the device not being visible at MemoryInit() time because for some reason FSP is doing PCIE configuration/probing in that path. Hack around the broken FSP logic by configuring the pads for kepler's power and clkreq. BUG=chrome-os-partner:44326 BRANCH=None TEST=Built and booted glados. lscpi shows the device on bus 2. Change-Id: I543eb3ccd3ab5ffacd6efc959e6e2f7a88de78b3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 67f6b57487e8724b469f74870e0083d4e1dac4d2 Original-Change-Id: I7fe4a707f9321b7bdec4b4be729c5d0dcce65f6e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294810 Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11419 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29google/glados: Export GPIO for EC_IN_RWDuncan Laurie
Export the proper GPIO for EC_IN_RW so it can be picked up and used by depthcharge/vboot. BUG=chrome-os-partner:43072 BRANCH=none TEST=build and boot on glados P2 Change-Id: I32d338ef424086ec9701900e976bd0dffe4637a0 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: dd983c84de0c3b896b20d38438a3285cfcaf7e56 Original-Change-Id: I77f7d3a0c0d733302b81273d96026d39b001ed19 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294712 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11418 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-28veyron_rialto: remove spurious GPIO assignmentsAlexandru M Stan
GPIO(0, B, 3) and GPIO(7, C, 5) are not actually connected, GPIO(0, B, 4) is named differently. BUG=chrome-os-partner:43031 TEST=Rialto should still boot just fine, USB should still work BRANCH=master Change-Id: I11879385de6e9b57ac28bcae699333beb5a0d64c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: a66bf1fd73ff8d15d4ec1a8f3602465941285c32 Original-Change-Id: Ib7d2baa6ed1ab38db786eb4d5e77316ad72cbfd4 Original-Signed-off-by: Alexandru M Stan <amstan@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294713 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/11400 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28veyron: add Nanya NT5CC256M16DP sdramjinkun.hong
BRANCH=None TEST=Boot from veyron BUG=None Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 6fe83821013954f0f2069598fd90a2d49de81101 Original-Change-Id: I68b105aa4bc3e82ef6a2421b127391e319c34d6e Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294660 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-(cherry picked from commit c115d9a3ea2ca1cb62b2a1ee75996d8adb991d5d) Original-jwerner: Added Minnie Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294763 Change-Id: I2bd6521c209db0e2d7d0bdb8ef2cde2715f321a6 Reviewed-on: http://review.coreboot.org/11399 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28veyron_rialto: Turn on all ledsAlexandru M Stan
Without this, the leds would be stuck to whatever the pullup/down states the pins come with on rk3288. Ready2_LED, an orange led, is one of the leds in this state. This might confuse some users thinking there's an error. Turn all of them on instead. Later on depthcharge will use the same LEDs to indicate dev mode status. BUG=chrome-os-partner:44274 BRANCH=master TEST=Boot firmware without anything else, note all leds on Change-Id: I5cf19aabd2a59a61699ef491ae11424cf5a0c874 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 2e1a332a5653fb76bbf8fe624274ec64d2b443a5 Original-Change-Id: I4c4e8940dd9cf1ac0301ac00bfc5992ba16e1589 Original-Signed-off-by: Alexandru M Stan <amstan@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294065 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/11398 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28veyron: mickey sdram-lpddr3-samsung-2GB.inc enable odtjinkun.hong
only modify the MR3 value, there will always be some mickey not working properly. After enable ODT, we use many mickey do tests, now functioning properly. BRANCH=None BUG=chrome-os-partner:43626 TEST=My mickey now boots up Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 681c169d59f5638d35b777eb2b7543e3b0dd90c8 Original-Change-Id: Ieb2b8a56054f91b6be81260e4c574425fb72fed3 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293324 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Commit-Queue: Douglas Anderson <dianders@chromium.org> Original-Trybot-Ready: Douglas Anderson <dianders@chromium.org> Original-Tested-by: Douglas Anderson <dianders@chromium.org> Original-(cherry picked from commit 5397c2f32f5851b9f514b0bd2ae68999a77cabbf) Original-Reviewed-on: https://chromium-review.googlesource.com/294126 Change-Id: Icb3c839bebebfcae54fc6e96e9958c7020d49eff Reviewed-on: http://review.coreboot.org/11396 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28edid: Use edid_mode struct to reduce redundancyDavid Hendricks
This replaces various timing mode parameters parameters with an edid_mode struct within the edid struct. BUG=none BRANCH=firmware-veyron TEST=built and booted on Mickey, saw display come up, also compiled for link,falco,peppy,rambi,nyan_big,rush,smaug [pg: extended to also cover peach_pit, daisy and lenovo/t530] Change-Id: Icd0d67bfd3c422be087976261806b9525b2b9c7e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: abcbf25c81b25fadf71cae106e01b3e36391f5e9 Original-Change-Id: I1bfba5b06a708d042286db56b37f67302f61fff6 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289964 Original-Reviewed-by: Yakir Yang <ykk@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11388 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28veyron: mickey sdram-lpddr3-samsung-2GB.inc now 40 OhmDouglas Anderson
The value of 0x4 (60 Ohm) apperas to be causing lots of problems. Since 0x1 (34.3 Ohm) was _almost_ right, let's try 0x2 (40 Ohm) and hope it's the sweet spot. BRANCH=None BUG=chrome-os-partner:43626 TEST=My mickey now boots up Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 06db96e00d39972edbaf8429cbe88bbc66804e15 Original-Change-Id: If8b7d51d058ae000c0af189a648c62fa38a872ac Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291121 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-(cherry picked from commit 0dabadca1ab3bb310f85646d020bdcf672014071) Original-Reviewed-on: https://chromium-review.googlesource.com/291291 Change-Id: Id32790c894c09616e32503aa790fa294093eca8a Reviewed-on: http://review.coreboot.org/11386 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28veyron_rialto: Force 3G modem offDavid Hendricks
This basically does the same thing for firmware what CL:290631 did in the kernel. We want to keep the modem off until it needs to be used to avoid enumeration/detection issues. BUG=chrome-os-partner:43271 BRANCH=none TEST=needs testing Change-Id: I3b63a77c732dc4895b728b30f1dd71210a9c0e90 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: a90ccd7fbffe44abe05e96341cc77067442c85e4 Original-Change-Id: I3516de1ea9160f7186ad7f5fb3b5d29ac73143b5 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290890 Original-Reviewed-by: Alexandru Stan <amstan@chromium.org> Reviewed-on: http://review.coreboot.org/11385 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28Smaug: Add NVDEC and TSEC carveoutsTom Warren
The NV security team requested that coreboot allocate the NVDEC and TSEC carveouts. Added code to set up NVDEC (1 region, 1MB) and TSEC (2 regions, splitting 2MB), and set their lock bits. Kernel/trusted code should be able to use the regions now. Note that this change sets the UNLOCKED bit in Carveout1Cfg0 and Carveout4Cfg0/5Cfg0 (bit 1) to 0 in the BCT .inc files (both 3GB and 4GB BCTs) so that the BOMs can be written. Any future revisions to these BCT files should take this into account. BUG=None BRANCH=None TEST=Built and booted on my P5 A44. Saw the carveout regions in the boot spew, and CBMEM living just below the last region (TSEC). Dumped the MC GeneralizedCarveoutX registers and verified their values (same as BCT, with only BOM/CFG0 changed). Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: a34b0772cd721193640b322768ce5fcbb4624f23 Original-Change-Id: I2abc872fa1cc4ea669409ffc9f2e66dbbc4efcd0 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290452 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-(cherry picked from commit f3bbf25397db4d17044e9cfd135ecf73df0ffa60) Original-Reviewed-on: https://chromium-review.googlesource.com/291081 Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Change-Id: I924dfdae7b7c9b877cb1c93fd94f0ef98b728ac5 Reviewed-on: http://review.coreboot.org/11381 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-27google/storm/Kconfig: remove select CONSOLE_CBMEM_DUMP_TO_UARTMartin Roth
This seems like more of a debug option, than something that should be forced to be enabled by the platform. Since it's causing a Kconfig warning, I'm just removing it. The alternative to removing it would be to add dependencies on CONSOLE_CBMEM && !CONSOLE_SERIAL Change-Id: Ifc4e4cbeea08a503c38827dd75e0e2e78e8a5eda Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11343 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-27glados: Abstract board GPIO configuration in gpio.hDuncan Laurie
Move all the various places that look at board specific GPIOs into the mainboard gpio.h so it can be easily ported to new boards. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados p2 Original-Change-Id: I3f1754012158dd5c7d5bbd6e07e40850f21af56d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293942 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I93c4dc1795c1107a3d96e686f03df3199f30de8a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11282 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-08-27glados: Implement Chrome OS specific handlersDuncan Laurie
Implement the required Chrome OS specific handlers to read the recovery mode, clear the recovery mode, read the lid switch state, and read the write protect state using the appropriate methods. Also update the Chrome OS ACPI device to use the GPIO definitions that are exposed now by the SOC. BUG=chrome-os-partner:43515 BRANCH=none TEST=build and boot on glados and successfully enter recovery mode Original-Change-Id: Ifd51c11dc71b7d091615c29a618454a6a2cc33d7 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293515 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia6ef83a80b9729654bc87bb81bd8d7c1b01d7f42 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11281 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27glados: Fix SPD part number for Hynix H9CCNNN8JTBLARDuncan Laurie
The part number was the same as the H9CCNNNBLTLAR which means it is not possible to distinguish the two based on part number alone. This breaks mosys and thus the factory tests. BUG=chrome-os-partner:43514 BRANCH=none TEST=boot on glados P2 SKU3 and verify memory reported by mosys Original-Change-Id: I606ef3989bd7273d134a258bc933088ccc865542 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293513 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7cea7cc4c61a20fda47673c8e25c431d391aa3bc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11279 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27glados: Add touchscreen device in ACPIDuncan Laurie
Add the ELAN touchscreen device in ACPI to bind it to the I2C device at bus I2C0, address 0x10, interrupt 31 (GPP_E7). BUG=chrome-os-partner:43514 BRANCH=none TEST=boot on glados P2 and see touchscreen initialized by kernel Original-Change-Id: I23b071b2767547baed239c94216cda6162d045dd Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293512 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I8a9492e6fa1f650cef0871329ae8944caffdaf5a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11278 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27glados: Clean up mainboard ACPI devicesDuncan Laurie
Clean up the device code for the glados mainboard, using the defined values for interrupts by the SOC and moving the various codec i2c addresses to the top of the file. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados Original-Change-Id: Iead1aeb54363b15a6176d4f4a9511674195c0505 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293511 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I083c9ef6140e20a433cb2017e4c3cbc7a41e8fed Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11277 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-26ChromeOS mainboards: Move more Kconfig symbols under CHROMEOSMartin Roth
Move the CHROMEOS dependent symbols VIRTUAL_DEV_SWITCH and VBOOT_DYNAMIC_WORK_BUFFER under the CHROMEOS config options for the mainboards that use them. Change-Id: Iad126cf045cb3a312319037aff3c4b1f15f6529d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11336 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-08-26Google Kconfig: Add MAINBOARD_HAS_NATIVE_VGA_INIT in good placesMartin Roth
Add 'select MAINBOARD_HAS_NATIVE_VGA_INIT' which is just used as a gate symbol to display MAINBOARD_DO_NATIVE_VGA_INIT to the mainboards that are already selecting MAINBOARD_DO_NATIVE_VGA_INIT. Since MAINBOARD_HAS_NATIVE_VGA_INIT is not used in any code, this should not have any other effects. This fixes the warning: warning: (BOARD_SPECIFIC_OPTIONS) selects MAINBOARD_DO_NATIVE_VGA_INIT which has unmet direct dependencies (VENDOR_ASUS && BOARD_ASUS_KFSN4_DRE || MAINBOARD_HAS_NATIVE_VGA_INIT) Change-Id: I8ceee69ebae90dc32f55df58c2e80fe25397f049 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11301 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-21ChromeOS: Fix Kconfig dependenciesMartin Roth
Add CHROMEOS dependencies to selects for the following Kconfig symbols: CHROMEOS_RAMOOPS_DYNAMIC CHROMEOS_RAMOOPS_NON_ACPI CHROMEOS_VBNV_CMOS CHROMEOS_VBNV_EC CHROMEOS_VBNV_FLASH EC_SOFTWARE_SYNC LID_SWITCH RETURN_FROM_VERSTAGE SEPARATE_VERSTAGE VBOOT_DISABLE_DEV_ON_RECOVERY VBOOT_EC_SLOW_UPDATE VBOOT_OPROM_MATTERS VBOOT_STARTS_IN_BOOTBLOCK WIPEOUT_SUPPORTED This gets rid of these sorts of Kconfig errors: warning: BOARD_SPECIFIC_OPTIONS selects CHROMEOS_VBNV_EC which has unmet direct dependencies (MAINBOARD_HAS_CHROMEOS && CHROMEOS) Note: These two boards would never actually have CHROMEOS enabled: intel/emeraldlake2 has MAINBOARD_HAS_CHROMEOS commented out google/peach_pit doesn't have MAINBOARD_HAS_CHROMEOS Change-Id: I51b4ee326f082c6a656a813ee5772e9c34f5c343 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11272 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-20mainboard: Get CHROMEOS/MAINBOARD_HAS_CHROMEOS right (again)Alexandru Gagniuc
CHROMEOS is a user-visible bool. It must not be 'select'ed in Kconfig. That's why we have MAINBOARD_HAS_CHROMEOS. This is the fifth time I find this being used wrong. Why is this confusing/so hard to get right? Change-Id: Icb4629355c63508f5a044b46842524b3d203c2da Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11290 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19glados: use macros for magic numbers in ASLAaron Durbin
The skylake SoC code now has macros for the previously hard-code numbers for IRQs and GPEs. Switch over to using those as they bring a little more clarity. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: Ic8fcc59d680cdddec9dfbc3bf679731f6d786793 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293411 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I594907005372100a3c9d17dda9d17769844ad272 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11234 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-17Fix Kconfig: ALWAYS_LOAD_OPROM has unmet dependency VGA_ROM_RUNMartin Roth
Broadwell and Skylake chipsets, along with a few mainboards were selecting ALWAYS_LOAD_OPROM without making sure that the dependency for that symbol was met as well. Looking at the dependencies for VGA_RUN_ROM, we see: PCI && !PAYLOAD_SEABIOS && !MAINBOARD_DO_NATIVE_VGA_INIT Since ARCH_X86 selects PCI, that's always met here. Since Broadwell and Skylake don't have native VGA init yet, that's not needed. - Make sure that VGA_RUN_ROM is selected as well. - Add dependency on !PAYLOAD_SEABIOS for both ALWAYS_LOAD_OPROM and VGA_RUN_ROM symbols where they're selected. Fixes Kconfig warning for these boards and chipsets: warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS) selects ALWAYS_LOAD_OPROM which has unmet direct dependencies (VGA_ROM_RUN) Change-Id: I787a87e9467e1fc7afe8b04864b2a89b54824b9f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11246 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-14glados: make EC_SCI_L workAaron Durbin
In order for the EC_SCI_L to work the GPE0 route needs to be set along w/ the GPE event for the EC. As the GPE0 route is dynamic the EC_SCI_GPI needs to be set along with the route so everything lines up. In this case, the GPE0 route is set to the defaults such that GPP_C, GPP_D, and GPP_E are routed to GPE0 block 0, 1, and 2, respectively. This works out for glados because the EC_SCI_L is connected to GPP_E16. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados. The 'acpi' interrupt in /proc/interrupts is incrementing as well as /sys/firmware/acpi/interrupts/gpe50. Original-Change-Id: I71fc4bec124f3ac87453a099412154e67aba6280 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/292011 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Idbb6d29364655537abc9ae6f012b3abb38edf138 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11210 Tested-by: build bot (Jenkins)
2015-08-14glados: make EC_SMI_L functionalAaron Durbin
Set the EC_SMI_GPI define to be GPP_E15 and route that GPIO for SMI generation. Also, the mainboard_smi_gpi_handler() was introduced on skylake in order to process any GPI that could generate an SMI. Switch to this handler so one can process the appropriate events. BUG=chrome-os-partner:43778 BRANCH=None TEST=Used 'lidclose' on EC command line during depthcharge to confirm EC_SMI_L generates SMI and shutdown happens. Original-Change-Id: Ia365b86161670a809e3fa99dde38fccc612d5e77 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291934 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ic16ea8e8d6ff564977ed2081d2353c82af71adea Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11209 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14glados: enable SMBus deviceAaron Durbin
In order to run with the debug FSP the SMBus device needs to be enabled. Additionally, the TCO block lives within the SMBus device so if TCO is to be employed then the SMBus device needs to be enabled as a prerequisite. BUG=chrome-os-partner:42407 BRANCH=None TEST=Buit and booted into kernel. Original-Change-Id: I269650fa5222b4741ef495188dff1f4b8176fe89 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290364 Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Change-Id: Ia1f72ea7bd70728de83cdff07df9810a326266c2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11181 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14glados: move to native gpio configurationAaron Durbin
Instead of relying on FSP to do gpio configuration in one place use the native support in coreboot. This also removes the open coded configuration of the memory configuration ids. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I4655221d821d91a2270d774305a02d6bd5c3959c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289800 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2e66242d050c3825f6bc65d3d2c7f51d2cdfbd73 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11175 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-13glados: Enable wake from EC via LAN_WAKE#Duncan Laurie
Enable the Deep Sx pins to allow wake from the EC via LAN_WAKE#. Report the EC wake pin LAN_WAKE as GPE[112]. BUG=chrome-os-partner:43079 BRANCH=none TEST=suspend/resume on glados with wake from keyboard Original-Change-Id: I99664e1e406d15e7460046a6168cbd3a377aaca4 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288921 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I19db144ed5db183f47af03340886a5e770af8bc8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11171 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-10google/stout: Fix ELOG related ifdefsPatrick Georgi
The used functions require the ELOG_GSMI feature, not just ELOG. Change-Id: If38cf0b710d9236012bfb1f0b119c10f9e533a25 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11098 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-09license headers: Drop FSF addresses againPatrick Georgi
Some FSF addresses found their way back into our tree. Change-Id: I34b465fc78734d818eca1d6962a1e62bf9d6e7f3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11145 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-08google/urara: Stub out get_write_protect_state()Patrick Georgi
vboot2 requires it Change-Id: I63bc3f176af72da8ea172a09aa536a10f1184b14 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11099 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29skylake: clean-up pei_datarobbie zhang
Remove the items that are obviously broadwell left or become no-need with fsp. BUG=chrome-os-partner:43186 BRANCH=None TEST=build and boot on sklrvp3. Signed-off-by: robbie zhang <robbie.zhang@intel.com> Change-Id: I5dfd62363eecc514e45a7b7ba0961ec7fe0499ee Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 570920cdc9e9c08ee85dcb08998069f1cae2d3cd Original-Change-Id: I63176584042516c4d28f1bb6403e7bbe5de61010 Original-Reviewed-on: https://chromium-review.googlesource.com/288833 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Robbie Zhang <robbie.zhang@intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: http://review.coreboot.org/11072 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29veyron_rialto: Select PHYSICAL_REC_SWITCHJonathan Dixon
Copied from Change-Id: I8d8dc0c0b98bbd194095d47047c8c5199ce17769 BUG=chrome-os-partner:43022 BRANCH=None TEST=Used physical recovery button to enter dev mode on rialto Change-Id: I39fd13fee3b9f272f3dc08a447091e05a3d74741 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: eed0652f84cba963044908bb91aac7b8c1c81fd4 Original-Signed-off-by: Jonathan Dixon <joth@chromium.org> Original-Change-Id: I388d8bb0faa93b54540be095e68450192592a093 Original-Reviewed-on: https://chromium-review.googlesource.com/287660 Original-Reviewed-by: Jason Simmons <jsimmons@chromium.org> Reviewed-on: http://review.coreboot.org/11069 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29veyron: update mickey sdram-lpddr3-samsung-2GB.incjinkun.hong
Modify MR3_I/O Configuration, Change 34.3 ohms to 60 ohms. This resolves an issue that was observed on some Mickey boards with the Samsung 2GB LPDDR3 and is believed to be caused by inferior routing on the small PCB. (Elpida 2GB LPDDR3 seems unaffected.) BUG=chrome-os-partner:41905 TEST=Boot from mickey BRANCH=None Change-Id: Ic20d9eceb00658c214fd032a2f213dbe0d51a91b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1305010aee6818910ad1dec26d9d948505ca281e Original-Change-Id: I5517e07fc5716ed4cd58e5502f13ccd61ffb5357 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286333 Reviewed-on: http://review.coreboot.org/11051 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29Revert "smaug: Do not gate XUSB partitions"Andrew Bresticker
The PLLU and UTMIPLL power-up sequences have been fixed in the kernel. It's no longer necessary for the XUSB partitions to be ungated at boot. This reverts commit 3a4a8a97c1851b6f3dd211451d9678358fac3ad7. BUG=chrome-os-partner:41244 TEST=Build and boot on Smaug; xHCI still works. BRANCH=none CQ-DEPEND=CL:282765 Change-Id: Id9a1c9960b6c7286b3185c60371d864874f50bb3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d52e50240bca62997af729722fbcdf5226438b7f Original-Change-Id: Ieb9c8644a5fb108d77703933fde82d359f403fd1 Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286810 Original-Reviewed-by: Benson Leung <bleung@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Mark Kuo <mkuo@nvidia.com> Original-Reviewed-by: Mark Kuo <mkuo@nvidia.com> Reviewed-on: http://review.coreboot.org/11050 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29google/stout: Implement functions required by CHROMEOSPatrick Georgi
BRANCH=none BUG=chromium:513990 TEST=google/stout builds Change-Id: I00de7524297e4471a9f7d6afd0d2b991d29020e9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: b85c54af7d4def45f014ee1d9b79df0b649f90f7 Original-Change-Id: I0870dd11c97cecc932a135f73be8234a88c0622b Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288860 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/11064 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29google/parrot: Implement functions required by CHROMEOSPatrick Georgi
BRANCH=none BUG=chromium:513990 TEST=google/parrot builds Change-Id: I5e354d6160e554f1c41e84eac6102e84de34b81d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: d5a6253e6f19815736a6b433f6c58e3be2e5841b Original-Change-Id: I3a3bf9ead333d56472f856c9efefff239fb70586 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288852 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/11063 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29google/butterfly: Implement functions required by CHROMEOSPatrick Georgi
BRANCH=none BUG=chromium:513990 TEST=google/butterfly builds Change-Id: Ia678ca4b0778ee4a2e55ba44a5d89ac6dd691b35 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 0d82ea2090fae9c66f41ee05cc20a9b22d3641c0 Original-Change-Id: I2fea10c17b769ca76b9d0b80978b4c512ed8c680 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288851 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/11062 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-24glados: Support reading memory strap GPIOs to select SPDDuncan Laurie
Add some board specific code to enable the memory configuration GPIOs in GPIO input mode and read them to determine which memory type is on the board. Also add the other memory types that are not yet present in the glados mainboard directory. This should be replaced with the real gpio infrastructure once it is ready. BUG=chrome-os-partner:43069 BRANCH=none TEST=build and boot on glados Change-Id: I7a9ce10e92ad6681528572e87b6cfee29880841a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d81e969c5950fd89bb745d1403abddb08a942f83 Original-Change-Id: Iffb0bd5c176f2adbdd9302d9bff5b7bde725d671 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/287436 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11046 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-24glados: Enable internal pullup for EC_IN_RWDuncan Laurie
Enable 20K internal pullup for the EC_IN_RW GPIO. BUG=chrome-os-partner:42285 BRANCH=none TEST=build and boot on glados Change-Id: I499164fb5050d350510072d2a06eb97fb7f9fcb1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e2de7d4800797a1585165a34dd39af3d635b1f55 Original-Change-Id: I7af1b78482197701aa452998106c2c3476fcc330 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/287437 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11045 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-24glados: Add ACPI configs for speaker amps and codecBen Zhang
The audio codec nau8825 and two ssm4567 speaker amps are instantiated via ACPI. BUG=chrome-os-partner:41280 BRANCH=none TEST=The devices are instantiated. Speaker/headphone playback works on glados. Change-Id: I1297c2435b3051dd749ad7de324b64ba1504cf09 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 59e5eb2682a2fc2cb58068dfcb6dd2415d43b286 Original-Change-Id: Ib7ec8c868251601f67cdf365cd3e935d256c8ac5 Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282364 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11044 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-24rockchip: rk3288: extend jerry backlight vcc_led delay timehuang lin
some jerry panels need more delay time between the vcc_led and bl_en, so we extend the delay time from 20ms to 120ms. BUG=chrome-os-partner:42997 TEST=Boot from jerry, and do not flicker again BRANCH=none Change-Id: Ifcf84578038eb5c2e5a0dfae936ee63cef671968 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0b00b6bd108f0aae461085d00819eca08ec892b3 Original-Change-Id: I74999601b41ccac22493cc9cd0bf52cd4dbb8c26 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287373 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11042 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-23google/veyron_rialto: enable VIRTUAL_DEV_SWITCHJonathan Dixon
BUG=chrome-os-partner:43022 TEST=None BRANCH=None Change-Id: I41c904603e7213da1c8d8e0945b572f6ba844031 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d91722317ffc55a4848e8e3bdac8412218fe1dc4 Original-Change-Id: I1ed4c7aaa35158815f8f7a94eafb77db55a381d0 Original-Signed-off-by: Jonathan Dixon <joth@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/287300 Original-Reviewed-by: Jason Simmons <jsimmons@chromium.org> Original-Reviewed-by: Karl Townsend <karlt@chromium.org> Reviewed-on: http://review.coreboot.org/11036 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-23glados: Fix the write protect GPIO exported in ACPIDuncan Laurie
Update the write protect GPIO reported in ACPI to be 71 which is GPP_C23. Also update the controller id to INT344B:00 which will point at the sunrisepoint device in /sys/class/gpio. BUG=chrome-os-partner:42560 BRANCH=none TEST=verify crossystem output with and without WP enabled Change-Id: I625859bd8ac371a5c0cae18697dccf216c26a8b6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8fc5cb6b72dacd6aefe69fe8204f4e0d209ed8a4 Original-Change-Id: I04892e75f9bfe739c44eb40e7c6a969c33e157ca Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286842 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11035 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-23glados: Add SPD manufacturer and part numberDuncan Laurie
The FSP memory info hob does not return this data so we need to supply it from the SPD included with the mainboard. BUG=chrome-os-partner:42975, chrome-os-partner:42561 BRANCH=none TEST=execute "mosys memory spd print all" on glados Change-Id: Idfb71d36d1f8163d0daceb68675b10194db7cde7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7feece45900e5166864927047ad3ab7b997f8258 Original-Change-Id: Id2bc544ac5faf53f0f676fe132fea1db5640a401 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286877 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11034 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-23glados: Set the write protect GPIODuncan Laurie
The write protect gpio is not added to the gpio map so the structure is not valid for vboot to consume. BUG=chrome-os-partner:42560 BRANCH=none TEST=build and boot on glados, check basic crossytem output CQ-DEPEND=CL:286911 Change-Id: I228d75049b919449072e395699c822203a08f1c6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d15438c4bf56d92189f2f501a62b55b5d00ba461 Original-Change-Id: I3290c4b96e1cc675c618a983915b778f11175020 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286930 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11031 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-23cyan/strago: disable Ambient Light Sensor deviceJagadish Krishnamoorthy
No devices are connected to i2c4 bus on both strago and cyan board. Hence disabling the ALS platform data. This will fix the i2c4 timeout issue and also help in boot time optimization. Removed unused macros. BUG=None BRANCH=chrome-os-partner:41934 TEST=After booting to kernel, i2c4 timeout error message should not appear in dmesg. Change-Id: Ib7ab4c95b0830a8d4e53c6c0ee919649ad1ed354 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3c52b64037b46016fe01f1d55c4c58f7684eb778 Original-Change-Id: Ia7acdcef67a2f2837866f56aa0426a02ee05db46 Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283608 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11005 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21google/cyan: Configure EC_IN_RW signal as gpio inputHannah Williams
BUG=chrome-os-partner:42881 BRANCH=None TEST=Using ctrl-d in recovery mode to switch to dev mode works. Change-Id: Iefbd11d435c4beb570875d4835a085b194d1d1e8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: be172409792a224855b1d31621f23d1969d319b9 Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Change-Id: Icf57dfc4cc258aa2cba341f40d285f8c843aace5 Original-Reviewed-on: https://chromium-review.googlesource.com/286612 Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/11013 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21intel/cyan: Fix crossystem "wpsw_cur" statusHannah Williams
The GPIO mapping was incorrect for wpsw_cur. The GPIOs for East community were in two ranges: 0: INT33FF:02 GPIOS [373 - 384] PINS [0 - 11] and 12: INT33FF:02 GPIOS [385 - 396] PINS [15 - 26] The discontinuity was not accounted for, hence the error. The original offset was 0x16 whereas it should be 0x13 BUG=chrome-os-partner:42798 BRANCH=None TEST=Run crossystem and test wpsw_cur entry. If screw is present, it should be 1 and if not present, it should be 0 Change-Id: I2faea1fe1415c9d4cb23444d03c7c9d47c87e8e5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 30ac96f606a5618e9ef12bac3f50fac433141acd Original-Change-Id: I166a7c3e15a990b507ae3c13e15ab56bee7fb917 Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286534 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/11010 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21Cyan: Tune charger current limit in performance states table.li feng
Charger performance states table defines charger current limit for each p state. Modify charger current control values for SANYO battery used in Cyan. BUG=None BRANCH=None TEST=System is charging battery, in shell window, issue command "echo 0 > /sys/class/thermal/cooling_device4/cur_state", "echo 1 > /sys/class/thermal/cooling_device4/cur_state", "echo 2 > /sys/class/thermal/cooling_device4/cur_state", "echo 3 > /sys/class/thermal/cooling_device4/cur_state", or "echo 4 > /sys/class/thermal/cooling_device4/cur_state", will see EC console show different charging current value. Change-Id: Ie9bc78822a73de6bed338bfbcc5e9045653689dc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3a6162151d1f9c756a13d2afc17f6b9c18608efc Original-Change-Id: I71e8247d057e4728eedcd5e8a275b64428290d09 Original-Signed-off-by: li feng <li1.feng@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285605 Original-Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Divya Jyothi <divya.jyothi@intel.com> Original-Tested-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: http://review.coreboot.org/11004 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21Glados: Update Serial IO modes in devicetreeNaveen Krishna Chatradhi
This patch updates the Serial IO modes for UART2 to PCI mode in devicetree for glados board. Also we switch over to CONSOLE_SERIAL8250MEM_32 here. 8-bit legacy UART will stop working after devicetree change. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for glados and tested LPSS logs on glados. CQ-DEPEND=CL:284881 CL:284882 CL:284883 Change-Id: I433979c852c80848c006ef089b43d75a17e761c5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c37519e0762801cbb9b547b538b385c84299189 Original-Change-Id: I2faec08d089e407c5ab9838bea980553f49821c4 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284826 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/11002 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21google/glados: add new boardPatrick Georgi
Change-Id: I0c196ff84484717c59c59d11bb7230b5920e0654 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10997 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21cyan/strago: Disable wwanJagadish Krishnamoorthy
Disabling the wwan gpio line since wwan is not used. BRANCH=none BUG=none TEST=wwan should not connect to network on cyan/strago. Change-Id: I9d2e5d5b185a4622218e894d3b092afe15e09289 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9a20c602b3bb768baa38b17e21cb4e5b0d9249ef Original-Change-Id: Ib8d5fd15a172ef898ce675a85c2ea3e5f5c79144 Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285304 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10992 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21cyan: Enable EC software syncRavi Sarawadi
BUG=chrome-os-partner:40526 BRANCH=None TEST=Verify that system boots when used with coreboot and EC versions that also have Software Sync enabled. Change-Id: I6ed562fa51d83ddf16fc74d35db7c0004f57c79e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 090a66c50fac21808c4721a32b1728cc904f1b00 Original-Change-Id: Ia4d87d9a177c579567c03ae113889a277ffecee0 Original-Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283573 Original-Commit-Queue: Divya Jyothi <divya.jyothi@intel.com> Original-Tested-by: Divya Jyothi <divya.jyothi@intel.com> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/10985 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-17mainboard/google: Add Braswell based Cyan boardLee Leahy
Add initial files for the cyan board. Matches chromium tree at 927026db This board uses the Braswell FSP 1.1 image and does not build without the FspUpdVpd.h file. BRANCH=none BUG=None Test=Build and run on cyan Change-Id: I935839be033c25e197e78fbee306104b4162a99a Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10182 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16foster: correct odmdata in odmdata.cfgYen Lin
So odmdata has the correct UART port of 0 BUG=chrome-os-partner:40741 BRANCH=None TEST=build Foster ok; and check scratch20 register Change-Id: I2c203317e6305214b74430780f2fe7b15652873a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0a0a99ac9c7db267129e4bc3478f9bb1ece08507 Original-Change-Id: I7be10d5deb5118f1cf3e339afca94893610437f2 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/280291 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10955 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16smaug: correct odmdata in odmdata.cfgYen Lin
So odmdata has the correct UART port of 0. BUG=chrome-os-partner:40741 BRANCH=None TEST=build Smaug ok; and check scratch20 register Change-Id: I59154daa5b5627d3b594ff9505e4f02de0d4d7aa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 814cd164ab9ed9bf2e072f3728e89ea8d7cf0343 Original-Change-Id: I2252b728775cf2550d666ead0085c0ab3b72e40b Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277024 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10954 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16foster: add sdram_configs.cYen Lin
Add sdram_configs.c to both romstage and ramstage. BUG=chrome-os-partner:40741 BRANCH=None TEST=Build ok on Foster Signed-off-by: Yen Lin <yelin@nvidi.com> Change-Id: Ib270c837ebe355c8d16072186c2b27d1c469fd48 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 73bc1abf2821176c21179880774887eec7c858b1 Original-Change-Id: Ia80a57a81e44542ee3d5437866071d50c8c5b8cb Original-Reviewed-on: https://chromium-review.googlesource.com/280290 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Tested-by: Yen Lin <yelin@nvidia.com> Original-Commit-Queue: Yen Lin <yelin@nvidia.com> Reviewed-on: http://review.coreboot.org/10951 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16smaug: ramstage: include sdram_configs.cYen Lin
get_sdram_config() (in sdram_configs.c) will be needed in ramstage. BUG=chrome-os-partner:40741 BRANCH=None TEST=Build ok on Smaug Change-Id: I2920f8687b6a801a91dc5b5b50fc5637057e4321 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d3092e360b26cbda41549452aeeba9ffc0b92ed Original-Change-Id: I43a20f3178cbf5b57a3a9ca7391856787aa8cdb8 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277373 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10950 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16smaug: Use VNBN_FLASH instead of VBNV_ECFurquan Shaikh
CQ-DEPEND=CL:285312 BUG=chrome-os-partner:36613 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: Ib90333e3331a90b4539d49e1a72833fe3385879f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 042fc1a451081780f8af35af6943130f6412ca5f Original-Change-Id: I729996c04d8bd6a627421803a59037d7c47a3e98 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285345 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10949 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16smaug: Increase drive strength for QSPI PinmuxFurquan Shaikh
Change the drive strength for QSPI Pinmux to DRIVE_STRENGTH_2 as per recommendations from nVidia hardware engineers. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: I5a7b94acb57bbc21d277a49fd0a6b892638fc0ca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 58d085e6acbcd0fd355b1c7efc10606312caf8e8 Original-Change-Id: I03dd288d2e335d40c83feaec7efbf10a7d3bf1e6 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284959 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10945 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-14azalia: fix up and clean up shrinkage of boilerplate codeJonathan A. Kollasch
Should fix regression in HDA verb setup on nvidia mcp55 and intel sch southbridges. The mcp55 code could not find the mainboard's verb table because the table was not even being compiled in. The sch boards appeared to have the same issue. Intel broadwell and fsp_bd82x6x seemed to have not gotten the boilerplate shrink, so apply it to those too. Followup-to: Ib3e09644c0ee71aacb067adaa85653d151b52078 (azalia: Shrink boilerplate) Change-Id: If7aae69f5171db67055ffe220bdff392caaa5d9f Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10826 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-13smaug: Set LDO2 voltage to 1.8VFurquan Shaikh
LDO2 regulator is used as an always-on reference for the droop alert circuit. Set output voltage to match kernel settings. CQ-DEPEND=CL:284649 BUG=chrome-os-partner:42305 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: I5ef4e266d8ec278dadffa846af8dc49b6d18c37e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 611465f6248cba0ddce0083b431cb7ee17bc4b4c Original-Change-Id: I58cc473452b871392d813387707a0b8288e46561 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284879 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10900 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-09veyron_{brain,danger,mickey,romy}: Select PHYSICAL_REC_SWITCHDavid Hendricks
BUG=chrome-os-partner:42220 BRANCH=veyron TEST=Used physical recovery button to enter dev mode on mickey Change-Id: I78332f516b042be9c0cef6d8a59af44b670fc260 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4fcd79a133dc750dffd5d23e0b84a109e7b7cb8d Original-Change-Id: I8d8dc0c0b98bbd194095d47047c8c5199ce17769 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/283546 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10844 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09smaug: Update PMIC settingsFurquan Shaikh
Update PMIC settings as per table provided by hardware eng team. Change-Id: I17a8a1a44fa8c9093e13e8d7e4a2f5b07a3b1f1f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3c49afd0d1a17b73f2192206ff7389e2f7930fec Original-Change-Id: I027febb6849f1c4d15bf56d8bcd29c431655c7b6 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283543 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10843 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09veyron_danger: Enable developer mode switchDavid Hendricks
Danger has a physical developer mode switch, it was just never set up. This patch defines it, sets it up in fill_lb_gpios(), and disables VIRTUAL_DEV_SWITCH. Note: For now at least, dev mode is a bit wonky on Danger. It's connected to both a DIP switch and a button. The button is normally open, pulling dev mode high (defaulting to ON). The switch's "ON" position will pull the value low, so we invert the value in coreboot to see the expected behavior. Dev mode is enabled by holding the button down during boot or by setting switch 2 in the DIP bank to the ON position. BUG=none BRANCH=none TEST=toggled dev switch on Danger and saw dev screen show up (or not) as expected Change-Id: I9369b96b6c9b54553d969b919ed663abdc704dd2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dce53f1a31919f15f6e46c4a7d1c5ce541c2b318 Original-Change-Id: I737f165d7704e2f73375099367f012b365e3e77d Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/280852 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10839 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-07marvel/bg4cd: move timestamp init to SoC codePatrick Georgi
No need to repeat this in the mainboard code (even if there's only one right now). Change-Id: Iaa3508c27f8c38cfa343ab1d8a094ce922dec157 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/10825 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-07-07rk3288: Use timestamp region for pre-cbmem timestampsFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully for veyron_pinky Original-Change-Id: I3862e9bf2c32085c921adae4c1dcdf88ff0f3ff3 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/227243 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 0fabdbb05826160beb8ee8f89339b18a49e87ab8) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4504d29a43084d4bd406626899b25903200fa6d7 Reviewed-on: http://review.coreboot.org/10740 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-07-06veyron*: Kill SKIP_DISPLAY_INIT_HACKDavid Hendricks
Now that we have functioning display code for all platforms, we can just get rid of this ugly hack used on non-Chromebook veyrons. BUG=none BRANCH=none TEST=built for Brain, Rialto, Mickey, Romy Change-Id: Ibe248c7cc74940811345c249d66992d74fe85fe5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c627b087ba9fc07b4ec4a6d55d2e0203bdd4ff5 Original-Change-Id: I946eddb4e8ce1dbaa20212a2bb417e71a31b2ba3 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282049 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10785 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-07-06veyron_rialto: Use VOP_MODE_NONE for display init.David Hendricks
This uses VOP_MODE_NONE for display init on veyron_rialto and adds a mainboard_power_on_backlight() stub so that we can finally get rid of SKIP_DISPLAY_INIT_HACK. BUG=none BRANCH=none TEST=built for veyron_rialto Change-Id: Ia6b420a962fe266e773c804b8e5c68da35848753 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a290c938c163759a3672c07d8ec7c0a38057b13d Original-Change-Id: Iec2d7f03857198a4d6f7490db1e3e19c74f18c43 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282048 Reviewed-on: http://review.coreboot.org/10784 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06veyron_brain: Add basic HDMI supportDavid Hendricks
This adds a configure_hdmi() function that drives the HDMI enable output high and configures the iomux. Calls to PMIC functions to enable HDMI power are moved here as well. BUG=none BRANCH=none TEST=with follow-up patches, we now get a dev screen on Brain. Change-Id: Ifd2648376c789fb29c9e2e4ab6bdb10ca439e4a2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 91ec6a96edaf2042236aee0383e18715014f1013 Original-Change-Id: I0c6e9f8fc5e06f53a1a160d8ab2e32447168139e Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282046 Reviewed-on: http://review.coreboot.org/10778 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 20:02:47 +0000