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Some of the I2C buses are required to operate at different voltage level
compared to other I2C buses eg. I2C bus to Google Security Chip (GSC)
should be at 1.8V level. By default, all the I2C buses are initialized
to operate at 3.3 V. Add support to configure I2C pad RX select through
devicetree and update the concerned devicetree.
BUG=b:188538373
TEST=Build and boot to OS in Guybrush. Ensure that the communication
with GSC is fine. Build Majolica mainboard.
Change-Id: I595a64736fdac0274abffb68c5e521302275b845
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Some of the GPIOs are either re-purposed for different use-cases or are
unused in upcoming board phase (board version 2). Update the GPIO
configuration accordingly. Here are the GPIOs that are updated:
GPIO Board Id 1 Board Id 2
=============================================
GPIO31 TP183 EN_SPKR
GPIO69 EN_SPKR SD_AUX_REST_L
GPIO70 SD_AUX_RESET_L Unused TP27
GPIO74 RAM_ID_CHAN_SEL Unused TP49
BUG=b:189327557, b:188542649, b:188542497
TEST=Build Guybrush mainboard. Verify Audio is audible and SD card is
detected fine in Board ID 1.
Change-Id: I31523b3e03d2b59577f33eae548747834cfc98aa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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GSC is connected with AP via i2c bus so we need to enable i2c in
psp_verstage.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I5f7b73be67a692ea7de31ae53bd111d0e4b6998c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55136
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update DPTF parameters from internal thermal team.
BUG=b:180875580
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Id18a38cddbcacbafbe2c54d94dbda5e00de02b3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
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If unspecified, chipset code already uses 101, and 0x65 == 101.
Change-Id: I524ca492fa577003df23017756f74a455582132f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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On Chromebooks the RAM code is implemented by the resistor straps
that we can read and decode from ADC. For Cherry the RAM code can be
read from ADC channel 2 and 3.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4f28bc1c567cb886bd90d930219981a6206b9bb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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This patch adds support for SPM. This adds 43ms to the boot time.
TEST=program counter of SPM is correct value after booting up.
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5f17f6d51fc9ad2d23c71c3c5cd29fdc777dc071
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55154
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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I2C4 is not used pn Brya hence make below changes:
1. Disable it in SerialIoI2cMode.
2. Remove I2C4 config in common_soc_config.
TEST=Make sure FSP is not programming I2C4.
Change-Id: I94c72b7fac9d8a001913b5faa2c0c8a3e8b701e9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add Goodix GT7996F touchscreen into devicetree for cret.
BUG=b:180547935, b:188501391
BRANCH=dedede
TEST=Built cret firmware and verified touchscreen function.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I2a6f7c1e9900492937202c0bc6595674f1e79e5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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For all of the audio devices in overridetree.cb add the probe matches
that will determine if the device should be enabled or not based on the
selected audio daughter board type.
AUDIO=MAX98357_ALC5682I_I2S: enable max98357, dmic1 and alc5682i
AUDIO=MAX98373_ALC5682_SNDW: enable max98373, dmic2 and alc5682
BUG=b:188696010
TEST=test different audio devices based on fw_config value:
> AUDIO=UNKNOWN
ectool cbi set 6 0x00000000 4 2
> AUDIO=MAX98357_ALC5682I_I2S
ectool cbi set 6 0x00000100 4 2
> AUDIO=MAX98373_ALC5682_SNDW
ectool cbi set 6 0x00000200 4 2
Change-Id: I6f159442516830f9d304d78c83f070e4fcff4a37
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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In order to resolve the I2C address conflict with another peripheral in
the upcoming hardware build, left speaker amplifier I2C address is
reconfigured.
BUG=b:188539052
TEST=Build Guybrush mainboard. On Guybrush board ID 1, all the 3
speaker amplifiers are added to the ACPI table.
\_SB.I2C2.D028: Realtek SPK AMP L at I2C: 03:28
\_SB.I2C2.D029: Realtek SPK AMP R at I2C: 03:29
\_SB.I2C2.D02A: Realtek SPK AMP L1 at I2C: 03:2a
At the OS side, the concerned speaker amplifiers are probed and
enumerated.
localhost ~ # i2cdetect -y -r 2
0 1 2 3 4 5 6 7 8 9 a b c d e f
00: -- -- -- -- -- -- -- -- -- -- -- -- --
10: -- -- -- -- -- -- -- -- -- -- UU -- -- -- -- --
20: -- -- -- -- -- -- -- -- UU UU -- -- -- -- -- --
30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
70: -- -- -- -- -- -- -- --
Change-Id: I69a7e7dd65a459c2e5629ada1dea1f1660dd9990
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Configure I2C rise/fall time in device tree to ensure I2C
CLK runs accurately at I2C_SPEED_FAST (<400 kHz).
Measured I2C frequency changes are just as below after tuning:
touchpad: 434kHz ---> 391kHz
touchpanel: 439kHz ---> 382kHz
audio codec RT5682: 445kHz ---> 385kHz
BUG=b:187555396
BRANCH=dedede
TEST=Build and check after tuning I2C clock is under 400 kHz
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I8438e37be49f8a74f53fd8460110dac1a3f06993
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The entries in the ACPI tables for the fingerprint module's SPI
configuration were incorrect.
1) The GPIO is routed to IOAPIC (and SCI), therefore in ACPI, it must be
described by Interrupt(), not GpioInt()
2) The chip-select signal was selected as 1, not 0 `device spi 0/1 on`
BUG=b:181635081
TEST=verified in kernel logs:
localhost # ~ dmesg|egrep 'cros-ec-dev|cros-ec-spi'
[ 4.569412] cros-ec-dev cros-ec-dev.1.auto: CrOS Fingerprint MCU detected
[ 4.575303] cros-ec-spi spi-PRP0001:00: Chrome EC device registered
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I9ef6c99f011969fc444e0c12b806529cb82bba3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55147
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As per the comments in CB:54090 mainboard api
mainboard_tcss_get_port_info() is simplified and moved to tcss common
block code.
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com>
Change-Id: I7894363df4862f7cfe733d93e6160677fb8a9e31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Add Elan eKTH7D18 touchscreen into devicetree for cret.
BUG=b:180547935, b:187484857
BRANCH=dedede
TEST=Built cret firmware and verified touchscreen function.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Iab87ddfc7b46420439efa3e7e55c88ad4c27155d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Configure I2C rise/fall time in device tree to ensure I2C
CLK runs accurately (380<frequency<400 kHz).
Measured touchpad I2C frequency is 394 kHz
BUG=b:189740533
BRANCH=dedede
TEST=Build bios and make sure frequency meets specification.
Change-Id: Ibc0504a5be6fe9237b8b30783c659a761d10561a
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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There are two touch pads that Sasukette used have the same I2C address.
It will show "/dev/input/event4: SPPT2600:00 06CB:CE9D Touchpad" when
the Synaptics touch pad is connected after running evtest under VT2.
BUG=b:189520603
BRANCH=dedede
TEST=It will show "/dev/input/event4: SYNA0A00:00 06CB:CE9D Touchpad"
when the Synaptics touch pad is connected after running evtest under VT2.
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: If0bd80baa27dfeb7bcb43f0ca4b02e1228e372a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55035
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the primus variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-generated by create_coreboot_variant.sh version 4.5.0)
BUG=b:188272162
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PRIMUS
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I26787f296793b281b7f1ee1a7d240006163c6015
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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1) Hynix H9HCNNNCPMMLXR-NEE
2) Micron MT53E1G32D2NP-046 WT:B
BUG=b:186616388, b:181736400
Change-Id: I56bfe8aa4f8d8aab2011fa8d17b3b2c8659658e3
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54951
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to support no MIPI camera variant, move related configuration into variant folder.
BUG=b:188272162
BRANCH=none
TEST=build no MIPI camera variant without error
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I4e64d078a8e39732ad29443c3b09ca008a7e902f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Based on schematic and gpio table of volet, update gpio and
devicetree settings for volet Proto.
BUG=b:186334008
TEST=FW_NAME=volet emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ia0e9557e01ce1e7a49a3dddf6da3e4a29587a8b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55113
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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volet use same memory configuration from Voxel, copy voxel setting to
volet.
BUG=b:186334008
TEST=FW_NAME=volet emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I7e65b18f2ddae3d1ce02d9006153269697188f61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55096
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Add 1 port and 1 endpoint
2. Add support for OVTI8856
WFC is on I2C0
BUG=None
BRANCH=None
TEST=Build and boot brya
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Ic5e9c28f255bdf86a68ce80a4f853be4e7c7ccfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id2bdce5871f57e9edb17f89cba61b5c5ae018566
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The chipset devicetree only has the essential PCIe devices enabled that
are needed for the SoC code to work. It also defines aliases for all
PCIe devices that can be used to reference the devices in the mainboard-
specific devicetrees and devicetree overrides. To make the change easier
to review that part will be done in a follow-up patch.
Despite missing in the PPR, device pci 18.7 exists on Picasso.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b7c3fd32579a23539594672593a243172c161c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Update the first version DPTF parameters received from the thermal team.
BUG=b:188936764
TEST=emerge-volteer coreboot chromeos-bootimage
Cq-Depend: chrome-internal:3851737
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Id14b1d0bdd48c65eafbdd2e80b4611c86781be00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Update devicetree and gpio driving of storo that enable stylus
Updates the GPIO configuration for GPP_C12 to
PAD_CFG_GPI_GPIO_DRIVER and device tree entry for PENH device to
use WAKEUP_ROUTE_GPIO_IRQ.
BUG=b:188519508,b:188365033
BRANCH=dedede
TEST=build bios and the pen behavior can be detected.
Change-Id: I2ffc969569b3ca29ba76326140f958a9707199f7
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54762
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enabling AC connect/disconnect wake events in brya to meet Chrome OS
wake requirements.
These changes are similar to Volteer and Shadowmountain.
BUG=none
BRANCH=None
TEST=manual tested DUT wakes for AC connect/disconnect in S0ix
Change-Id: I14b3efd429e3aa701af534f150baf35fcdeb9f35
Signed-off-by: madhusudanarao amara <madhusudanarao.amara@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54855
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We would like to have an easy way to completely disable TPM support on a
board. For boards that don't pre-select a TPM protocol via the
MAINBOARD_HAS_TPMx options, this is already possible with the
USER_NO_TPM option. In order to make this available for all boards, this
patch just removes the whole USER_TPMx option group and directly makes
the TPM1 and TPM2 options visible to menuconfig. The MAINBOARD_HAS_TPMx
options can still be used to select defaults and to prevent selection of
a protocol that the TPM is known to not support, but the NO_TPM option
always remains available.
Also fix some mainboards that selected TPM2 directly, which they're not
supposed to do (that's what MAINBOARD_HAS_TPM2 is for), and add a
missing dependency to TPM_CR50 so it is set correctly for a NO_TPM
scenario.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib0a73da3c42fa4e8deffecb53f29ee38cbb51a93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
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This fixes the following error from the Linux kernel:
ccp 0000:03:00.2: ioremap failed
ccp 0000:03:00.2: initialization failed
ccp: probe of 0000:03:00.2 failed with error -12
BUG=b:186575712,b:189202985
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5cbc620001d3c21c538b62ab2811b6e07269feb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54962
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The firmware config field in CBI lets us control initialization
parameters based on the OEM design.
BUG=b:188713024
TEST=Build
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I56ddc7218688919f20f41e0f143419c39d83849d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Since the default for the corresponding UPD of the Picasso FSP is
DXIO_PSPP_POWERSAVE and the devicetree default is DXIO_PSPP_PERFORMANCE,
add a deviectree setting for each board that's using the Picasso SoC
code to not change the setting for the existing boards.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0008ebb0c0f339ed3bdf24ab95a20aa83d5be2c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Not sure which policy we should select here or if that should be done in
the board-specific devicetree overrides instead of the baseboard.
BUG=b:188793754
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I792d909ce75cb73571c9fec58c18f749ea3ae029
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54933
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:188793754
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I262c4c3ae90d8d12fdfe71a3620739070a444a55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54931
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All relevant USB phy settings can now be controlled via devicetree.
The given values are the AMD default ones.
For proper tuning procedure and values contact AMD.
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: Ie8d08bde54f8c0cb8202ba111b9c7a9bd33fa03e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Configure GPIO CAM_PDN5 (AP_XHCI_INIT_DONE) as output, so that
payloads (for example depthcharge) can assert it to notify EC to enable
USB VBUS.
BUG=b:187149602
TEST=emerge-asurada coreboot
BRANCH=asurada
Change-Id: I3bf63f91b8057e35be2780024a8b398c3044729b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54902
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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haboki/habokay is the same design as drawlat/drawcia, and differs only
in replacing Cr50 with discrete TPM.
BUG=b:187094464
TEST=FW_NAME=haboki emerge-keeby coreboot
Cq-Depend: chrome-internal:3850094
Change-Id: Id866927b7041c5bf1c73fb4f0c03798eb61efa79
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54755
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add GPIO "beep enable" for switching on and off.
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Change-Id: Iddb781e30fa90f05767cceeb83e623432540dcc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add new memory MT53E512M32D1NP-046 WT:B in the mem_parts_used.txt and
generate the SPD ID for the parts.
BUG=b:183057749
BRANCH=dedede
TEST=Build the cret board.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ib797af858e8f7ea275291e552102db74f4724aad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54747
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Goodix touchscreen according to the Programming Guide Rev.0.7
BUG=b:188872893
TEST=build and boot into OS.
check dmesg trying to add GDIX0000:00 device.
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I38c9bbf6e1c1531bf3524552db58c0bf183acbb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=b:189053502
BRANCH=puff
TEST=build image and verified by thermal team.
Change-Id: Ic2337b9eabef158633c5e6dfa935ed5c8d3d76d1
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54718
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 2f8a7046bb120d96022ada1e74545f859f97521f.
Reason for revert: CB:54752 makes this unnecessary
Change-Id: I3ad0bcafe50e3eafb9a106720c6c9ea5cb0efc4f
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54789
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ELAN touchpad into devicetree for sasukette.
BUG=b:188376649
BRANCH=dedede
TEST=built sasukette firmware and verified touchpad function
Signed-off-by: lizhi7 <lizhi7@huaqin.corp-partner.google.com>
Change-Id: I898aeda936eb10ef4ead679a1c087060fad71a08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54369
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drawper would use synaptics touchpad.
BUG=b:184878424
TEST=emerge-dedede coreboot and check touchpad function work.
Change-Id: I2d2c205e19d8e3472e0fa7ca20fd38e381ac0de0
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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Update ACPI HID to 10025682 for Machine driver probe
BUG=b:187912480
TEST=Build and boot to OS in Mancomb. Ensure that the sound card probed.
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I5dc87c7a8fb876adc26165655f8f2d4157aa68c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54749
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Send USB_MUX host event for the connect/disconnect type C devices.
BUG=none
BRANCH=None
TEST=manual tested USB connect/disconnect
Change-Id: I5a720e1f1ea42f200e0e4c98f42894e4b92c67f8
Signed-off-by: madhusudanarao amara <madhusudanarao.amara@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54725
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:188446049
TEST=Build and boot to OS in mancomb. Ensure that the system can suspend
and resume successfully. Ensure that the sleep state GPIOs are
reflecting the state as expected.
Change-Id: I43e86a07075fe66f89c2c5665adc209e985e4f04
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Drawper support LTE+HDMI,
so use DB_PORTS_1A_HDMI_LTE to select HDMI VBT output for it.
BUG=b:186393848
BRANCH=dedede
TEST=Build and boot to OS check HDMI output works.
Change-Id: Ibf34cce1e3cbfce8a71dce880c50f85db9295b1e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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DB_PORTS_1C_1A_LTE 6
DB_PORTS_1C 7
DB_PORTS_1A_HDMI_LTE 8
BUG=b:186393848
BRANCH=dedede
TEST=build pass
Change-Id: I8632960d7e538402bf033d07402116dac848f5ac
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Enable ASPM, Common Clock and Clock Power Managment. Accomplish this
by adding the options in the platform Kconfig as well as dxio
descriptors.
BUG=b:187743927
TEST=Boot to ChromeOS and see ASPM, CC and Clock PM enabled with lspci
Change-Id: I9d6e606763798afc6b797d7d24ee7cae09f9e33f
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54681
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable ASPM, Common Clock and Clock Power Managment. Accomplish this
by adding the options in the platform Kconfig as well as dxio
descriptors.
BUG=b:187743927
TEST=Boot to ChromeOS and see ASPM, CC and Clock PM enabled with lspci
Change-Id: Iefc4b5b489cb8caf59f21dd4333d7af66ba47c32
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54282
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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UI monitors this input event and sends global mic mute command to CRAS
when the physical switch is toggled.
BUG=b:184593945
BRANCH=puff
TEST=build image and verify with evtest on DUT.
Apply crrev.com/c/2870806 with chrome cmdline flag and verify global
mute is triggered.
Verify sequences of switch toggle and suspend/resume.
Change-Id: Id89947885fdd96c5b5d598bda6db127daf298dc3
Signed-off-by: Ben Zhang <benzh@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Enable Display Controller Engine Audio endpoint to enable HDMI audio.
BUG=b:186479763
TEST=Build and boot to OS in mancomb.
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I47cf9a9dc73fd47e390b079bb9eaa14dc364404a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The time constant values were taken from the zork thermal.asl.
BUG=b:186166365
TEST=Boot guybrush to OS and verify logs look correct
thermal-0294 thermal_trips_update : Found critical threshold [3641]
thermal-0321 thermal_trips_update : No hot threshold
thermal-0200 thermal_get_temperatur: Temperature is 3060 dK
thermal-0219 thermal_get_polling_fr: Polling frequency is 100 dS
thermal-0200 thermal_get_temperatur: Temperature is 3060 dK
thermal LNXTHERM:00: registered as thermal_zone0
ACPI: Thermal Zone [TM00] (33 C)
thermal-0200 thermal_get_temperatur: Temperature is 3070 dK
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iaeed75bdaa16b117d0fa7144ede98db1388f74f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Modify the value of "SPEAKER_GPIO_NAME" in katsu as rt1015p sdb
BUG=None
BRANCH=kukui
TEST=Speaker can work normally in katsu during firmware stage
Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: Ib3672383ab34bb07b4e5eb7f7e8b4549e13c67b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54642
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I2d08fa7506c6230491273f57ee0116927b29abe3
Fixes: 95370e1f ("mb/google/sarien: Add HD Audio verb table")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Correct the Realtek ALC3254 codec name in the comment. The name is used
in the original commit message, and is also present in the Linux kernel
(`sound/pci/hda/patch_realtek.c`).
The file was an exact copy of
`src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h`
added in commit 95370e1f (mb/google/sarien: Add HD Audio verb table).
Change-Id: I43cd73a14e07eb4518e3d44b6f81dff5016da721
Fixes: e3443d87 ("mb/google/drallion: Add new mainboard")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Correct the Realtek ALC3254 codec name in the comment. The name is used
in the original commit message, and is also present in the Linux kernel
(`sound/pci/hda/patch_realtek.c`).
Change-Id: Id8a099297bd8bcebf9734e1beee2449fdcca75c5
Fixes: 95370e1f ("mb/google/sarien: Add HD Audio verb table")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Enable AMD I2S machine driver and configure the devicetree with HID
information so that the machine driver ACPI objects can be passed to the
kernel. Also configure Audio Co-processor(ACP) to operate in I2S TDM mode.
BUG=b:187860242
TEST=Build and boot to OS in Guybrush. Ensure that the ACPD device is
enabled in the appropriate scope in SSDT.
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I528f90d81a418236e512a1e0840ff44c3a3a983e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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The handler is the same on all Bay Trail mainboards. Factor it out.
Change-Id: Ia1b6faaca4792cda5f14948d23498182bf4bb2c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54415
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Move discrete TPM in the devicetree to avoid emitting the following
message: "Using default TPM ACPI path: '\_SB_.PCI0.LPCB'"
There is no corresonding ACPI device for 1f.5 PCI device. Therefore,
move the discrete TPM to a device that has the corresponding ACPI
device node. Functionality should remain the same.
BUG=b:187518267
Change-Id: Ie9ec70336d5651c87f06f8b357abd1bfdb1cc06b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
|
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Enable macronix SPI config on herobrine board.
BUG=b:182963902
Change-Id: I505ee95d9f2ca16baf244135b3e2e8fe72f93491
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
In order to use the USB WWAN module in USB mode (as opposed to PCIe),
the PCIe RP must be turned off at the FSP level. The `probe` statement
in the devicetree unfortunately takes effect too late, because the UPDs
for disabling/enabling PCIE RP belong to FSP-M (romstage), whereas
fw_config probing for devicetree is done in ramstage.
Add a new variant-specific file which will handle manually setting the
UPD based on FW_CONFIG instead.
BUG=b:180166408
TEST=set CBI FW_CONFIG field to LTE_USB, see message in console,
set field to LTE_PCIE, do not see message in console.
Change-Id: Ica2f64ec99fa547e233012dc201577a14f6aa7d7
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54633
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This changes updates mainboard properties by adding DFP number, PLD
and power_gpio for each DFP.
BUG=b:186521258
TEST=Validated Retimer firmware upgrade along with upstream kernel under
no device attached scenario.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I18f29ce5f8450a8b0f8208a60b8b607f9f0d8817
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52714
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Along with upstream kernel for Retimer firmware update, coreboot defines
power control for each DFP respectively under host router. This change
removes the power_gpio from baseboard. Individual DFPx power_gpio will
be added once the dependent definition is complete.
BUG=b:186521258
TEST=Build image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Iec2437ab20d283d080752a80aa4514aa9af6897e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52711
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
We recently added GPIO definition for PCIE vGPIO for Alder Lake.
We also need to disable GPIO dynamic PM for this community which is
already done for other communities as well.
BUG=b:188392183
BRANCH=None
TEST=Code compiles and Check if dynamic PM for GPIO COMM3 is also
disabled
Change-Id: I2f8645b8f4a9995e727a7623af97531c5de52892
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54383
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Most boards use `device lapic 0 on` with zero written in decimal.
For the sake of consistency, update the remaining boards to follow suit.
Change-Id: I1d3b1ac107e33aae11189cdd5e719b8e48b10f08
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Add ELAN Touchpad device under I2C0
BUG=b:188373661
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com>
Change-Id: I15b9cb0d0276b5e2dd06694530cc35e5643efb9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52936
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The patch enables HECI1 interface to allow OS applications to communicate
with CSE.
TEST=Verify PCI device 0:16.0 exposed in the lspci output
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I73acdd99788f9b60b7bcea372145e9694a124174
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54210
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable/disable LTE function based on LTE bit of FW_CONFIG.
The LTE function settings are included GPIO settings, USB port settings and
power off sequence.
BUG=b:187797408
BRANCH=dedede
TEST=Build and test the change on cret.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ib926e99aaf9df433a7cff71180ee55431d69f718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
To support gpio reset SoC, we need to pass the reset gpio parameter to
BL31.
TEST=execute `echo b > /proc/sysrq-trigger` to reboot system
Change-Id: I1a55216c0d5a00bbdb373d931bd50ebe7ca5694f
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Configure DDI-0 connector type to DP.
BUG=b:187856682
TEST=Build and boot into OS
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Ic8af14509b0d246c5c2da6e1a48991384471e69f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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TCSS OC pins have not been correctly configured for volteer.
This patch fills the value from devicetree to correct the OC pins
mapping.
BUG=b:184660529
BRANCH=None
TEST="emerge-volteer coreboot chromeos-bootimage", flash volteer2 and
verify CpuUsb3OverCurrentPin UPDs get set correctly.
Change-Id: I12da755a1d3b9ec3ed0a2dbfb0782313dd49c7e9
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Initialize and calibrate DRAM in romstage.
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com>
Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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DPTF parameters from thermal team.
1. Modify TSR1 sensor as charge sensor.
2. Modify P-state parameter
BUG=b:180641150
BRANCH=dedede
TEST=build and verified by thermal team.
Change-Id: I43002db61de650d29cd85944a4eaea1b2f99aec4
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52755
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Samsung DDR4 memory part K4AAG165WB-BCWE 16Gb
index was generated by gen_part_id
BUG=b:180986354
TEST=none
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I94b950b51b41767676ab3ddf89e88860c42f5f1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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volta will use different wifi SAR from voxel.
Using clamshell mode of fw config to decide to load volta wifi sar.
BUG=b:184820057
TEST=build and verify wifi power as expect.
Cq-Depend: chrome-internal:3824093
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I000aefca63346c70556688f232ca54360b3badef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54051
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PCIE6 only needed when use the PCIE LTE.
BUG=b:180166408
BRANCH=none
TEST=FM350 can/can't be detected when enable/disable this config.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9dce05fdb6eb956a054d3815ff706b94f0d3fc37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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1) USB sub-board
2) SD sub-board
3) GSC
4) Keyboard backlight
5) Audio sub-board
6) LTE module
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I74ca5ab5366a17e9e1784ec872b9cd77f8663c7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54097
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure USB HUB_RESET_L gpio to high.
BUG=b:187485847
TEST=Build and boot from USB to OS, check the USB function.
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I94e4806c7463030df31f8d819510f9533a622f2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Select GOOGLE_SMBIOS_MAINBOARD_VERSION allows querying
board revision from the EC.
BUG=b:187904819
TEST=1. emerge-guybrush coreboot chromeos-bootimage
2. flash the image to the device and check board rev
by using command `dmidecode -t 1 | grep Version`
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I48dc83d85cfc49e2e4155e389814fce08693c4bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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The CBFS mcache size default was eyeballed to what should be "hopefully
enough" for most users, but some recent Chrome OS devices have already
hit the limit. Since most current (and probably all future) x86 chipsets
likely have the CAR space to spare, let's just double the size default
for all supporting chipsets right now so that we hopefully won't run
into these issues again any time soon.
The CBFS_MCACHE_RW_PERCENTAGE default for CHROMEOS was set to 25 under
the assumption that Chrome OS images have historically always had a lot
more files in their RO CBFS than the RW (because l10n assets were only
in RO). Unfortunately, this has recently changed with the introduction
of updateable assets. While hopefully not that many boards will need
these, the whole idea is that you won't know whether you need them yet
at the time the RO image is frozen, and mcache layout parameters cannot
be changed in an RW update. So better to use the normal 50/50 split on
Chrome OS devices going forward so we are prepared for the eventuality
of needing RW assets again.
The RW percentage should really also be menuconfig-controllable, because
this is something the user may want to change on the fly depending on
their payload requirements. Move the option to the vboot Kconfigs
because it also kinda belongs there anyway and this makes it fit in
better in menuconfig. (I haven't made the mcache size
menuconfig-controllable because if anyone needs to increase this, they
can just override the default in the chipset Kconfig for everyone using
that chipset, under the assumption that all boards of that chipset have
the same amount of available CAR space and there's no reason not to use
up the available space. This seems more in line with how this would work
on non-x86 platforms that define this directly in their memlayout.ld.)
Also add explicit warnings to both options that they mustn't be changed
in an RW update to an older RO image.
BUG=b:187561710
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I046ae18c9db9a5d682384edde303c07e0be9d790
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable DPTF functionality for Alder Lake based brya
BRANCH=None
BUG=b:188028732
TEST=Built and tested on brya board
Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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modify USB OC pin setting for Shuboz/Jelboz/Jelboz360
Shuboz/Jelboz:
usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0
usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0
usb_port_overcurrent_pin[2] = "USB_OC_PIN_1" # USB A1
usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1
Jelboz360:
usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0
usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0
usb_port_overcurrent_pin[2] = "USB_OC_NONE" # NONE
usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1
BUG=b:182879559
BRANCH=zork
TEST=emerge-zork coreboot, validate the OC mapping.
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
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Redefine GPIO_EC_IN_RW to GPP_F17
Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com>
Change-Id: I428eb8db34c80d38899a2b823ec7193de4a8f5e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Select touchscreen(s) based on touchscreen source provisioned in SSFC of CBI (higher 32 bits of FW_CONFIG in coreboot).
The reason is to avoid to enable multiple touchscreen ICs with the same slave address.
BUG=b:186609348
TEST=build and boot to OS.
Change-Id: I087ea677a8865fc8c5b3f7c9773bd7f97924dbb3
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
|
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Enable SCP SRAM to allow module in SCPSYS to access DRAM.
TEST=AFE acess DRAM successfully
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I40862f8d74e5aa17361f1c91ea31a10b0a4ffb31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54014
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Remove TSR2 and use DPTF parameters from internal thermal team.
BUG=b:175938681
TEST=build and boot to OS.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If0ec1ec48b8971efe87f1f8d10332a9c16352122
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raymond Wong <wongraymond@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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In order to support wake on WLAN events, configure the wake resource.
BUG=b:186011392
TEST=Build and boot to OS in guybrush. Ensure that WiFi power resource
is added to SSDT.
Device (\_SB.PCI0.GP20.WF00)
{
Name (_UID, 0x38B82CBC) // _UID: Unique ID
Name (_DDN, "WIFI Device") // _DDN: DOS Device Name
Name (_ADR, 0x0000000000000000) // _ADR: Address
}
Scope (\_SB.PCI0.GP20.WF00)
{
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x08,
0x03
})
}
Change-Id: Ic238d9606aea20c058e9b47093693f10b14e6288
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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The 448KB size of the GBB is larger than is needed, so adjust it down
to the minimum size needed.
BUG=b:186761897
TEST=Build & Boot guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7a24945cd9ecc8872871f57b09ca71fc40e92473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add audio codec module RT5682 in project and define GPIO_137 in the
override_table for SSFC framework to adjust IRQ configuration.
BUG=b:182221327
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682I or DA7219 then check whether device tree is updated correspondingly by disabling unselected one.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I202f71f57ad2db84fb90b52f9ffd7a1fd05494a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
|
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Create the chronicler variant of the volteer reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:187318819
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_CHRONICLER
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Iebfea87b7c4cfc2a83e88a6c479a0842774ae018
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
|
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Disable HSBIAS sense setting.
BUG=b:184103445
TEST=boot to check cs42l42 is functional.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I12c0e0a0f7490d35d36fe8ccbc940f29e1bb7976
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Probe the fw_config for RT1015 speaker amplifier operation mode and
enable it accordingly in the device tree.
BUG=b:180570923
BRANCH=dedede
TEST=ALC1015Q-VB drive speaker OK
Change-Id: I756bfa6f604ed320de9a515821979aa95c869ebf
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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Add support for GPIO and SPD driver for pirika
BUG=b:184157747
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
Change-Id: Id367a83b04aad62b7deabae99b3f91905a2fc46c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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Update LTE USB port configuration at run-time after probing the firmware
config. By default the concerned USB port takes the Type-A port
configuration.
BUG=b:186380807
BRANCH=dedede
TEST=Build and boot to OS in metaknight
Change-Id: I5ad5a1670adef54075923cf912fb41a1ce776155
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Raymond Wong <wongraymond@google.com>
|
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This callback is required to update the devicetree config at run-time
after probing the firmware config.
BUG=b:186380807
BRANCH=dedede
TEST=Build and boot to OS in metaknight.
Change-Id: I857211bfc4beb36ab225f3786c1707336a34aae9
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Raymond Wong <wongraymond@google.com>
|
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Add EMCP LPDDR4X DDR FEPRF6432-58A1930 for ram id 9.
BUG=b:186141919
BRANCH=kukui
TEST=New Emcp can boot normally on kakadu/katsu
Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: Ieaf05a0a7b0c0671c07b0df29319ebd91fe63e57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54009
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I1d6ecdb31eef65d2e96d9251348390aa8598be6c
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
