summaryrefslogtreecommitdiff
path: root/src/mainboard/google
AgeCommit message (Collapse)Author
2021-11-16mb/google/brya/var/redrix: Update dsm parameters for speeker/tweeterWisley Chen
For tuning, redrix needs differnet dsm paramters file for L/R speeker/tweeter. BUG=b:204841998 TEST=build Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I6f93603a6809f9a5aea9f2e554935de5d0457286 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-16soc/mediatek/mt8186: add early initialization for eMMCRex-BC Chen
Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to access eMMC in the very early stage (for example, depthcharge needs it 20ms after started) so we have to start initialization in coreboot. TEST=boot kernel from eMMC ok BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I3bc06b1fc506b1d6f54f7f456117d22477a87e29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-16mb/google/corsola: Configure eMMC and SD CardWenbin Mei
The Corsola reference design has both eMMC and SD Card interfaces so we have to configure both in RAM stage. TEST=boot kernel from eMMC and SDCard ok BUG=b:202871018 Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: I0fa8712eb61685a305dc5dd49cc2e55f1f0eecd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-16soc/mediatek/mt8186: Configure eMMC and SD CardWenbin Mei
The Corsola reference design has both eMMC and SD Card interfaces so we have to configure both in RAM stage. TEST=build pass BUG=b:202871018 Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: I2f26a8a11edd29a80a7195e3a324151d66ecb293 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-16mb/google/brya/var/vell: Generate LP5 RAM IDKevin Chiu
Add the support LP5 RAM parts for vell: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) BUG=b:204284866 TEST=emerge-brya coreboot Change-Id: I49745948ebdb25fd98e285defd75714f80271968 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2021-11-16mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_LRob Barnes
In CL:3248796 GPIO_5 was made the default for SD_AUX_RESET_L. No variant is actually using GPIO_5 for SD_AUX_RESET_L. Making GPIO_69 the default and only overriding to GPIO_70 for guybrush bid==1. BUG=b:202992077 BRANCH=None TEST=Build and boot guybrush, SD card works Change-Id: I6546ad9961f6f7146aa3aefc35d39a2eb282a252 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-15mb/google/brya/var/redrix: Hook up two missing sensorsWisley Chen
Redrix has 4 thermal sensors, so add the missing sensors settings. BUG=b:200134784 TEST=build and verified by thermal team. Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ia9c58129d439ade21e96896c5e593cd08a627603 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-11-15mb/google/herobrine: Use same I2C/SPI configs for piglin and hoglinShelley Chen
As Hoglin variant was recently added, need to make sure that it uses the same configs as piglin. BUG=b:197366666 BRANCH=None TEST=create hoglin image and make sure that it boots on CRD 2.0 Change-Id: I14497a205262ac1081c24631e4fd8d39bb804fce Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59273 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-15Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016. This relands commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: The original CL did not handle some devices correctly. With the fixes: * commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables) * commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early GPIO tables) * commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage This CL also fix the following platforms: * Change to always trusted: cyan. * Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus, poppy, reef, volteer. * Add to both Makefile and early GPIO table: zork. For mb/intel: * adlrvp: Add support for get_ec_is_trusted(). * glkrvp: Add support for get_ec_is_trusted() with always trusted. * kblrvp: Add support for get_ec_is_trusted() with always trusted. * kunimitsu: Add support for get_ec_is_trusted() and initialize it as early GPIO. * shadowmountain: Add support for get_ec_is_trusted() and initialize it as early GPIO. * tglrvp: Add support for get_ec_is_trusted() with always trusted. For qemu-q35: Add support for get_ec_is_trusted() with always trusted. We could attempt another land. Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15mb/google/brya/var/felwinter: Disable PCIE port 6Eric Lai
PCIE port 6 is empty as per schematics. BUG=b:206047996 TEST=PCIE port 6 is disabled. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I30fa897c9310c44545e3df670895639a5144e1de Reviewed-on: https://review.coreboot.org/c/coreboot/+/59243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15mb/google/brya/var/felwinter: Remove USB2 port 0Eric Lai
USB2 port 0 is empty as per schematics. BUG=b:206047996 TEST=USB2 port 0 is disabled. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I45d467a80c23d82dc33dcbed176430a758eea403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15mb/google/brya/var/felwinter: Enable garage pen detectionEric Lai
Enable garage pen detection. BUG=b:197912223 TEST=Check evtest can trigger event when toggling the switch. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib5929c876d1a0da34dadd7997a61ab8e75acbbb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridgeMalik_Hsu
Enable RTD3 driver for PCIe-eMMC bridge, If the board version is less than 1, do not enable RTD3 driver. BUG=b:204469567 TEST=Boot into eMMC storage and perform suspend stress 100 cycle passed Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I5836d65cedfe3907af2c4c33de7a396c4bb8b727 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15mb/google/brya/variants/gimble: Update PL1 min valueSumeet Pawnikar
Update PL1 minimum value from 3W to 12W as per the thermal design discussed in this bug 203371203 comment #10. BUG=b:203371203 BRANCH=None TEST=Build and boot the gimble system Change-Id: Id66cfb6f6dc0217bd4d83eae1d66ad867a1bdb46 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15mb/google/brya/var/kano: Add thermal sensor settingsDavid Wu
Kano has 3 thermal sensors, so add the missing sensor settings. BUG=b:205648035 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I0da25f142149f94c83fdf7b2ba2cb8694cddb412 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-11-15mb/google/brya: Create vell variantShon Wang
Create the vell variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:205908918 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_VELL Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Change-Id: Ide8ba1c0dd9b5d9ad90556053abf2a597136a10c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15mb/google/corsola: Add VMCH and VMC for regulator interfaceRex-BC Chen
Add VMCH and VMC for providing power of SDCard. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I50fc87415086eb22ff35d157dba38cfd7594cc40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek/mt8186: add USB supportRex-BC Chen
1. Enable and setup USB drivers. 2. Pull up to a weak resistor for USB3_HUB_RST_L and we reset the hub via GPIO149. TEST=boot kernel from USB ok BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ifcc11d51b0c1e495477957111e6021ef8275f629 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15mb/google/corsola: Implement regulator interfaceRex-BC Chen
Use regulator interface to use regulator more easily. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ied43cba51036c62a120df2afffeb63b5d73f012b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15mb/google/corsola: add configuration for kingler and krabbyRex-BC Chen
The 'corsola' reference design will include two implementations with different BOM selections - 'krabby' and 'kingler'. TEST=none BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Iaf9c6af1a395030937a9a5c00e95d7246ddcb6eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/59249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek/mt8186: Add support for PMIC MT6366James Lo
Add basic support for VCORE/VDRAM1/VDDQ of MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com> Change-Id: I22e30421560a32f4a9e15899e8150376b1414494 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-13mb/google/guybrush: Add variant_espi_gpio_tableRob Barnes
Add separate gpio table for early eSPI bus init. Remove espi GPIO from early_gpio_table. This allows for initializing eSPI separately from other GPIOs. Simplify verstage_mainboard_early_init. BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-11-13Revert "mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 setting"David Wu
This reverts commit ba6fdc892d62741e456ac5628fcd6f869c4cb9af. Reason for revert: Refer to intel doc #627075 (Intel_600_Series Chipset_Family_PCH_GPIO_Impl_Sumry_ Rev1p5p1), GPP_R6 ~ GPP_R7 should be NF3 for dmic. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I460fd99b4ad4b9c470f692032ff7ea2b51cad388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-12google/stout: Remove duplicate recovery mode switch entryKyösti Mälkki
Change-Id: I6e742b9d5256da2b7edcca0efda4faf999207465 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-12google/butterfly: Refactor get_recovery_mode_switch()Kyösti Mälkki
Do not place console output in low-level GPIO functions. The caller of get_recovery_mode_switch() is in vboot_logic.c that is linked in romstage. So presumably recovery mode is broken and is not fixed with this commit either. Change-Id: I2a0fdbb370d54898c72adb29a0e9b990a5fc0ce1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-12mb/google/trogdor: Modify BOE panel_id for mrblandZanxi Chen
Modify BOE panel_id for mrbland due to hardware changes. BUG=b:205166230,b:198548221 BRANCH=trogdor TEST=emerge-strongbad coreboot Change-Id: I65fecd854c4e3443edc07a44a1d43572d5030e4c Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58995 Reviewed-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-12mb/google/brya/var/primus: Disable autonomous GPIO power managementCasper Chang
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=b:201054849 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Change-Id: If5a99a96e5d4b84be3f2c1165283ce249ca75d58 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-12google/deltaur,drallion,sarien: Refactor ChromeOS GPIOsKyösti Mälkki
Low-level GPIOs should not depend on late cros_gpios that should be guarded with CHROMEOS and implemented for the purpose of ACPI \OIPG package generation. Change-Id: Ibe708330504bc819e312eddaf5dfe4016cda21a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-12mb/google,intel: Add ChromeOS GPIOs to onboard.hKyösti Mälkki
Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-11mb/google/brya/var/felwinter: Enable SaGvEric Lai
Enable SaGv. BUG=b:198235324 TEST=Boot into without issues. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3cbff8d28bb5b5bfdad323f348b9f880245d049d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11mb/google/brya/var/kano: Configure USB2 and USB3 portDavid Wu
Disable unused USB2 and USB3 port BUG=b:192370253 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia2fa10fb21e0a42e51728bc3d78163ca213f8d91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11mb/google/brya/var/kano: Add gpio-keys ACPI node for PENHDavid Wu
Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. BUG=b:192415743 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia36119678cfd5c65a62685d3312537d9aa21e83b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-11-11mb/google/guybrush: Define ACPI Power Resources for FPMCUKarthikeyan Ramasubramanian
Currently all the power sequencing for FPMCU is done explicitly in different stages of coreboot. This can all be done by adding ACPI power resources for FPMCU and clean up the unused code. Here is the expected power sequence: PowerUp : Assert EN_PWR_FP -> 3 ms delay -> De-assert FPMCU_RST_ODL Shutdown : De-assert EN_PWR_FP -> Assert FPMCU_RST_ODL Reboot : Shutdown -> 200 ms delay -> PowerUp BUG=None TEST=Build and boot to OS in Guybrush. Ensure that the FP is able to unlock the system after the first login attempt. Ensure that the FP is able to wakeup the system. Observed that the power resource is added correctly in the FPMCU ACPI object Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 { PR01 }) Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot { PR01 }) PowerResource (PR01, 0x00, 0x0000) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x01) } Method (_ON, 0, Serialized) // _ON_: Power On { \_SB.CTXS (0x0B) \_SB.STXS (0x20) \_SB.STXS (0x0B) } Method (_OFF, 0, Serialized) // _OFF: Power Off { \_SB.CTXS (0x0B) \_SB.CTXS (0x20) } } Change-Id: I52322eaecf6961ff9a196ca9ab2d58b7d4599d4f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-11mb/google/brya/var/taeko: Enable CPU PCIE RP 1Joey Peng
Modify settings to enable CPU PCIE RP 1 according to schematics. BUG=b:205504257 TEST=emerge-brya coreboot and can successfully boot with ssd and emmc. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I0f817c860f2b295c6aa84fa1999d374d99f817f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11mb/google/guybrush/dewatt: update dewatt configChris.Wang
copy config from guybrush reference board. BUG=b:204151079 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ide9e002390e59725dc0e45f83280db2a78270993 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-11mb/google/brya/var/gimble: Improve USB2 eye diagram of DB Type-C portMark Hsieh
- Set MAX OC1 to USB2_C1 BUG=b:205676803 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Idcf13ad072ae5d7a897f54adb19e6b2b068609dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2021-11-11mb/google/brya/var/felwinter: Update typeC EC mux portEric Lai
We need to put USB setting in mux order. BUG=b:204230406 TEST=Type C mux configuration is correct. Wrong: added type-c port0 info to cbmem: usb2:2 usb3:2 sbu:0 data:0 added type-c port1 info to cbmem: usb2:3 usb3:3 sbu:0 data:0 Correct: added type-c port0 info to cbmem: usb2:3 usb3:3 sbu:0 data:0 added type-c port1 info to cbmem: usb2:2 usb3:2 sbu:0 data:0 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I19338e162db6145dbeb5830de1a372cf98f779a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-11-11mb/google/brya/variants/gimble: Update audio setting for SmartAMPMark Hsieh
Divide dsm_param_file_name into dsm_param_R and dsm_param_L BUG=b:205684021 TEST=build and check SSDT Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie2db709a63152c1ccee2f7d594284e366ada8a01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59046 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-11mb/google/dedede/var/galtic: update Wifi SAR for convertiblesFrankChu
Add wifi sar for galtic/galtic360/galith360 Using convertible mode of SKU ID to load wifi table. Each Project and SKU ID correspond as below galtic (sku id:0x120000) galith (sku id:0x130000) gallop (sku id:0x150000) galtic360 (sku id:0x260000) galith360 (sku id:0x270000) BUG=b:203741126 TEST=emerge-dedede coreboot chromeos-bootimage \ coreboot-private-files-baseboard-dedede verify the SAR table is correct in each project Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: If4203d176dd717fa62c88d9b4fab8a53847213fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/58734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-11google/beltino,jecht: Refactor ChromeOS GPIOsKyösti Mälkki
Change-Id: I4052baca2d8041b2a6d6fd410fcf99248662d7a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-11ChromeOS: Replace with or add <types.h>Kyösti Mälkki
It's commented in <types.h> that it shall provide <commonlib/helpers.h>. Fix for ARRAY_SIZE() in bulk, followup works will reduce the number of other includes these files have. Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11mb/google/brya: Enable thermal control functionality for tpchSumeet Pawnikar
Enable DPTF based thermal control functionality for tpch device on brya device. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I6a35a101599bb811fcddaabab5296f8c6c12af31 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-09mb/google/brya/var/redrix: Set RFI Spread Spectrum to 6%Wisley Chen
Set RFI Spread Spectrum to 6% for Redrix as RF team request. The default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard as default. BUG=b:200886627 TEST=build Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Id0b42446e9e46ef629b5ca8d5d29faf2d771348d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-09google/trogdor: Update the power on sequence of ps8640xuxinxiong
For the Qualcomm PBL configuration of GPIO, we need to initial the GPIOs for VDD33# and RST# at the beginning of coreboot. According to the pa8640 latest spec v1.4, update the sequence of VDD33# and PD#. BUG=b:204637643 BRANCH=trogdor TEST=verified the waveform of ps8640 at coreboot phase. Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Change-Id: Ia378aafa49ec462c990501ce48721e330d9648b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58994 Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-09mb/google/dedede/var/metaknight: Probe and enable amplifier operation modeDavid Wu
Probe the fw_config for RT1015 speaker amplifier operation mode and enable it accordingly in the device tree. BUG=none BRANCH=dedede TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I2de1487b7f4767e9ba6432174c39feeb25f9534c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09mb/google/dedede/var/bugzzy: Adjust I2C speedSeunghwan Kim
This change adjusts all I2C speed to lower then 400KHz. The rise_time_ns and fall_time_ns values for each port are capured by a scope. BUG=None BRANCH=dedede TEST=built and verified adjusted I2C speed < 400KHz Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I9504608dd8d9a5f5a3848ef34691557942c21023 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09mb/google/dedede/var/magolor: Enable ELAN touchscreen for magnetoTyler Wang
Add ELAN touchscreen support for magneto. BUG=b:203122673 TEST=Build and verify that touchscreen works. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ie86692901113e952c597fcfc6c58e7ee0fc172fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/58967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09mb/google/dedede/var/bugzzy: Update charger performance control tableSeunghwan Kim
Update charger performance control table of DPTF for bugzzy. Since the EC change chromium:197776876 modified maximum charging current to reduce skin temperature, this change adjusts the charging performance table with the modified value. BUG=b:197776876 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I33e176fcf5d380b315ff352c6c65af3b8b93c4b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09mb/google/dedede/var/bugzzy: Enable Wifi SARSeunghwan Kim
BUG=None BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot chromeos-bootimage Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: Ie967ef7fbc19886c631e634a0b0c3f2cf1e490af Reviewed-on: https://review.coreboot.org/c/coreboot/+/58845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09ChromeOS: Fix <vc/google/chromeos/chromeos.h>Kyösti Mälkki
Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-09soc/nvidia,qualcomm: Fix indirect includesKyösti Mälkki
Avoid indirect <vc/google/chromeos/chromeos.h> as the files really only need <security/vboot/vboot_common.h>. Change-Id: Ic02bd5dcdde0bb5c8be0e2c52c20048ed0d4ad94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-06google/guybrush: Move SPI speed overrideKyösti Mälkki
SPI speed override is not related to ChromeOS, thus the location in chromeos.c was poor choice. Change-Id: Ie3db89f252af1f44e9539497c05bdf965565a191 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05mb/google,intel: Fix indirect include bootmode.hKyösti Mälkki
Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-05mb/google: Fix indirect include bootmode.hKyösti Mälkki
Change-Id: I882c567e6bca0982a0d3d44c742777c4d7bd5439 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-05mb/google/corsola: Add NOR-Flash supportRex-BC Chen
Add NOR-Flash drivers to pass verification of flash at verstage. TEST=boot to romstage BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Iee3dd336632b0cf998f5f7c1d118e01e8270e815 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05mb/google/taeko: Update the FIVR configurationsKevin Chang
This patch sets the enable the external voltage rails since taeko board have V1p05 and Vnn bypass rails. BRANCH=None BUG=b:204832954 TEST=FW_NAME=Check in FSP log and run PLT test Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I20ff310d48d3e7073fe5e94d03d29cc55a46d1f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-05mb/google/brya/var/felwinter: Correct typeC EC mux portEric Lai
Type C port2 uses EC mux port0 as per schematics. BUG=b:204230406 TEST=No error message in depthahrge. update_port_state: port C2: get_usb_pd_mux_info failed Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I85218c81018b248c41a2cdaf9360a86e2a7d4d7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-04mb/google/sarien: Add OEM product namesFelix Singer
Add OEM product names from public sources. Change-Id: Ic051aa9c8afabd47e7e9f6ac878190d9904ef757 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-04mb/google/guybrush: Set Gen3 default for all PCIe devicesMatt Papageorge
Currently link_speed_capability is not specified within the DXIO descriptors sent to FSP. This value specifies the maximum speed that a PCIe device should train up to. The only device on Monkey Island that is not currently running at full speed is the NVME but this may not always be the case. BUG=b:204791296 TEST=Boot to OS and check link speed with LSPCI to verify NVME link speed goes from 2.5 GT/s to 5 GT/s Change-Id: Ibeac4b9e6a60567fb513e157d854399f5d12aee9 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-04mb/google/brya/var/kano: Update GPIO table for speak and dmicDavid Wu
Refer to intel doc #627075 (Intel_600_Series Chipset_Family_PCH_GPIO_Impl_Sumry_ Rev1p5p1) Set GPIO GPP_S0 ~ GPP_S3 to NF4 and GPP_R6 ~ GPP_R7 to NF3. BUG=b:204844177 b:202913826 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Iafe52ec3a6deead1d2fc5ada0f2842cf2a9f41a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CT Lin <ctlin0@nuvoton.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-04mb/google: Add OEM product names for various boardsMartin Roth
All of these names came from public sources. Signed-off-by: Martin Roth <martin@coreboot.org> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Change-Id: I1ed9cc0c1ff63dc415e0cc63fa9d2dcd429a093b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-04mb/google/guybrush/bootblock: add comment on selecting eSPI interfaceFelix Held
Setting the PM_ESPI_CS_USE_DATA2 bit in PM_SPI_PAD_PU_PD results in the eSPI transactions being sent via the SPI2 pins instead of the SPI1 pins. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iad8e3a48496a52c14c936ab77c75dc1b403f47bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-04soc/amd/cezanne/include/gpio: fix GPIO 106 native function namesFelix Held
The name looked a bit odd and the Cezanne PPR #56569 Rev 3.03 confirmed that the native function names don't have the EMMC_ prefix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I917c74afd98f2e2133e160d352f11f08c19a3ec6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-03mb/google/trogdor: Mark kingoftown as supporting Parade PS84640Kevin Chiu
BUG=b:204272905 BRANCH=master TEST=emerge-trogdor coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Ie13ddfef6adfd53adb0a0d3a98995fb00b8a45e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-03mb/google/corsola: Add MediaTek MT8186 reference boardRex-BC Chen
Add mainboard folder and drivers for new reference board 'Corsola'. TEST=build pass BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I2d701c03c97d3253effb6e93a2d55dcf6cf02db6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-02Revert "mb/google/brya/var/kano: disabled autonomous GPIO power management"David Wu
This reverts commit 287cc02c007fd47b515d19389ea00ea0461fd5a1. Reason for revert: it will break s0ix. BUG=b:201266532 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I393077b26e2cdeae055d8eea1030754602e94ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/58809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02mb/google/volteer: allow MKBP devices and disable TBMC deviceFrankChu
Enable MKBP (Matrix Keyboard Protocol) interface for all volteer family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:171365305 TEST=manual test on Volteer: Volume Up/Down and Power buttons, Tablet Mode switch Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I2bb2e895af17fa4280113e57e2b0ca780af8840e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02mb/google/guybrush: Update STT coefficientsJason Glenesk
Update guybrush STT (Skin Temperature Tracking) configuration settings to values provided by power team after tuning. BUG=b:203123658 Change-Id: I14c69dbe044e4f3f2711be96e5ea80db0686b3eb Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-02mb/google/brya: Correct AT24 NVM address sizeVarshit B Pandya
Currently, the address size field of AT24 NVM is incorrect, and Linux v5.10 kernel logs the message below: at24 i2c-PRP0001:01: Bad "address-width" property: 14 The valid size of the AT24 NVM is 16 bits so modify the value from 0x0E to 0x10. TEST=Boot brya and check the kernel log and see "Bad address-width" error message is not shown. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I6c1ed5334396e0ca09ea0078426a7b5039ae4e8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-11-02mb/google/brask: add the mkbp deviceZhuohao Lee
In order to let the ec passing the key event like recovery and power key to the OS, we need to include EC_ENABLE_MKBP_DEVICE to generate the MKBP device. BUG=b:204519353, b:204512547 BRANCH=None TEST=pressed recovery key and power button in the OS and checked the UI behavior. Change-Id: Ia1d0b9b301994ad9a0f4bf28b75ab0310a1d63a0 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02mb/google/zork/var/vilboz: Generate new SPD ID for new memory partsFrank Wu
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. Hynix H5ANAG6NCJR-XNC 2. Micron MT40A512M16TB-062E:R 3. ADATA 4JQA-0622AD BUG=b:199469240 BRANCH=firmware-zork-13434.B TEST=FW_NAME=vilboz emerge-zork coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I57cca403800d9731a7b689ac9773a7940e83904e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-11-01soc/intel/braswell: Set GNVS DPTE via devicetreeAngel Pons
Introduce the `dptf_enable` devicetree setting to set the DPTE GNVS field, as newer Intel platforms do. Change-Id: I88b746c64ca57604f946eefb00a70487a2fb27c0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-01mb/google/dedede/var/storo: Add fw_config probe for multi audio codecZhi Li
Compatible headphone codec "Realtek ALC5682I-VD" and "ALC5682I-VS" BUG=b:202463494 BRANCH=dedede TEST=ALC5682I-VD or VS audio codec can work normally Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: Ib808ddadef1029d3f06eb2d68164243c386d4905 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-01mb/google/brya/var/brya0: add HPS as generic I2C peripheralDan Callaghan
Some brya0 units have HPS fitted and connected to PCH I2C2, rather than a user-facing camera. Because HPS uses I2C address 0x51, which may conflict with the user-facing camera EEPROM, introduce a new fw_config bit to indicate whether HPS is present. BUG=b:202784200 TEST=FW_NAME=brya0 emerge-brya coreboot chromeos-bootimage TEST=ectool cbi set 6 0x28191 4 # set bit 17 for HPS TEST=flashrom -p internal -w image-brya0.serial.bin Signed-off-by: Dan Callaghan <dcallagh@google.com> Change-Id: I322548bcfccf16ba571396bc88fd6fc03c036a4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58646 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-01mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9755 for braskDavid Wu
Enable DRIVERS_GENESYSLOGIC_GL9755 support for brask. BUG=b:197385770 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If421e0df058b6f2b87267d5e3822940b90062f71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-01mb/google/brya/var/taeko: Add probe for MAX98357+ALC5682I_VSJoey Peng
Add probe function for the "VS" version of the audio amplifier so taeko can recgonize MAX98357 with ALC5682I_VS. BUG=b:202913837 TEST=FW_NAME=taeko emerge-brya coreboot and check taeko can recgonize MAX98357 with ALC5682I_VS Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Id4ff2003ee6a6f6f4ad98694996689e1a84092c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com>
2021-11-01mb/google/dedede/var/kracko: Add Wifi SAR for krackoRobertChen
Add wifi sar for kracko BUG=b:194460420 TEST=emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage Change-Id: I83bca544c9f71142f95ea1137f732c182b3f29b7 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
2021-10-29mb/google/brya/var/brask: Correct the GPIO config of buzzerAlan Huang
GPP_B14 is used by buzzer and should be set to NF1 'SPKR'. BUG=b:198998974 TEST=emerge-brask coreboot depthcharge and verify if the buzzer beeps. Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I84978af152a7117c1f3398a9b7adde161db058dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29mb/google/brya/anahera: Disable autonomous GPIO power managementWisley Chen
With cr50 fw 0.3.22 or older version, it needs to disable autonomous GPIO power management and then can update cr50 fw successfully. BUG=b:202246591 TEST=FW_NAME=anahera emerge-brya coreboot chromeos-bootimage. Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I9137b6264ee80bc9e00dfdc3ab3926bccb4bf47c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29mb/google/brya/var/kano: disabled autonomous GPIO power managementDavid Wu
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=b:201266532 TEST=FW_NAME=kano emerge-brya coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If6783e0df1404c9a353061fb564210aa0d12896e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29mb/google/brya/var/kano: Add fw_config probe for MIPI cameraDavid Wu
Add fw_config probe for MIPI OVTI2740 camera BUG=b:194926283 TEST=FW_NAME=kano emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ic5a7cebf1f5c847c01e951a237af691e0ad6c73d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-28mb/google/brya/var/taeko: add HPS as generic I2C peripheralDan Callaghan
BUG=b:202784200 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Signed-off-by: Dan Callaghan <dcallagh@google.com> Change-Id: I400719d762b001811f809f9549fd030dff9928d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-28drivers/net/r8168.c: Guard against generating power resourceArthur Heymans
Not all platforms need to generate power resources, but the code does not get optimized out at build time because the devicetree gets compiled into a linked list. As this code pulls in some heavy ACPI dependencies that is even implemented with weak empty function it makes sense to optimize out this code using a Kconfig constant. This saves 1.5K in ramstage size on gigabyte/ga-945gcm-s2l. Change-Id: I82289aa7e6e82318417f3b827b86182891dfc2a6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58657 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-28mb/google/guybrush/var/nipperkin: update telemetry settingsKevin Chiu
Currently, the AMD SDLE stardust test fails with incorrect VDD/SOC scale/offset value, it needs to update the two load line slope settings for the telemetry. AGESA sends these values to the SMU, which accepts them as units of current. Proper calibration is determined by the AMD SDLE tool and the Stardust test. VDD scale: 92165 -> 73457 VDD offset: 412 -> 291 SOC scale: 30233 -> 30761 SOC offset: 457 -> 834 BUG=b:200194315 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage pass AMD SDLE/Stardust test Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: If53c173000a276a80247ccb08736280a25948939 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-27mb/google/guybrush: Move EN_PWR_FP from GPIO_32 to GPIO_3Rob Barnes
EN_PWR_FP is used to enable power to the FPMCU. This frees up GPIO_32 for other uses. This move applies to all board except: * Guybrush * Nipperkin board version 1 Add callbacks for variants to override fpmcu shtudown gpio table and fpmcu disable gpio table. BUG=b:202992077 TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure fingerprint still works. Change-Id: I4501554da0fab0cb35684735e7d1da6f20e255eb Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-27mb/google/guybrush: Move GSC_SOC_INT_L from GPIO_3 to GPIO_85Karthikeyan Ramasubramanian
GSC_SOC_INT_L gpio is used by Google Security Chip (GSC) to interrupt SoC when the SoC is in S0 state. Hence use GPIO_85 which is in S0 domain and save the GPIO_3 in S5 domain for other use-cases. This move applies to all board except: * Guybrush * Nipperkin board version 1 Update the GPIO configuration, device tree configuration accordingly. BUG=b:202992077 TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure that the SoC <-> TPM communication is working fine. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I019f10f2f457ab81bcff77ce8ca609b2b40cb2ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/58638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-27mb/google/guybrush: Fix GPIO overrides during verstageKarthikeyan Ramasubramanian
GPIO overrides are defined for verstage. But the overrides are neither enabled nor applied during verstage. Enable the overrides and apply them during verstage. BUG=None TEST=Build and boot to OS in Guybrush. Perform suspend/stress, warm and cold reboot cycling for 10 iterations each. Ensure that all the PCIe devices are enumerated fine. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I510313bf860d8d55ec3b04a9cfdfa942373163f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-27mb/google/brya/var/gimble: disabled autonomous GPIO power managementMark Hsieh
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=b:200918380 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I83cc1a5d80bf23d052e83c9791ef866966a3d9b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58626 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-27mb/google/dedede/var/lantis: Generate new SPD ID for new memory partsWisley Chen
Add new memory parts in memory_parts_used.txt and generate SPD id for these parts: Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL BUG=b:204015941 TEST=run part_id_gen to generate SPD id Change-Id: I78ec575d354a5ae7c014a6050364d0a5214e4e92 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com>
2021-10-27mb/google/dedede/var/driblee: Generate new SPD ID for new memory partsFrank Wu
Add new memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: 1. K4U6E3S4AB-MGCL 2. H54G46CYRBX267 BUG=b:204023388 BRANCH=firmware-keeby-14119.B TEST=FW_NAME=driblee emerge-keeby coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I1b40e24faf8d85f32839a3d44fd936ca7ee7e09f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-27mb/google/guybrush: Remove WWAN_DISABLE GPIOKarthikeyan Ramasubramanian
In-band controls work to enable/disable the WWAN module. Hence WWAN_DISABLE_GPIO is not critical and can be marked as not connected. BUG=b:188415287 TEST=Build and boot to OS in Guybrush. Ensure that the WWAN module is enumerated on boot and reboot. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7fefba3de9c749971911b21ed4712e950cef5a6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-27mb/google/guybrush: Update SD_AUX_RESET_L signalKarthikeyan Ramasubramanian
On all upcoming variants and board versions of existing variants, SD_AUX_RESET_L signal moves from GPIO_69 to GPIO_5. This means all boards except: * All board versions of Guybrush * Nipperkin Board Version 1. Also in Nipperkin, LCD_PRIVACY_PCH signal moves from GPIO_5 to GPIO_18. Configure the gpios accordingly in baseboard, guybrush and nipperkin variants accordingly. Also update the DXIO port descriptor for SD PCIe engine with the corresponding AUX reset GPIO. BUG=b:202992077 TEST=Build and boot to OS in Guybrush & Nipperkin. Ensure that the SD Controller and SD Card are enumerated fine. Ensure that the enumeration is successful after a suspend/resume cycle. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If28810747e6b4eaae2a693a98e1adc830f80bcf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-27mb/google/brya/var/kano: Disable unused PCIE root port in devicetreeDavid Wu
The baseboard enables PCIe RPs 6, 8 and 9, but kano doesn't use these. Having them enabled will occasionally cause suspend attempts to fail, therefore disable them in the overridetree. BUG=b:203389490 b:192370253 TEST=FW_NAME=kano emerge-brya coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie2b82cff6d910c961eeb56704dcbae2bdc2a8c53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-27mb/google/guybrush: Reconfigure GPIO_5Karthikeyan Ramasubramanian
On Guybrush, pen is stuffed and GPIO_5 is used to enable Pen power. On Nipperkin board version 1, pen is not stuffed and instead the GPIO is used to control LCD Privacy settings. On upcoming Nipperkin board versions and other variants, GPIO_5 is not used. Configure GPIO_5 accordingly. BUG=b:202992077 TEST=Build and boot to OS in Guybrush. Ensure that the configuration is retained on existing boards. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I2aa2f16282b91f157701212ee27ddd2e89918767 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-27mb/google/dedede/var/drawcia: Generate new SPD ID for new memory partsWisley Chen
Add new memory parts in memory_parts_used.txt and generate SPD id for these parts: Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL BUG=b:204014463 TEST=run part_id_gen to generate SPD id Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I43df98d84c6a274d6f96c8818ce6acff9337d8d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-27mb/google/dedede/var/haboki: Generate new SPD ID for new memory partsWisley Chen
Add new memory parts in memory_parts_used.txt and generate SPD id for these parts: Micron MT53E512M32D1NP-046 WT:B Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL BUG=b:204015944 TEST=run part_id_gen to generate SPD id Change-Id: Icf2f7352a4bd6a58e3e7abdcaac823b863984732 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-27mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 settingDavid Wu
Correct GPIO GPP_R6 and GPP_R7 setting to NF2 (DMIC_CLK1 and DMIC_DATA1). BUG=b:197385770 TEST=emerge-brask coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia3813306f8c7b69fe5cf0e188c55256b68d329ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/58578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-27mb/google/brya/var/kano: Update the FIVR configurationsDavid Wu
This patch set disables the external voltage rails since kano board doesn't have V1p05 and Vnn bypass rails implemented. BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia1f3f4b2ada0154c716aedd521d4151124411ba3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-27mb/google/guybrush/var/nipperkin: config eSPI alert as in-bandKevin Chiu
To prevent unexpected alert from eSPI to SOC, configure this alert pin to in-band. BUG=b:199458949,b:203446084 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I18d38fe504bd9f2069b9977d5a35729691f672d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 09:49:00 +0000