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Linux always "turns on" a PowerResource when it boots, regardless of
_STA, so the _ON routine should be idempotent. In this case, it all is,
except for the LTR restore, which would restore a value of 0 when _ON is
run the first time, which means that LTR is disabled on the root port
from then on, as the save/restore routines will keep saving/restoring
that 0. THis patch fixes the problem by moving the power checks from
PGON/PGOF to GCOO/GCOI.
BUG=b:244409563
TEST=boot agah and verify that LTR is still enabled on the root port
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4ed78323608eede5b8310598f1f1115497ab2b5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67278
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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The Linux kernel runtime D3 framework expects a PCIe device to have a
power resource in order to be properly power-manageable. The _PR0/_PR3
values were pointing at the PEG0 Device, which is not a PowerResource,
so this must have confused the RTD3 framework and RTD3 was not
functional. Removing the _PR0/_PR3 fixes the problem.
BUG=b:243888246
TEST=echo auto > /sys/bus/pci/devices/0000:01:00.0/power/control;
sleep 10;
echo on > /sys/bus/pci/devices/0000:01:00.0/power/control
After this there are no longer errors seen in dmesg about failing
to place the device into D0.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I83fa1e5fabd3257b097c10e7a13c9861872685ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Mostly there are too many extraneous `\_SB.PCI0.` prefixes, also a few
minor cleanups, but nothing functional.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I79d919d2f04f57232f8f6a4e4d0690833faeb834
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Similar to the prior CL (commit db8ad5e), do the same register dance
before/after GCOFF.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8fecba40c5a5af11e24f82db07face3ce10481bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67086
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Refactor AMD DPTC tablet mode in preparation for adding low/no battery
DPTC settings.
1. Refactor and simplify acpigen_write_alib_dptc() into the following
functions:
- acpigen_write_alib_dptc_default()
- acpigen_write_alib_dptc_tablet()
2. Add device tree register value dptc_tablet_mode_enable to control
whether DPTC tablet mode is enabled for a variant.
3. Add dptc.asl to perform the necessary ACPI checking before modifying
the DPTC settings.
BRANCH=none
BUG=b:217911928
TEST=Build zork
TEST=Build nipperkin
TEST=Boot skyrim
Change-Id: I2518fdd526868c9d5668a6018fd3570392e809c0
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Lists of GPIO PINS being updated:
SPKR_INT_L_R
RST_HP_L
SOC_HDMI_HPD_L
SOCHOT_ODL
SOC_FPMCU_INT_L
EN_PP3300_WLAN
BUG=b:24410269
TEST=Build and boot Google/Rex to ChromeOS.
Change-Id: If2fb354f931217c09a6c1c81ca780cb121b24468
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67449
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable touchpad for Google Rex.
BUG=b:245866939
TEST=Build and boot to Google Rex. Verify touchpad works.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I49fdd72bf3350085e82411b95edcd6a9a09d2df5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67471
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
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Add GPE route for GPP_B.
BUG=b:245866939
TEST=Build and boot to Google Rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I28066a6cc75908f8ceefbdbf8c088c56833606ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add functionality such that the FPMCU is power cycled and has its reset
sequenced on boot.
This has been added such that we do not need to update the bootblock.
We are required to do this as bootblock exists in read-only flash for
devices that have already been manufactured and so have no method of
updating the sequencing there.
Power remains off during coreboot (after briefly being turned on in the
unchangeable bootblock).
Once control is handed over to the Kernel, it takes care of sequencing
the power and reset appropriately and ensures the FPMCU is unpowered for
>200ms on boot.
BUG=b:240626388
TEST=Confirmed FPMCU is still functional on Vell and Anahera.
Confirmed power is off for approximately 6 seconds on boot (target
>200ms).
Confirmed reset is de-asserted approx 5ms after power application
(target >2.5ms)
Change-Id: I9694f8837e0a72eaed42a5eeee92b0f120269086
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66915
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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TEST=Boot to OS on nivviks/nirwen and check that stylus GPIOs are
configured based on fw_config.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ibbe9f379abe10a741642e11d4833d3a53489693a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66929
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Config I2C high / low time in device tree to ensure I2C
CLK runs accurately at I2C_SPEED_FAST (400 kHz).
EE measured touchscreen/audio runs at 385.5/397.9kHz after tuning.
BUG=b:244403643
BRANCH=firmware-dedede-13606.B
TEST=Build and check after tuning I2C clock is under 400kHz
Change-Id: I7d9503e5f92295432e31f09ae791eaa18eac9d4d
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that the driver skips
initial probe during kernel boot and prevent privacy LED blink.
BUG=b:194979741
BRANCH=firmware-brya-14505.B
TEST=Build and boot skolas to OS. Verify entries in SSDT.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3c32dd71ab454227b15913bda7f542230e5568db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Historically, ChromeOS devices have worked around the problem of OEMs
using several different parts for touchpads/touchscreens by using a
ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel)
to indicate that the device may or may not be present, and that the
driver should probe to confirm device presence.
Since c636142b, coreboot now supports detection for i2c devices at
runtime when creating the device entries for the ACPI/SSDT tables,
rendering the 'probed' flag obsolete for touchpads. Switch all touchpads
in the tree from using the 'probed' flag to the 'detect' flag.
Touchscreens require more involved power sequencing, which will be done
at some future time, after which they will switch over as well.
TEST: build/boot at least one variant for each baseboard in the tree.
Verify touchpad works under Linux and Windows. Verify only a single
touchpad device is present in the ACPI tables.
Change-Id: I47c6eed37eb34c044e27963532e544d3940a7c15
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67305
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch enables AC plug/unplug for resume.
BUG=b:188457962
BRANCH=grunt
TEST=Verified AC plug/unplug wakes up Treeya.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I10480f8224b909fefe42d46d7c03fc9d3fe5abfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch enables AC plug/unplug as resume signals.
BUG=b:188457962
BRANCH=Zork
TEST=Verified AC plug wakes up Ezkinil.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: Ib1af6ff9f18544ec6a86e34588fb4d9e8cd3bab2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Follow the Thermal_paramters_list-0902.xlsx to modify DPTF parameters
and fan table.
1. Modify CRT of TSR0 - TSR3 to 97.
2. Modify TCC offset to 6.
3. Update new fan table.
BUG=b:244657172
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I751bc5442f64428c383034755cd5d74fbd0ea91e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67314
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Modify fan speed/duty table follow "Duty table.xlsx".
BUG=b:244262869
TEST=Boot to ChromeOS. Using SDV system, enter duty value, and then
system feedback fan speed.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Id5e885b96624d5fc31f1d42e3582c3ab01e08458
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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The PCIe WWAN module used on rex requires control over 4 signals to
successfully power it on. It is desirable to do this before passing
control to the payload, because the modem requires a ~10 seconds
initialization phase before it can be used.
The corrected sequence looks like:
1) Drive device into full reset and enable power in bootblock
2) Deassert FCPO in romstage, after power rails stabilize
3) Deassert WWAN_RST#, then WWAN_PERST# in ramstage
BUG=b:244077118
TEST=FM350 could be enumerated via lspci
Measured signals to check start-up Timing Sequence, tpr/ton1/ton2.
Tpr = 572mS
Ton1 = 6.3s
Ton2 = 6.3+4.17ms
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: I6cda9348ef7f54efe5ba2358040596a1c2da1b13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67332
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This area relates to storing of AP RO verification information.
CONFIG_VBOOT_GSCVD is enabled by default for TPM_GOOGLE_TI50 and
guybrush is using TPM_GOOGLE_CR50.
Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Change-Id: I896b871bf2ac64e334514b979add9b8ac2c43945
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
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Change the name of the CALIBRATION_REGION definitions used in two
separate locations. This conflict was causing an error for the
lint-001-no-global-config-in-romstage test.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If6734f2a7d9be669586ea350fb9979fcd422b591
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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dptc_enable is being treated as a bool, so convert to explicitly be a
bool.
BRANCH=none
BUG=b:217911928
TEST=Build zork
TEST=Build guybrush
TEST=Build skyrim
Change-Id: I0e93d892b3b8016221812c8b9ec6c257dcf13ef5
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67188
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Pass the reset gpio parameter to BL31 to support SoC reset.
TEST=build pass.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ifdfbd6bd82f64b084f6349cb617443053c89a3f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67357
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The implementations of register_reset_to_bl31() are the same for
MedaiTek platforms, so we extract them to soc/common/bl31.c.
BUG=None
TEST=build pass
Change-Id: I297ea2e18a6d7e92236cf415844b166523616bdf
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The T4 of ANX7625 power on sequence should be larger than 0ms, but it's
-59ms now. So add 70ms delay between DSI_TE and LCM_RST.
BUG=b:242352915
TEST=The sequence T4 is larger than 0ms when power on.
Change-Id: I6b888707ec3c0612e396564e77c4cdbe92614dc5
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Initialize winterhold devicetree.
BUG=b:241196632
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I9fe224cdc2acb1f13d3bf9341b487892c15f8ea2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Follow FT6_SOC_GPIO_PM&Strap_20220815A.XLSX
update Gpio setting
BUG=b:240824497
BRANCH=None
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I2086c326cbf46ba6378d18d37dcbbe9fafa6b2bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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GSPI0 pads required muxing to NF8. Support for extended
native functions was added in
commit b6c32d7fe4ea98ba8b3a10cb5ce46448801855b8
BUG=b:244610269
TEST=build and booted on Rex
Change-Id: Iab4e0bc6890cd8e976c513fe87dda0da9b5f2ee0
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
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This project concluded and the coreboot implementation is no longer
required.
BUG=b:244596639
BRANCH=firmware-brya-14505.B
TEST=none
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: Ie647dac7ad4879ec1b11baa0a8cb0990af56852f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67299
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update DPTF parameters from internal thermal team.
BUG=b:244373677
BRANCH=firmware-dedede-13606.B
TEST=Build image and verified by thermal team.
Change-Id: I8415e0d25a79764f0c1d11688728b7caa3b3d6a4
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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elog_gsmi_cb_mainboard_log_wake_source is called from SMI and causes
eSPI transactions. If the SMI interrupts an ongoing eSPI transaction
from the OS it will conflict and cause failures. Removing this call to
avoid conflicts. This can be re-enabled after refactoring
google_chromeec_get_mask to use ACPI MMIO.
This is a copy of CB:63280 but for skyrim.
BUG=b:227163985, b:243557044
TEST=suspend/resume skyrim and no longer see EC wake sources in elog.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iac56840fe15101bc556d8cce9960f761c6ea7181
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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Enable DSP setting. Make sure the SSP can work as expected.
BUG=b:243123156
TEST=Dev beep working on Rex.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I6ae28e414ac4ac33f596df57691c979eac5fe132
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67270
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Select SYSTEM_TYPE_LAPTOP so the FADT PM profile is correctly set to
mobile (vs the default of desktop).
TEST=build/boot google/dewatt, run FWTS and verify FADT PM profile correct
Change-Id: I480fbe85782e2c63efa8d2212d503a47d8149ab9
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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As part of investigating b/240690391 I noticed that we were missing
the daughter board ports. Not all SKUs have these ports connected,
but it doesn't hurt to have the extra ACPI nodes.
BUG=none
TEST=build
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id6fc34acbfa30bc15e697043bf93bcf584256128
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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Nvidia recommends saving and restoring the LTR Enable bit in PCIe config
space for the PCIe root port before/after GC6 entry. Also the detectable
error bit should be cleared, as there may be errors expected during the
GC6 flow.
BUG=b:214581763
TEST=no more correctable errors after GC6 entry/exit
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I058ce1b3f17fb6cc59785a85efaf9ea0504cf2ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
|
|
BUG=b:238937091
TEST=Dump SSDT on nereid and check that the wifi device contains the
DmaProperty. Also check that the kernel marks the device as untrusted.
Change-Id: I0725ea18d52420a3161d6fcfa3bcb72ebe35f3a5
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
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Compile-time support of DPTC is controlled by
EC_ENABLE_AMD_DPTC_SUPPORT in each variant's ec.h file. This CL removes
EC_ENABLE_AMD_DPTC_SUPPORT and replaces it with the Kconfig value
SOC_AMD_COMMON_BLOCK_ACPI_DPTC.
Each variant's run-time support of DPTC continues to be controlled by
the variant's overridetree.cb "dptc_enable" value.
BRANCH=none
BUG=b:217911928
TEST=Build zork
TEST=Boot skyrim
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ic101e74bab88e20be0cb5aaf66e4349baa1432e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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Fix EC_IN_RW config for Rex. Dauntless on Rex does not have an EC_IN_RW GPIO pin.
Port of commit 7f339c6050c5 ("mb/google/corsola: Correct EC-is-trusted logic")
BUG=b:243950850
TEST=Built and booted to Google Rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I97e5c752b4f36c9221137903f755837880f6b1c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67208
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
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This reverts commit 47fee08fc3a383e14dc974754d6e463fa320badf.
The required EC changes are now in place to revert this W/A that
disables the LID based shutdown.
BUG=b:243920003
TEST=No shutdown request has triggered while booting AP at
depthcharge.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5ae56912f030f6f0e3cb49282bbffc920fb389c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67206
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
|
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CB:66978 introduced an incorrect condition to check for the presence of
SPD binaries to be injected into APCB_SBR_D5.gen. This caused the SPDs
to be not injected into the APCB and hence the system fails to boot. Fix
it by updating the path of the SPD binaries correctly.
BUG=b:244173966
TEST=Build and boot to OS in Skyrim.
Change-Id: I5efa634fafdcc4769dfad5f533d5512e7c03644f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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Override bluetooth enable_delay_ms to 10ms, per advise from vendor.
BUG=b:233369179
BRANCH=guybrush
TEST=Boot nipperkin, connect to headset, suspend and reboot,
headset still functions.
Change-Id: Ic00de6704018f27339512929f85531aa72205b0e
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67177
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
|
|
Set bluetooth enable_delay_ms to 200ms. 200ms is the lowest common
denominator between the two BT chipsets.
BUG=b:233369179,b:236289478
BRANCH=guybrush
TEST=Connect to headset, suspend and reboot, headset still functions
Change-Id: Id4c23de37351d28d02aaa797fa19ff49e9dfa76c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65180
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
|
|
Added DPTF passive, critical, active policies for Nirwen.
Added additional TSR for Nivviks and updated the PL2 time window
Ref: EDS doc#645550
BUG=b:238713292
TEST= Boot to OS and verify dptf policies are set based on fw_config.
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Change-Id: Iae46736d8d7723a20983dcaad42a7007d76cfad8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
This change adds support to configure the DPTF policies based
on the fw_config THERMAL_SOLUTION.
BUG=b:238713292
TEST=Boot to OS and verify that dptf policies are set based on
fw_config.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I0ffb9d7cc6c963add001a31ba23a6d6c351dd621
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
The current subsystem ID used by the amps may end up getting used
again for future products, therefore this CL updates the subsystem
ID to 103C8C08, which was specifically generated for this amp.
BUG=b:202484541
BRANCH=brya
TEST='FW_NAME=vell emerge-brya coreboot'
Change-Id: I399d8d99ead4fb6fdfa24c2a7a3e3d5e63603b8b
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Update memory and RAMID table
BRANCH=None
BUG=b:243337816
TEST= emerge-coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: Iec3c2098be86661249b1786a02f0768f9d8ad0ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
|
|
To match byra commit 7c2514fc072f95eed6483518811fb6c39f780f5b (mb/google/brya: Change GPP_F17 programming), update A17 pad
configuration to the APIC only.
TEST=Verified booting to OS on Google/Rex.
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Ie9f071dc4a2755dd1f396e2afe730ead66bb1dd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67183
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:238937091
TEST=Dump the SSDT on nivviks and check that the wifi device has the
DmaProperty.
Change-Id: I910b7da7050f9aebfe0eb58552c82b1b29de3772
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
This workaround was added since reading the firmware version on Ti50
versions < 0.0.15 will cause the Ti50 to become unresponsive. No one is
using Ti50 this old anymore, so remove the workaround.
BUG=b:224650720,b:236911319
TEST=Boot to OS on nivviks with Ti50 0.22.4. Check the log contains the
firmware version:
[INFO ] Firmware version: Ti50/D3C1 RO_B:0.0.26/- RW_B:0.22.4/ti50_common:v095c
Change-Id: I3628b799e436a80d0512dabd356c4b2566ed600a
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Add a new board 'Magikarp', and enable SDCARD_INIT for it.
BUG=b:242822419
BRANCH=None
TEST=none
Change-Id: Id7432e33b6fd5f1c25536cf068ff76612575e8ee
Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
|
|
Initialize and calibrate DRAM in romstage.
DRAM full calibration logs:
dram_init: dram init end (result: 0)
DRAM-K: Full calibration passed in 50176 msecs
TEST=Full calibration pass.
BUG=b:233720142
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I31f5693ffe4a1e30defbc8a96dc128de03d6b7e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66278
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch disables LID based shutdown requests.
Google/Rex platform receives a forced shutdown request while
booting to depthcharge due to EC wrongly detecting the LID is being
closed.
For now disable the LID based shutdown behaviour in depthcharge unless
the EC issue gets resolved.
BUG=b:243920003
TEST=Depthcharge no longer sees the force shutdown request now.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I03e33ea4d04dc48331d1cf98c47786b2a184c258
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Add FW_CONFIG probe for new audio sku:
ALC5682I + MAX98357
BUG=b:243474931
TEST=Boot to OS and verify audio devices are set based on
fw_config.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I16af6cf4644c473034e184e95ff2038ca31b20de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67016
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch enables Cnvi BT Audio Offload feature and also
configures the virtual GPIO for CNVi Bluetooth I2S pads.
BUG=b:239670216
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ibc7116e8dc5367fd94d29aba36b91778d0c21e4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Follow the "619907 Alder Lake-S and Raptor Lake-S Platform" and "685472 Intel® Dynamic Tuning Technology (Intel® DTT)" to override tdp pl1 in 15w cpu MSR to 55w and in 28w cpu MSR to 64w.
BUG=b:236294162
TEST=emerge-brask coreboot and check MSR_Package Power Limit-1 in 15w and 28w CPU is correct.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Icb3d7c72b672fbd3e2a9f7ad1f2d1cb2ffc798c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66910
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The define GPIO_PCH_WP needs to be mapped to GPP_H10 based on
the Rex schematics 24/6/2022.
TEST=Built and booted on Google Rex.
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I2489c244bd4cbd9e10ed3db981a6e56a954b5e20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67083
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The define EC_SYNC_IRQ needs to be mapped to A17 based on
the Rex schematics 24/6/2022.
BUG=b:243781237
TEST=Successfully build rex and tested to ensure EC is now functional.
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Ib61ddc9f73dd7b817d3b990bef8f0169f7cafbcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67082
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Because the poweron state of some of the WWAN GPIOs is the
asserted state, this patch fixes the poweron sequence so that the
WWAN module is always correctly powered on, in both cold and warm
reboot scenarios.
BUG=b:233564770
TEST=USE="project_crota emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I4ec8312c30392b9ca0a3e0321cb4578e76ec5787
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Update the DQS for Rex as per the latest Rex schematics (08/25).
BUG=b:243734885
TEST=Built successfully. Confirmed on HW.
Change-Id: I2a458a3da725f953cbba8a194ac6f314f5467419
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67041
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
|
|
This patch configures GPP_E03 (GSC_SOC_INT_ODL) as GPI/APIC in early
GPIO tables.
BUG=b:243641061
TEST=Able to build rex image.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I4aa180c7105be3f356a0bbd5b92b4ced628c34fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67017
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
|
|
Create the morthal variant of the skyrim reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:240970782
BRANCH=None
TEST=util/abuild/abuild -p none -t google/skyrim -x -a
make sure the build includes GOOGLE_MORTHAL
Signed-off-by: Moises <moisesgarcia@google.com>
Change-Id: I25c25f067a040e6930f4fc60fadb8be85dc8eda6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
|
|
Update the build script to check if SPD exists, and only if SPD exists
the APCB_SBR_D5.gen could be executed.
BUG=None
TEST=Build
Change-Id: Ib7b977a89d403242e8bb1f684269e70082125e88
Signed-off-by: Isaac Lee <isaaclee@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66978
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
|
|
Now that the GPU CLKREQ# signal is working correctly, ASPM L1 substates
can be enabled and appear functional.
BUG=b:240390998
TEST=lspci reports them as functional, MODS does not hang
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8297f6bbf7f5a1f7d4ac519bc5b7b3112a74a9a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66811
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Converge as many of the GPU's GPIOs to use PLTRST# as the reset signal
explicitly, as the hardware engineers requested this.
BUG=none
TEST=boot and reboot agah, dGPU still visible on PCIe bus
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I78e58eb17cadc95083571affbecb4e1ce0adf16a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66809
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Support oem_variables and change based on EC notify event.
BUG=b:238921409
TEST=emerge-draco coreboot
1. check ACPI object ODVX has oem_variable[0]=0
Name (ODVX, Package (0x06)
{
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000
}
2. check can get EC oem variable change notify in the kernel log
Change-Id: Ibd856563a43d73a3b1be09b3fbebca1b36b5eab1
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66575
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This comment header is necessary for supporting propagation of overrides
to variants.
Change-Id: Iee92fa4fbc4851c7032401cff99ea49f87717c7f
Signed-off-by: Kevin Chowski <chowski@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Add a new skolas variant, which is a variant of brya's skolas
baseboard.
BUG=b:242869976
BRANCH=firmware-brya-14505.B
TEST=none
Change-Id: I7f9f0389d8b1bf75d8652cbcc9d0c15d3a529802
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Reading Ti50 version is now supported on Ti50 version 0.22.4. Therefore
stop selecting TI50_FIRMWARE_VERSION_NOT_SUPPORTED for corsola.
BUG=b:234533588
TEST=emerge-corsola coreboot
TEST=cbmem -1 | grep 'Firmware version'
BRANCH=none
Change-Id: Id8d849eaf99542363c64e27411549eb6dddfd059
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66905
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Pronin <apronin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
1. Moved CHROMEEC_* to common (required for all boards)
2. added missing EC_GOOGLE_CHROMEEC_SKUID
TEST=Verified with simics on RVP
Change-Id: I26a01e5d1c78d4cd83b1aa53e68b2c3059da6061
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66762
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable DPTF oem_variables and override based on CPU match id.
BUG=b:236294162
TEST=emerge-brask coreboot and check the value in odvp0 is correct.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ic935ec42f4de0cbec996da37b44f354978fe4b62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66907
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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bypass power
Add FW_CONFIG probe to separate ext fivr settings for Pujjoteen
and others(Pujjo and Pujjoflex)
BUG=b:242663554
TEST=Boot to OS and verify that ext_fivr_settings are set based on
fw_config.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I6bb6d1701c55459cf331dd2f3ffe07f91bca2fa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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The current reset delay is not enough to make touchscreen IC ready,
ILITEK feedback their requiremt is 400ms in spec T2.
After changing the reset_delay_ms and check touchscreen works,
ILITE also change the IRO to low level trigger.
This CL is to reflect that.
BUG=b:235929123
BRANCH=firmware-dedede-13606.B
TEST=check touchscreen function work
Change-Id: I126b2d74c1d7a1799e2f67a8ab01cba074447c06
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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Configure GPIOs according to schematics.
BUG=b:242277219
TEST=emerge-nissa coreboot
Change-Id: Id7412059ba98d58f7014ab7201ea8958ede5905e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Update Devicetree according to yaviks's design.
BUG=b:242277219
TEST=emerge-nissa coreboot
Change-Id: I5d91cccbb44787bcbe7258a817ff97b6dce86c2e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Add ELAN touch support
BUG=b:243120074
TEST=emerge coreboot and check ELAN touch screen is workable
Change-Id: If30232b3da9af0015d6d87535b53f905c5a30bcb
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66912
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Isaac Lee <isaaclee@google.com>
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DPTF Policy and temperature sensor values from thermal team.
BUG=b:242797681
TEST=build FW and boot to OS.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Id4365f87843a4408ae457e7ef27291fdaa0d5bde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66827
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change is to skip sending the MBP HOB since coreboot doesn't
use it and also helps to reduce the boot time by ~40msec on ADL-N
variants.
Boot time data:
Before:
* 955:returning from FspSiliconInit 1,231,364 (117,051)
After:
* 955:returning from FspSiliconInit 1,198,221 (79,497)
BUG=b:241850107
TEST=Verified that boot time is reduced by ~40msec and also S0i3
is working.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Iaeaa8bcdf8467fdd467a10a98dd7582e8e0b067c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The infrastructure for selecting an appropriate firmware image to use
the right descriptor is now ready so runtime descriptor updates are no
longer necessary. Since the different descriptor builds split along
HDMI/USB-C lines for nereid, a single VBT file can be used for each,
removing the need for runtime VBT selection as well.
BUG=b:229022567
TEST=Nereid type-C and HDMI outputs work as expected
Signed-off-by: Sam McNally <sammc@chromium.org>
Change-Id: Idf1fbd6c26203adbda002dec3f11e54a7b9f9b82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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This reverts commit feb551a92550fcc28b32aca77117aa743018b233.
Adding new variant "pazquel360" is not needed.
BUG=b:239599467
TEST=emerge-trogdor coreboot
Signed-off-by: chaogui@google.com
BRANCH=none
Change-Id: I4878d3a54f96fb9d38f2da1a1c918dfdef80a301
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66805
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DPTF Policy and temperature sensor values update from thermal team.
BUG=b:237640264
TEST=USE="project_crota emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: I45b4f80cbec0723c63ac7fc7176e13ae5a2b54c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66365
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds support for turning the PCIe SRCCLK# on and off during
RTD3 (just like the soc/intel/common/block/pcie/rtd3 driver).
TEST=GC6 and GCOFF sequences still work
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4b369cfcc7245a1c212fa65f65fdab542f60e196
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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For board revs 3 and later, the PG pin for the NVVDD VR moved from
GPP_E16 to GPP_E3. To accommodate this, the DSDT contains a Name that
this code will write the correct GPIO # to depending on the board rev,
and we'll use that instead.
BUG=b:239721380
TEST=still works on board rev 2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I11aec6069da8e086789419303871c6d0f5fb29af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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Modify GPP_D17 setting for SD_WAKE_N.
BUG=b:242647845
TEST=Build and boot on pujjo
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Iacd89d27174869e34c48d1f62793ddc45b43f3f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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This patch provides a mitigation path for having different size SPINOR
parts across Rex board revisions. Rex Proto 0 only has 64MB SPINOR
mounted on the board, and the plan is to use 32MB later with Proto 1
onwards.
Hence, the idea here is to maintain a 32MB SPI Flash layout across all
Rex board revisions, but the Proto 0 build only selects
BOARD_ROMSIZE_KB_65536 config for adding padding at the end of the
32MB range.
BUG=b:242825380
TEST=Able to create 64MB AP Firmware for Rex with below layout:
SI_ALL: 0-9MB
SI_BIOS: 9MB-32MB
Padding/Unused: 32MB-64MB
Additionally, able to hit CPU reset on MTLRVP (has 64MB SPINOR) with
Rex AP Firmware binary.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibcc2206456639ef4ff22e0c4069521e583be58cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66828
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Currently, to enable/disable LTE based on fw_config on nissa, we have
two sets of GPIOs: lte_enable_pads and lte_disable_pads. This was to
prevent the SAR interrupt pin GPP_H19 from floating for the short period
of time between enabling it in gpio.c and disabling it in fw_config.c
(see CB:64270 for more details).
With the new pad-based GPIO overrides (CB:64712), this is no longer an
issue since the gpio.c and fw_config.c overrides are applied at the same
time. So simplify the LTE GPIO configuration by enabling all the LTE
pins in the variant gpio.c, then disabling them in fw_config.c if
needed.
BUG=b:231690996
TEST=LTE still works on nivviks
Change-Id: I5bf20a027414ea5e7c1f198d69e355c76f467244
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66776
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the SoC that was upstreamed as Sabrina was finally renamed to
Mendocino, also adjust the abbreviation used for the DXIO/DDI descriptor
struct array names.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I14ecf98e4a94376a70e783774c8f7b8701581220
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66815
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 0 (0000)
H58G56AK6BX069 2 (0010)
K3LKBKB0BM-MGCP 2 (0010)
BUG=b:242277219
BRANCH=None
TEST=run part_id_gen to generate SPD id
Change-Id: I46c168482113beb7cd28f387ed495847aba8602f
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Create the yaviks variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:242277219
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_YAVIKS
Change-Id: Id60fe0e54a8e0196a302141f58c6695779ac251a
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Add GPIO configuration and device tree to enable the chip.
BUG=b:240607130
BRANCH=firmware-brya-14505.B
TEST=Patch linux with NXP's pending drivers
UWB device is probed and can respond to a simple hello packet
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I83be712d243c365a5cbfe6f69a6bd85440c5bec7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to 8
- Set FastPkgCRampDisable VCCIA and VCCGT to 1
- Set pre-wake randomization time (DPA) to 100
BUG=b:241349500
TEST=build FW and checked fsp log.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Id4a1540de8c3ee74695631acc8181dcc446fe137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66783
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add FW_CONFIG probe based on pujjoteen boxster of below devices:
LTE, SD card, stylus, WFC camera, AUDIO
BUG=b:236158122
TEST=Boot to OS and verify that above devices are set based on
fw_cofnig.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I49fc5461e7affba68a6b89bf166c84598fbfa088
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66741
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Ghost has two amps and address are 0x3c and 0x3d.
BUG=b:231581723
BRANCH=firmware-brya-14505.B
TEST=max98396 driver can get the DSD property correctly.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I3b6a331ca42e97f984f3a585726c02452bb067f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This reverts commit f87489bbae5bb1ae3b17b6a03af9e309769b1f72.
Reason for revert: Broadwell actually supports early flash writes.
Change-Id: I342aefe464c72a32b41a40062b62d871caa0707b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The I2C config was unnecessarily placed in the overridetree. As we
prepare for fanout, this is going to cause unnecessary noisy changes.
Move the I2C config to the devicetree to avoid this.
BUG=None
TEST=Build
Change-Id: I09ad5c911a0fd00274761cb71e9b659b47cd6da1
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66802
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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EN_PP3300_EMMC will change to GPP_A21 to meet DP++ function and it based on Moli GPIO Table_20220803.xlsx. But it will let current eMMC skus can't boot into OS, so use the board_ver to decide which gpio table return and set override_gpio_table_id2 and early_gpio_table_id2 based on Moli GPIO Table_20220803.xlsx
1. set GPP_A21 to EN_PP3300_EMMC
2. set GPP_A22 to NC
3. set GPP_E20 to DDIC_DP_CTRCLK
4. set GPP_E21 to DDIC_DP_CTRLDATA
BUG=b:241370405
TEST=emerge-brask coreboot
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I0a2c8684d140738f43658cd6075ed083eee44e65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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Create the winterhold variant of the skyrim reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:240970782
BRANCH=None
TEST=util/abuild/abuild -p none -t google/skyrim -x -a
make sure the build includes GOOGLE_WINTERHOLD
Signed-off-by: Isaac Lee <isaaclee@google.com>
Change-Id: I0e16f0a674aa3f4687cd82d5840a3c2087148a51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66620
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit I73b7ddec50936f7836f915f459ca0bdc0777cb22.
Revert change to disable post codes. Post codes were initially disabled
because of an issue with initialization within the SMU.
BUG=b:227201571
TEST=Build and boot to OS in Skyrim.
Change-Id: I2a2bd2252a103c682b5d4ad5ecd1da42b3744083
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66092
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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By moving the large wait for FBVDD discharge from PGOF
to PGON, the whole time may be avoided if enough time has
elapsed between the successive calls.
BUG=b:239719056
TEST=With Nvidia test software, verify ACPI prints
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I891aa14f120d58c45b8965038a9d2f2a417b3f3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Now that the virtual wire situation is figured out, the GC6 sequence
is updated to match the latest HW design guide from Nvidia. This
allows Nvidia test software to (mostly) successfully execute the GC6
test, but with some PCIe AER errors.
BUG=b:214581763
TEST=tested with Nvidia test software
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia094c4fa9b4db094a59b9b6f02be1a649ee8569b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Since the VW GPIOs are not in the baseboard GPIO table, they do
not actually override anything, and hence do not actually get
programmed. This patch moves the programming from the ramstage
table to the bootblock table so they get programmed.
BUG=b:214581763
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I42db44d38df20dd2695921e2f252be163f6b17f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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It is highly unlikely that the "OEM revision" of the DSDT is 0x20110725
on mainboards with a chipset not yet released on 2011-07-25. Since this
comment is most likely to have been copy-pasted from other boards, drop
it from boards which use a chipset newer than Sandy/Ivy Bridge.
Change-Id: If2f61d09082806b461878a76b286204ae56bf0eb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
|
