| Age | Commit message (Collapse) | Author |
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Enable separate MRC cache for recovery mode. This requires change in
flash layout to accomodate another region for RECOVERY_MRC_CACHE.
BUG=b:69473883
TEST=Verified following scenarios:
1. Boot into recovery does not destroy normal mode MRC cache.
2. Once recovery MRC cache is populated, all future boots in recovery
mode re-use data from the cache.
3. Forcing recovery mode to retrain memory causes normal mode to retrain
memory as well.
Change-Id: Icdfac3698507d89d98a51cfc3d756a56d2a2d648
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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There is merit in having new boards use the pinouts and controls
in scarlet. This adds a config so new scarlet-derived boards can
easily use scarlet structure without going through every file
and adding new logic.
TEST=Run "emerge-scarlet coreboot"
Signed-off-by: egemih@chromium.org
Change-Id: I5808f93f4563033ce93050e1eedb6eac2b52c3b3
Reviewed-on: https://review.coreboot.org/22517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Remove ugly camel case in the soc/amd/common and Stoney Ridge
SPD files and functions. Update the related mainboards.
Also, remove a unreferenced function prototype, smbus_readSpd().
Change-Id: I51045b6621f0708d61a570acbdcb4e6522baa1ea
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The mainboard directory is included through the PI makefile - most
mainboard directories aren't in the include path at all. Move the
ec.h file into the baseboard/variant directory that is already in
the include path.
BUG=b:69220826
TEST=Build
Change-Id: I89d361b700c66ba576de724927574fdab9461fc6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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All AGESA headers should be included only through agesawrapper.h
I missed this file in the Kahlee cleanup.
BUG=b:66818758
TEST=Build gardenia; Build & boot kahlee
Change-Id: Id9b303cb3cee8088fb5cca5257566c033d28c692
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This fixes some issues with the initial implementation that was copied
from reef.
- The board ID value shouldn't be size_t - it's not a size.
- Kahlee doesn't even need the memory.c file - it uses an SoDIMM.
BUG=b:68293392
TEST=build stoney platforms, boot kahleebo
Change-Id: Ife5660d36912e887edfd0365a9f16c5a172c9c86
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22515
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It's sometimes hard to find the code name of a Chromebook. Add the
marketing names to Kconfig, since they are easily available.
Information (mostly) taken from:
https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices
Unknown boards (unreleased, etc.):
* Fizz
* Foster
* Nasher, Coral
* Purin
* Rotor
* Rowan
* Scarlet, Nefario
* Soraka
* Urara
* Veyron_Rialto
Baseboards:
* Glados
* Gru
* Jecht
* Kahlee
* Nyan
* Oak
* Poppy
* Rambi
* Zoombini
White label boards:
* Enguarde
* Heli
* Relm, Wizpig
TODO: How does this interact with the board_status code?
Change-Id: I20a36e23bd3eea8c526a0b3b53cd676cebf9cd86
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Connect the EC thermal to Kahlee and Grunt thermal ASL. Intialize GNVS
thermal values in the mainboard finalize.
BUG=b:67999819
Change-Id: I89159a5fd3c639e511139b8c5948b6a4ee19aaa3
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Set the EC SCI reporting mask to include the power plug reporting.
BUG=b:65637324
TEST=Check power_supply_info on AC/DC.
Change-Id: I58814fc495081ffe8e47162da0fa4fbeba49d67b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Code within carrizo_fch should be SOC specific instead of board specific.
BUG=b:64034810
Change-Id: I5de2020411794bfcd3730789f62af9c9834a018b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22455
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a property for DSP calibration clock name and rate such that
RT5514 codec driver can control ssp1_mclk for DSP clock calibration.
BUG=b:67763576
TEST=boot on eve check RT5514 codec driver can get this device
property.
Change-Id: Icf9695ef67efb2bb073e39b2ece02d57f0460a0c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Original-Change-Id: Ie204dda81a099f23beb20be71380a8494a9bee31
Original-Reviewed-on: https://chromium-review.googlesource.com/756261
Original-Reviewed-by: Dylan Reid <dgreid@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/22451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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To enable faster download of hotword data set the SPI clock to the
Realtek 5514 DSP chip to 12MHz instead of the default 1MHz.
BUG=b:67763576, b:66161281
TEST=cras_test_client --listen /tmp/rec.raw, trigger hotword, and check
the samples using hexdump or cras_test_client --playback_f /tmp/rec.raw
Change-Id: I92710eae25613a8202c63888b86a269803c40fe6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Original-Change-Id: I7e50d755a90d739b6dec155228351c3974b2f3b9
Original-Reviewed-on: https://chromium-review.googlesource.com/686675
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Chinyue Chen <chinyue@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: Chinyue Chen <chinyue@chromium.org>
Original-Commit-Queue: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/22450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This feature was enabled at the kernel level, but that is triggering an
issue where FSP expects it to be disabled so it forces a cold reboot on
every warm reboot. Since we want this enabled anyway just set it this
way in the BIOS so it matches what the kernel expects.
BUG=b:68666100
TEST=pass firmware_FWtries on Eve with R63 OS image
Change-Id: I294e34d25406365d591da06ce4c931b710cfbbaa
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: I964d3d30392d130e808f37a661f2c89ec926cf58
Original-Signed-off-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/749733
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Tune PCH I2C4 hold times to ensure the frequency is always <400KHz.
BUG=b:67029862
TEST=boot on eve and measure I2C4 at Tp262 to be 385KHz
Change-Id: Ie93c5c40bc74069b285f6c3ee311f1bd7cefcaf1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: Iceabc806a17b9e6a144a4f6288c6cca790d03950
Original-Signed-off-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/739841
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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AER and LTR must be enabled individually on ports that need it,
in this case it should be enabled for WiFi and NVMe.
BUG=b:65457528
TEST=Wifi team verified that the performance is better with these changes.
Change-Id: I0d688fe07a1f3117c1ca617c2ce78e0d024a3510
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: Ib059517fa782ccc18ba5ef1f76058a1898b7bf7a
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/671211
Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Commit-Queue: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/22447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Use the rt5663 driver and provide values for the offsets which are
needed for providing manual values to compensate the DC offset for
L and R channels between headphone and headset.
BUG=b:62712227
TEST=build and boot on eve and ensure rt5663 is functional.
Change-Id: I88113616e4b7c79cff840168b7c54ae754dfa75f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: Ica4090636c1ff29f0298114e62c9cc6fe167a425
Original-Signed-off-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/611606
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Hsinyu Chao <hychao@chromium.org>
Reviewed-on: https://review.coreboot.org/22446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change the touchscreen power control back to coreboot instead of
under the ACPI _ON/_OFF methods, and switch the TOUCHSCREEN_STOP_L
pin back to an output.
This reverts previous changes to touchscreen GPIOs that were made
to get back to a known good/working state. Having ACPI control these
pins was resulting in a small percentage of touchscreen not being
discovered at boot. This platform is not intending to use S0ix so
the ACPI control is not needed.
BUG=b:63718744
TEST=manual testing on Eve devices.
Change-Id: I3fd64a435a053da1558ef736fe7baceee3c8f3a0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: Ia1e2ae7ca2a8b668c60fbda2aa50373e580646b2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/572692
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Commit-Queue: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/22445
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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All Stoney AGESA headers should be included only through agesawrapper.h
BUG=b:66818758
TEST=Build and boot tested
Change-Id: I642f5caf8a37ae4042c32fec3a92e0995193cb7a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Instead of getting the address of the GPIO function with an extern,
add a getter function and make the GPIO arrays static.
TEST=Build Grunt; Build & boot Kahlee
BUG=b:69164070
Change-Id: I3defcb66696459b915d7d4f43234d5c08ab7d417
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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mainboard.h only had a single function definition. Move it into
baseboard/variants.h and get rid of the file.
TEST=Build grunt/kahlee
BUG=b:69164070
Change-Id: I6b7d50d5c949733d77c42b4daf56ed1f97ed6954
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Update common files and add files for grunt to the variant directory.
BUG=b:68293392
TEST=Build only
Change-Id: I7b80e470058872d6613e66e64c8dd1494942e9b9
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=b:68293392
TEST=Build only
Change-Id: Ie4d039b4da10a992fc9dd2b0221fd4a1644aae6a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Several SPD hex files for chell were missing from upstream coreboot
(as compared to the Chromium tree/branch), which resulted in the
incorrect type and amount of RAM being reported on chell boards
with > 4GB RAM. Add these missing files and their Makefile entries.
TEST: boot google/chell m7/16GB config and observe correct RAM
type and amount reported via dmidecode and cbmem console log.
Change-Id: I37d708c96e754b438e40fc413420aa64bf234c29
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22402
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set the UMA memory size to 128 MiB. This value was empirically tested
by AMD as the lowest value one could use.
BUG=b:64927639
TEST=default, and 64, 128, 256, 384MB non-legacy configurations.
Change-Id: I2bc808d8b402c3eb16a1a5962f3fa9d6b224cf52
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21335
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max
supported for the device. AGESA's DRAM procedures follow the BKDG and
may vary depending on the number of slots on the motherboard. DIMM
numbering and ordering is also affected by this value.
Replace hardcoded integers with defined values for DIMM slots and
number of channels.
Change-Id: I4f7336da80b4e3d7f351502a63de0652e9ff5395
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21853
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Kahlee needs to keep its DRAM contents after a reset. Move this
override out of the OemCustomize.c file to a devicetree register
setting.
Change-Id: I3196cb8b94bec64e8ce59e4285cf8d97f442bd3d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21858
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On Astronaunt, after the system enters the S5 power state, there is a
10-second timeout before the system transitions the power state from S5
to G3. The EN_PP3300_DX_LTE_SOC signal, which is controlled by GPIO_78
on the APL platform, remains on during that period. If the system is
powered back on before going to G3, the built-in modem won't go through
a power cycle as EN_PP3300_DX_LTE_SOC is never de-asserted.
Keeping the modem, and indirectly the SIM, powered during a quick system
power cycle may sometimes be undesirable. For instance, we would like a
SIM with PIN lock enabled to require unlocking each time the system is
powered on. After the SIM receives a PIN, it may remain unlocked until
its next power cycle.
Also, it is often desirable to power cycle the modem when the system
goes through a power cycle. For instance, a user may power cycle the
system to recover a wedged modem.
BUG=b:68365029
TEST=Tested the following on an Astronaunt device:
1. Verify that the modem is powered on after the system boots from cold.
2. Suspend the system to S0ix. Verify that the modem remains powered on
when the system is in S0ix. After the system goes back to S0, verify
that the SIM with PIN lock enabled doesn't request unlocking, and the
modem can quickly reconnect to a network.
3. Configure the system to suspend to S3 instead of S0ix, and then
repeat (2).
4. Perform a quick system power cycle, verify that the modem is powered
cycle and the SIM with PIN lock enabled requests unlocking.
Change-Id: Ie60776d5d9ebc6a69aa9e360bd882f455265dfa2
Signed-off-by: Ben Chan <benchan@chromium.org>
Reviewed-on: https://review.coreboot.org/22415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Add dptf.asl (copied from reef) to baseboard variant includes,
instruct zoombini variant to use the baseboard's dptf.asl,
instruct zoombini variant to use the baseboard's gpio.h.
BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x
-a" compiles successfully.
Change-Id: I9aa37f5afc35dab372917a4c84ff3121ec569546
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/22381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change EC_SCI_GPI to GPE0_ESPI.
BUG=b:69011806
BRANCH=master
TEST=none
Change-Id: I5d07bc0ef295d776635ff3a585c8de9028bd3f6a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/22380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Poppy and variants won't be using deep S3. This change disables deep
S3 option in devicetree.
BUG=b:69053636
Change-Id: I5fb4a6a0e4216a3648b5ed888f6dc6618f1a9fc4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22378
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch enables customized NIC leds as follows:
Green Orange (Amber)
100M off blinking
1000M on blinking
BUG=b:65437780, b:68284778
TEST=Make sure the registers are programmed as expected and observe the
LEDs are behaving as expected. Perform suspend/resume test and the
LEDs are still working as expected.
Change-Id: I9bb1367a4c742c2755d620e14ee6dfe70ee7f34b
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This compares to the acpi directory in other variants.
BUG=b:68293392
TEST=Build and boot kahlee
Change-Id: I05d402995b280d6f020bc2575063dbffefa30670
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Even though this GPIO isn't used for Kahlee, it needs to be defined
so that the weak version of the variant_board_id() function can
compile.
BUG=b:68293392
TEST=Build and boot kahlee
Change-Id: Ia8daf70fbafe02ec37c6b5eb8421cdb11de3be8b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Now that recovery button has been enabled through cr50,
we can add VBOOT_PHYSICAL_REC_SWITCH config and treat
the recovery button like on any other chromebox.
BUG=b:37751915, b:63893483
BRANCH=None
TEST=With DUT in normal mode, boot into recovery, press ctrl+d
followed by pressing the recovery button. Should successfully
boot into dev mode.
CQ-DEPEND=CL:737477
Change-Id: I72fb42508083295e317dd06900796dc0cda753f6
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22368
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Enable Dialog DA7219 codec i2c device and add required SSDT parameters
BUG=b:68686020
TEST=With req'd driver support in kernel v4.4 verify audio on headset
Change-Id: Ic815c929f29bec0d26a2981e9933b752c2d84c70
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Signed-off-by: Shruthi Sudhakar <shruthi.sudhakar@intel.com>
Reviewed-on: https://review.coreboot.org/22264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Nautilus board uses Dialog da7219 headset codec,
Select the appropriate NHLT blob to be packaged in CBFS.
Also generate the required ACPI NHLT table for codec
and the supported topology in nautilus.
Removes unwanted DMIC blob pick for nautilus
BUG=b:68686020
TEST=With the required driver support in kernel verify that
the Audio plays on headset and recording on headset mic
Change-Id: I104889f54da1de38854bcb72aabbc88b739d6c09
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/22325
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:68865273
Change-Id: Ia2e9b10035e9dd502a563cdf8324ea8ea1922db3
Signed-off-by: Lann Martin <lannm@chromium.org>
Reviewed-on: https://review.coreboot.org/22359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
On older Grus, GPIO0_A2 was an audio voltage rail enable line. On
Scarlet, we instead moved the audio codec enable (previously on
GPIO1_A2) there. Unfortunately the code still had some hardcoded
leftovers that were overlooked in the initial port and make our speakers
smell weird.
This patch fixes the incorrect GPIO settings and adds the speaker enable
pin to the GPIOs passed through the coreboot table, so that depthcharge
doesn't have to keep its own definition of the pin which may go out of
sync.
Change-Id: I1ac70ee47ebf04b8b92ff17a46cbf5d839421a61
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Current VBT setting for T8 is only 1ms which is under Innolux
N116BCA-EA1 panel's spec.
Modify T8 to 100ms.
(Innolux's panel's spec requires T8 needs to be greater than 80ms)
CQ-DEPEND=CL:*496012
BUG=b:67756548
BRANCH=master
TEST=emerge-coral depthcharge coreboot chromeos-bootimage
Run on DUT and check panel sequence meets spec.
Change-Id: I580567decfccd78366c37181255015ac2cd76493
Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Reviewed-on: https://review.coreboot.org/22306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
From what I can tell FILECODE isn't used at all in this file.
Remove it.
Change-Id: Ie88140e63a4917f470f42119c1fe4e8c7d2584ca
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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In skylake based platforms, setting GPIO pad reset config
to DEEP will reset the gpio configuration across warm reset,
set it to RSMRST to preserve the configuration across warm resets.
Also, moving the configuration from early to late as appropriate.
BUG=b:64386481
BRANCH=none
TEST= WiFi functionality across S3, DeepS3, S0ix and warm/cold reboot.
Change-Id: I38940b7c7d71e60bf0e51d6978a00be148ad61bc
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Adapted from Chromium commit 12ad5b5: Reks : override USB2 Phy settings...
Base on Intel recommendation, override following
settings for USB2 port 1/2/3 on BSW D-stepping SOC.
1. Set USB[1] register for right side to 7321
2. Set USB[2] register for left side to 7021
3. Set USB[3] register for CCD to 7021
Original-Change-Id: I04240a010e875f29c47f4fea83ff918f180b0273
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Change-Id: Iabd6312576e9897315c4e4dbf19341380d9d1414
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Adapted from Chromium commit 6ee6f3d: Reks: To set the RX ODT limit...
Override RX ODT and DRAM geometry for Micron part MT52L256M32D1PF-107.
Use get_ramid() to determine if override is necessary.
Original-Change-Id: I41f3aba030a00152e1217533ef953338ac396605
Original-Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Original-Reviewed-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Change-Id: Iea8c3c67e5afb21285dc15ad665474ad5f192423
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
ASL+ Optimizing Compiler/Disassembler version 20170831 shows the remark
below.
```
dsdt.aml 87: Method (_CRS, 0x0, NotSerialized)
Remark 2120 - ^ Control Method should be made Serialized \
(due to creation of named objects within)
```
So, serialize the method.
Fixes: commit 4a51ea8470 (google/kahlee: Add ASL for Elan touchpad)
Change-Id: I664f493318cbfd80d91565c0d29ec918278c4906
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Move files that are particularly specific to the mainboard into the
variant directory. Files that only have small areas of mainboard
specific pieces use #if to separate between the boards.
Add memory.c to split out the variant board id into a weak function.
Add baseboard/gpio.h to satisfy the build - this will be updated in the
next commit.
BUG=b:68293392
Change-Id: I7c1beb45f571f2547f3b5b0d7ec78923d0cec761
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
add elan touchpad in devicetree.
BRANCH=master
BUG=b:66462881
TEST=emerge-nautilus coreboot
Change-Id: I30e6797ef06351690ff0b5c78ea76918547167a7
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: shkim <sh_.kim@samsung.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Update GPIO settings to meet nautilus's schematic design.
BRANCH=master
BUG=b:66462881
TEST=emerge-nautilus coreboot
Change-Id: I11930df62130431764702371a3ba84949a65ba30
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: shkim <sh_.kim@samsung.com>
|
|
update with nautilus memory spds.
RAM_ID = 0 => K4E8E324EB-EGCF
RAM_ID = 1 => K4E6E304EB-EGCF
RAM_ID = 2 => K4EBE304EB-EGCG
BRANCH=master
BUG=b:66462881
TEST=emerge-nautilus coreboot
Change-Id: I29d8a76b170aee64bb0125276df0e4709012daba
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: shkim <sh_.kim@samsung.com>
|
|
Current VBT setting for T8 is only 1ms which is under Innolux N116BCA-EA1
panel's spec.
Modify T8 to 100ms.
(Innolux's panel's spec requires T8 needs to be greater than 80ms)
BUG=b:67756548
BRANCH=master
TEST=emerge-coral depthcharge coreboot chromeos-bootimage
Run on DUT and check panel sequence meets spec.
CQ-DEPEND=CL:*493633
Change-Id: I7934b0f6d40b15796c55d360995c5eb0c5049222
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/22294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This is to enable SPD word access to reduce boot time. It can save
80 ~ 100 ms per DIMM.
BUG=b:67021853
BRANCH=None
TEST=system boot, and boot time is reduced
Change-Id: Ic527a539ed634e15b939b18fff4b4e08ebb3ec57
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
For Raydium, export reset GPIO as well as PowerResource.
Let EN_PP3300_TOUCHSCREEN signal will goes to low at S3 mode.
BUG=b:67879912
BRANCH=coral
TEST=emerge-coral coreboot
Change-Id: Ibf501b40ecfc957fd8be7ebffd2357dfa0e07757
Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com>
Reviewed-on: https://review.coreboot.org/22252
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
For MELFAS/Raydium, export reset GPIO as well as PowerResource
BUG=b:68141940
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I1915ff8207502b80ecba6b63ce2ce1b866faf4c4
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/22146
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
There's no need to have these separated.
BUG=b:64932381
Test=Build & Boot
Change-Id: I22898d3bf95d5e9a8fc2643bfccae1e2f5b29e44
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
In order to pass type C USB2 eye diagram for sku Astronaut,
USB2 port#1 PHY register needs to be overridden.
sku ID:0,1 Astronaut (USB)
port#1:
PERPORTPETXISET = 7
PERPORTTXISET = 2
sku ID:61,62 Astronaut (LTE)
port#1:
PERPORTPETXISET = 7
PERPORTTXISET = 5
BUG=b:68120012
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage
Change-Id: Icf5c9e5f4dae15630ec4d6ca6648cae78ca910c6
Signed-off-by: Ren Kuo <ren.kuo@quantatw.com>
Reviewed-on: https://review.coreboot.org/22135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This commit just moves the vboot sources into
the security directory and fixes kconfig/makefile paths.
Fix vboot2 headers
Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Add the missing device and ensure it shows up in the devicetree prior
to PCI enumeration.
Change-Id: Ia2c4ba1200422b36c533e86065a4fcd10c4b2722
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22055
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Beside the high-resolution eDP panel, it features a dual-mode
mini-DP port.
Change-Id: Iae60c1f930f5778ee3b5d9d19227168257e9ae06
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Add GPE configuration table.
Remove GPE3 from the power button ASL and set the EC to GPE3(AGPIO22).
Set the EC and PCIE/WLAN SCI GPIO signals.
Set GPE ASL methods for:
PCIE/WLAN 8h
EHCI 18h
XHCI 1fh
Note EC GPE3 methods are in the EC ASL.
BUG=b:63268311
BRANCH=none
TEST=Test lidswitch powers the device on and off at the login screen.
Change-Id: I27c880ee84b6797d999d4d5951602b654ede948e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22096
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Set PL2 based on either 90% of usb c charger's max power or sku id if
using a barrel jack.
BUG=b:37473486
BRANCH=None
TEST=output debug info for different skus and make sure
PL2 set correctly.
Change-Id: I487fce4a5d0825a26488e71dee02400dbebbffb3
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/21772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Stoney Ridge has one EHCI controller and one XHCI controller.
Also, update the Kahlee and Gardenia mainboards ASL to match.
Change-Id: I5749ca0640796732e74e551147f8c4446317b77e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
In the original AGESA headers, these tables are not defined as const.
Cast them to void * so that they'll work with either version of the
headers.
BUG=b:64766233
TEST=Build in cros tree and upstream coreboot, with old headers
and updated headers.
Change-Id: I75387b57caf5a3c6c25655120aafd942254b5c73
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22059
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There was no reason to have the AGESA callout tables in each mainboard,
so move them to soc/amd/common.
Move chip specific functions into the stoneyridge directory:
- agesa_fch_initreset
- agesa_fch_initenv
- agesa_ReadSpd
Combine agesa_ReadSpd and agesa_ReadSpd_from_cbfs, and figure out which
to use.
Soldered-down memory still needs to be supported in a future commit, as
stoney supports both DDR3 & DDR4. A bug has been filed for support for
the upcoming Grunt platform.
BUG=b:67209686
TEST=Build and boot on Kahlee
Change-Id: Ife9bd90be9eb0ce0a7ce41d75cfef979b11e640b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
This change adds support for logging EC events during S0ix resume.
BUG=b:67874513
TEST=Verified that EC events are correctly logged during S0ix resume:
284 | 2017-10-16 20:45:12 | S0ix Enter
285 | 2017-10-16 20:45:16 | S0ix Exit
286 | 2017-10-16 20:45:16 | Wake Source | Power Button | 0
287 | 2017-10-16 20:45:16 | EC Event | Power Button
288 | 2017-10-16 20:45:35 | S0ix Enter
289 | 2017-10-16 20:45:40 | S0ix Exit
290 | 2017-10-16 20:45:40 | Wake Source | GPIO | 112
291 | 2017-10-16 20:45:40 | EC Event | Lid Open
292 | 2017-10-16 20:50:51 | S0ix Enter
293 | 2017-10-16 20:50:59 | S0ix Exit
294 | 2017-10-16 20:50:59 | Wake Source | GPIO | 112
295 | 2017-10-16 20:50:59 | EC Event | Mode change
Change-Id: I9f6dcb8852d94ebf90bb5b63a17fde524d58d49f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
14" BigDaddy needs to override USB2 TxiSet additionally to
enhance driving strength.
Otherwise EA test will fail on USB2 eye pattern.
BUG=b:67820719
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I674c121a71866a5d44439eeb49e07f917d816de8
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/22037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch skips SPD data reading when system resumes from S3 since
MRC cahce is adopted and validated in fsp_memory_init.
BUG=b:67021596
TEST=Run suspend/resume on Fizz and make sure the systems are
working well when system resumes from S3. Checked dmidecode
information and SMBIOS type 17 data is the same with cold
boot.
Change-Id: I1692fca8456290d1471973b746537b5fec504e03
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
BUG=b:65386429
BRANCH=none
TEST=panel lights up
Change-Id: I9871969314b9b64bee2b20332e35bfc6fbd2ddda
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Remove IRQ and MP tables. Modern OS use ACPI instead of legacy tables.
Use Kconfig for reversable configuration if using old OS.
BUG=b:62241143
Change-Id: I5fc833c8af47b5f6fad757e129250e6202810dbb
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Enable PCIe Advanced Error Reporting for PCIe
root port 2, 3, 4 ,8.
BUG=b:64798078
TEST="lspci" shows that AER is enabled in the capabilities list.
Change-Id: I6438250d674e7d06cdecd8f25fadebca1973721e
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/21946
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
For Kahlee, the AMD firmware directory should be in the 1MB location
so that it's in the RO cbfs section.
BUG=b:65484600
TEST=Build & boot
Change-Id: I650d8bc0bfa773f5fb5dc11167fe3db3b9550b68
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22003
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Notify the EC the system is going to sleep.
Change-Id: I025e268a4f806d827348d91effff43a6a339a148
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Forward the apmc call to the chromeec.
Change-Id: Id724c1abf15617ad1ba28f2c0247455b014c1867
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add support for google/wizpig (white label Chromebook) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new wizpig variant
- Add new shared SPD file to the baseboard
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: I424d2256eb79ca3ea0a62620954c57c09ae0c0b2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add support for google/ultima (Lenovo Yoga 11e G3) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new ultima variant
Sourced from Chromium branch firmware-ultima-7287.131.B,
commit 3ef9e73: Revert "Revert "soc/intel/braswell: Put SERIRQ in quiet mode""
Change-Id: Ib38b110f50f4d6ae6eda40e787cd3c1c8dd5ece7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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Add support for google/setzer (HP Chromebook 11 G5) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new setzer variant
- Add new I2C touchscreen device and SPD files to the baseboard
for potential reuse by other variants
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: Ibcebebeb469c4bd6139b8ce83a1ca5ca560c2252
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Support the required AGESA_DO_RESET in bootblock.
BUG=b:64719937
BRANCH=none
TEST=Check AGESA reset request in booblock does a reset in the serial
console or ec console.
Change-Id: I462a1f81b8d209c15417946a314f2bfb9b226e4d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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We are changing the bootstraps in the EVTs so that the SOC
communicates with cr50 over SPI instead of cr50. SPI is more reliable
than I2C. Thus, disabling cr50 over I2C and enabling cr50 over SPI.
BUG=b:65056998, b:62456589
BRANCH=None
TEST=make sure that we can boot into kernel
run cold_reset and warm_reset and make sure both
boot successfully.
CQ-DEPEND=CL:714237
Change-Id: I85b9a61f0305e3c7ccada79d7702234a285a6d2a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/21970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add support for google/relm (white label Chromebook) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new relm variant
- Add new shared SPD files to baseboard
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: Ife10f5f75435f356cd896588dd6f425e54f3c88e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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Add support for google/kefka (Dell Chromebook 11 3180) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new kefka variant
- Add new shared SPD file to baseboard
Sourced from Chromium branch firmware-strago-7287.B,
commit ef41a46: Kefka: Modify USB2 settings to match the eye diagram
Change-Id: Ic6c8c5e5b6029bb99039c64b0182214e93552fa2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Typo found/fixed in to-be-merged boards; applying same fix to
already-merged boards.
Change-Id: I15f97467a5442888165399be997b0b690a3c312a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Fix typos in determining single/dual channel in cyan variants
which resulted in all boards being reported as 4GB/dual channel
in the cbmem console log.
These typos were found and fixed in yet-to-be-merged variants;
this patch applies the same fixes to already-merged boards.
Change-Id: I615463668e77bd817d5270f0f04d4d01f74e3b47
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Depthcharge was complaining that the GPIO for this flag wasn't set.
The GPIO also needs to be an input, not an output.
BUG=b:67614692
TEST=Depthcharge no longer complains that there is no GPIO set for flag5.
The system boots again.
Change-Id: Ib854e97b0a3aa42a95ceb8a42a9776f0345ff8b1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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This patch is to enable the support of device sleep
for SATA port 1 and disable unused SATA port 0.
BUG=b:65808359
BRANCH=None
TEST=Ran "suspend_stress_test -c 2500" and passed the test.
Change-Id: I33b8f5fd0c51d83e154ef7daac3274ff377bc8b3
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Shelley Chen <shchen@google.com>
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Create Nautilus board which derives from Poppy, a KBL reference board.
BRANCH=master
BUG=b:66462881
TEST=Build (as initial setup)
Change-Id: I6ca5ab821a7ba1746b37dfd3ea1ed367094d4f52
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/21895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all
skylake boards to use common gpio driver. Common gpio code
defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for
skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This
resulted in Linux kernel failing to configure all GPIO IRQs since the
ownership was not set correctly. (Observed error in dmesg: "genirq:
Setting trigger mode 3 for irq 201
failed (intel_gpio_irq_type+0x0/0x110)")
This change fixes the above issue by replacing all uses of PAD_CFG_GPI
in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER.
BUG=b:67507004
TEST=Verified on soraka that the genirq error is no longer observed in
dmesg. Also, cat /proc/interrupts has the interrupts configured
correctly.
Change-Id: I7dab302f372e56864432100a56462b92d43060ee
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The mainboard_memory_init_params() and mainboard_silicon_init_params()
methods already have weak definitions in drivers/intel/fsp1_1,
so having them declared as weak in the cyan baseboard has the effect
of them not being called at all unless overridden at the variant level.
Therefore, remove the weak declarations in the baseboard and ensure
that each variant has its own init functions if needed.
TEST: build/boot google/cyan
Change-Id: I1c76cb5838ef1e65e72c7341d951f9baf2ddd41b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change 868b3761 (mainboard/google/soraka: Reduce Wacom resume time)
removed the delay after taking device out of reset since it seemed
unnecessary in system resume case (because there is enough time after
taking device out of reset and before communication with device
starts).
However, without the delay, kernel driver runs into issue while
talking to the device during boot-up and runtime
suspend/resume. (Observed this error in dmesg: "i2c_hid
i2c-WCOMCOHO:00: failed to change power setting."). Thus, add 10ms
delay after taking device out of reset. Verified on multiple Soraka
system that with 10ms delay, kernel driver does not run into any issue
talking to the WCOM device during boot-up, runtime suspend/resume and
system suspend/resume.
BUG=b:65358919
TEST=No more errors talking to WCOM device in kernel dmesg.
Change-Id: I485b753cbae4b653e74337e048aea4d26ffdbb81
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Rajat Jain <rajatja@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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mainboard_ec_init implemented by all x86-based mainboards using
chromeec performed similar tasks for initializing and recording ec
events. Instead of duplicating this code across multiple boards,
provide a library function google_chromeec_events_init that can be
called by mainboard with appropriate inputs to perform the required
actions.
This change also adds a new structure google_chromeec_event_info to
allow mainboards to provide information required by the library
function to handle different event masks.
Also, google_chromeec_log_device_events and google_chromeec_log_events
no longer need to be exported.
Change-Id: I1cbc24e3e1a31aed35d8527f90ed16ed15ccaa86
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Adapt code to latest schematic changes, revision 1.1.
Configure GPD2 for EC_PCH_WAKE_ODL,
GPP_D5 for EC_I2C_SENSOR_SDA,
GPP_D6 for EC_I2C_SENSOR_SCL,
GPP_D7 for WWAN_SAR_INT_ODL,
GPP_D9 for touchscreen power enable,
GPP_D10 for wifi power enable,
GPP_D11 for wwan power enable,
GPP_D13 change to "No Connect" (was VOL_UP_ODL),
GPP_D14 change to "No Connect" (was VOL_DOWN_ODL).
BUG=b:66265441
BRANCH=None
TEST=None
Change-Id: Ic9e76ed3e958c1f96deb6356d6480c6ba7cfe699
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/21900
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I7fd667b1cf0b7c2a5e4ab7ac7748d9636a52ae54
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21725
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I1925f51d63290b8d08366b622d5df3aab3a7484e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21737
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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GPP_C23 is read by vboot_handoff to set the WP flag. Thus, it has
to be configured in early_gpio_table.
BUG=b:67030973
BRANCH=none
TEST=Verify by wpsw_boot and wpsw_cur match.
Change-Id: I96f2b53d7bc0901ffccce46b2d8ddae80c002fdc
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21876
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes checks that ensure EC to be in RO for recovery
boot. We do not need these checks because when recovery is requested
automatically (as opposed to manually), we show 'broken' screen where
users can only reboot the device or request recovery manually.
If recovery is requested, Depthcharge will check whether EC is in RO
or not and recovery switch was pressed or not. If it's a legitimate
manual recovery, EC should be in RO. Thus, we can trust the recovery
button state it reports.
This patch removes all calls to google_chromeec_check_ec_image,
which is called to avoid duplicate memory training when recovery
is requested but EC is in RW.
BUG=b:66516882
BRANCH=none
CQ-DEPEND=CL:693008
TEST=Boot Fizz.
Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Currently the WCOMCOHO registers a reset delay of 110ms to execute their
_ON_ asl power on method. This seems to be correct as per WACOM product
design specifications but it introduces an unwanted delay in overall system
resume time. This delay should be removed from ACPI critical path since the
entire kernel resume gets blocked on this sleep call unless this is over. In
the kernel I2C communication with WACOM driver starts with the resume
callbacks of I2C HID driver which gets triggered after display is completely
resumed. The display resume process takes at least 230ms so it's safe to
reduce the delay from coreboot and unblock the critical ACPI path.
BUG=b:65358919
BRANCH=None
TEST=manual testing on Soraka board to ensure that touchscreen works at boot
and after suspend/resume. Also verify that the overall S3 resume time is
reduced by 110ms.
Change-Id: I59d070977a95316414018af69d5b43e3147ccf4e
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://review.coreboot.org/21692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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RK3399 has a pin that can decide whether GPIO port 1 is driven with 1.8V
or 3.0V. We thought this mechanism was disabled by default, but it turns
out it wasn't. We want to use that pin as an output GPIO on Scarlet so
we need to reconfigure the respective SoC controls before we do that. It
seems that we also need to explicitly pinmux the pin away from that
special function (to normal GPIO) or weird things happen on some boards.
BUG=b:66534913
TEST=Sprinkled several long udelays, poked test points with a
multi-meter on Scarlet.
Change-Id: Ia02cbb4f3b2f14b0d958b84adcddb0c5f4259efa
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/21727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Hook the new required AGESA callout functions into the callouts tables.
BUG=b:66690176
TEST=Build and boot Kahlee - see the functions get called.
Change-Id: Ife9c2b20e59ede404edb1f700238e425fea35914
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=b:62095784, b:35775024
BRANCH=None
TEST=Run powerd_dbus_suspend from kernel. Plug in
usb device and make sure wakes up.
Change-Id: I214d6557998bdaf1d327c2a45532461b95d56a96
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add zoombini board files using cannonlake and FSP 2.0.
Copied most initial files from poppy and cannonlake_rvp.
BUG=b:64395641
BRANCH=None
TEST=Compiles successfully using "./util/abuild/abuild
-p none -t google/zoombini -x -a"
Change-Id: I13ebaae403d08f1b2e6881eeba4dc1787c792b4e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/21273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Modify the HID to align with ACPI spec. Add the DSD object
for the device tree support in kernel which will probe
the DW9714 device based on the HID.
BUG=b:65423422
CQ-DEPEND=CL:654383
BRANCH=none
TEST=Build and boot soraka. Verified that the VCM device
probe is successful.
Change-Id: Ic4a59dd2027267fbd3837fcd7dbc00551a69f7d6
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/21508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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We need support two touchpad for Robo project,
so adding Synaptices touchpad to coral.
BUG=b:63134907
TEST=Compiled, verified by ODM
Change-Id: If5a650338d5a7e6f01e9525d28588b871d390e50
Signed-off-by: Peggy Chuang <peggychuang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/21696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use a single define and set the CROS GPIO ASL device to match the
Stoney Ridge GPIO HID. Update the GPIO number to 142. Also, add a DDN
field in the GPIO ASL. This addresses the TEST indicated below.
BUG=b:65597554
BRANCH=none
TEST=grep ^ /sys/devices/platform/chromeos_acpi/GPIO.*/* reports AMD0030.
Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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