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Currently, SA IMGU gets enabled by the option SaImguEnable,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SA IMGU controller.
All corresponding mainboards were checked if the devicetree
configuration matches the SaImguEnable setting, and missing entries
were added.
Change-Id: I293a20a321c75f82a57cbd5339656d93509b7aa6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Currently, SDXC gets enabled by the option ScsSdCardEnabled,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SDXC controller.
All corresponding mainboards were checked if the devicetree
configuration matches the ScsSdCardEnabled setting, and missing
entries were added.
Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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This reverts the code from commit 728c0787f2 that removes the reset
GPIO from the touchscreen ACPI interface.
That patch exposes a bug which leads to an invalid opcode trap in the
touchscreen code. Reverting this gets the system working again, but is
not a long-term solution.
BUG=b:162596241
TEST=System boots to login screen.
Change-Id: I57a070d94f961cec43834c8bedd5dafc8a54171a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43078
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently SA thermal subsystem gets enabled by the option Device4Enable,
but this duplicates the devicetree on/off options. Therefore depend on
the devicetree for enablement of the SA thermal subsystem controller.
All corresponding mainboards were checked if the devicetree
configuration matches the Device4Enable setting, and missing entries
were added.
Change-Id: I7553716d52743c3e8d82891b2de14c52c6d8ef16
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44026
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently HECI1 gets enabled by the option HeciEnabled, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement/disablement of the HECI1 device.
All corresponding mainboards were checked if the devicetree matches
the HeciEnabled setting, and adjusted where necessary.
Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Allow variants to override the SPD_SOURCE_PATH to allow supporting
different types of DDR.
BUG=b:163065661
TEST="emerge-volteer coreboot" and verify all variants build.
Change-Id: Id52e651848548a783d6d9f57e88f6099425b063e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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This reverts commit 3d813cbede650a89a519d5896652328e4ecf88c6.
Reason for revert: the CL made the build unstable.
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I9d067eb13196ff7d537d557d8ff864b1572a3b04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43076
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Decrease the SPI ROM size from 32 MB to 16 MB
BUG=b:58540772
BRANCH=None
TEST= build firmware and check the magolor bin size
Change-Id: Ie7ddf698fde1dbf663859d5654946bc08abe737c
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Update dq/dqs mappings based on halvor schematics.
BUG=b:162892573
BRANCH=none
TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage
Change-Id: I98f79283aa18f6fd41114fb6b60cac1cbed69de7
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43988
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPIO_89 was marked as EN_DEV_BEEP_L in pre-v3.6 schematics, but it was
never really used on any of the zork variants. Starting with v3.6,
GPIO_89 is left unused in schematics.
This change configures GPIO_89 as PAD_NC in baseboard GPIO
table. Since EN_DEV_BEEP_L still needs to be driven high to allow
speakers to work, GPIO_89 is configured as PAD_GPO driven high on
pre-v3.6 schematics.
BUG=b:62108046
Change-Id: I026cd6cb598667ce6e115c3ec9357a6a56051d39
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44190
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds support for touchscreen power control using:
* GPIO_90 for trembyle based boards
* GPIO_32 for dalboz based boards
By default, baseboard tables configure these GPIOs as PAD_GPO driven
low and override trees expose these pads as enable_gpio to be used by
ACPI power resource.
In order to support pre-v3.6 boards, override tables configure these
pads as PAD_NC and drop the enable_gpio setting from device tree based
on board version.
BUG=b:161935640, b:162747210
Change-Id: Iba5e36b65b44ea11613b4d5fc8f13ce6433f83ab
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44193
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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v3.6 of reference schematics have switched the polarity of reset
signal to touchscreen controller from active high to active low. This
change updates the default configuration in baseboard gpio tables to
set the reset GPIO to output low and override tables in variants to set the
reset GPIO to output high. Additionally, devicetree by default exposes
ACTIVE_LOW configuration for reset GPIO. In order to support pre-v3.6
boards, reset GPIO is updated to ACTIVE_HIGH based on board version.
BUG=b:161937506
Change-Id: I092f274d8eb1920a1cd6d3eccbe8f26b0b28928a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Create function update_dmic_gpio to update DMIC GPIO for ACP machine and
use find_dev_nested_path function for consistency.
BUG=None
BRANCH=None
TEST=None
Change-Id: I96cf207f24c6117d98ff2bf7e6e5cd282489e805
Signed-off-by: Josie Nordrum <josienordrum@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44158
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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HP_INT_ODL is no longer connected to CODEC_GPI in schematic version 3.6.
Split variant_audio_update into update_dmic_gpio and update_hp_int_odl.
Changed GPIO_29 from PAD_NC to PAD_GPI in Trembyle. Changed GPIO_84 from
PAD_NC to PAD_GPI for Dalboz. Changed HP_INT_ODL to appropriate pin in
both boards devicetree.cb.
BUG=b:161938476
BRANCH=None
TEST=None
Cq-Depend: chromium:2335424
Change-Id: I05ffb063ab99823d07be6eaa911efbde3cc4ff55
Signed-off-by: Josie Nordrum <josienordrum@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44157
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Added VARIANT_SUPPORTS_PRE_V3_6_SCHEMATICS and
VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS. Added helper functions to check
if variant uses v3.6 and if variant uses CODEC GPI.
BUG=b:161938476
BRANCH=None
TEST=None
Change-Id: If86e1ea3c02db354c7b410f1bbc1daacb483cc51
Signed-off-by: Josie Nordrum <josienordrum@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44156
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new ddr_memory_cfg structure to support both DDR4 and LPDDR4x
memory types.
Change existing variant code to use the new meminit_ddr() call
instead of calling meminit_lpddr4x() directly.
BUG=b:161772961
TEST='emerge-volteer coreboot chromeos-bootimage' and verify that
volteer still boots. NOTE that this only tests the lpddr4 side
of the implementation as I do not have a DDR4 board to test this on.
Change-Id: Id4bca2bfa97530f0d04a0e8d90f01b8281d2aea6
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Newer boards have removed the second temperature sensor
and relocated the remaining sensor.
BUG=b:162909373
TEST=Confirm on hardware.
Change-Id: Ie41a57598b0c87a6632f4c55c0f60a94a89cae43
Signed-off-by: Andrew McRae <amcrae@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Set correct DDR geometry for all existing memory modules.
BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: I9b53ab2bf43e0dfb7448eb37a18faf686267eaed
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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A new board introduced to Kukui family.
BUG=b:162478693
TEST=make # select Fennel
BRANCH=kukui
Signed-off-by: xiatao5 <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I1f742a36793f38c37fbd4e1b4cbddbd542e785ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44061
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Zhaoyou Hong <hongzhaoyou@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update gpio GPP_E7 and enable the Raydium TS support
BUG=b:157402209,b:162632701,b:162636271
BRANCH=master
TEST= 1. emerge-volteer coreboot chromeos-bootimage
2. boot up on voxel DUT and make sure the raydium TS can work.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I377aded4982ece71f4dabb58f307f68c713edcd2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
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update telemetry value for SDLE test result.
BUG=b:160698427
BRANCH=None
TEST=emerge-zork coreboot
Change-Id: Icce57f9be2732ff79f336daa6c447a30247366cf
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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a. USI_REPORT_EN is no longer set to high in coreboot. Instead
GPIO_144 is exposed as stop_gpio in ACPI to allow OS to control this
pad as required.
b. Add Delay after stop_gpio Low - 300ms
BUG=b:162263398
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: I3d4dcb6e5cae5d9515abfd415315ec4114ca80b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44107
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I5d3a5ede47aefc7cc2ee330f8a0bcded16138764
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44173
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This cleans up some unneeded no-ops in the mainboard.c files
of baytrail boards.
Change-Id: I7662f6e860d672a99b211488122bec073cc78acf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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DRAM support list
0x00 HYNIX HMA851S6CJR6N-VK
0x01 HYNIX H5ANAG6NCMR-VKC
0x02 Samsung K4A8G165WC-BCTD
0x03 Samsung K4AAG165WB-MCTD
0x04 Samsung K4A8G165WC-BCWE
0x05 HYNIX H5AN8G6NDJR-XNC
0x06 HYNIX H5ANAG6NCMR-XNC
0x07 Micron MT40A512M16TB-062E:J
0x08 Micron MT40A1G16KD-062E:E
0x09 Samsung K4AAG165WA-BCTD
0x0A Samsung K4AAG165WA-BCWE
BUG=b:161579679
BRANCH=master
TEST=build
Change-Id: Ib9fa5ae98568d659326d431a4006174a343fa299
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change adds support for pen insert/eject operations in S0 and
wake on pen eject from S3 for vilboz.
BUG=b:157628650
Change-Id: I7ba0881b67dfb67c032667d591f7d1806a50af22
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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It is the same for the two Bay Trail boards in the tree.
Change-Id: I5110cfa8807406232e4f7f1fe79dfe9c3ae4dac4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
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Use tabs instead of eight (sometimes less) spaces.
Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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In kernel clk for AMD SoCs we expose a generic clk by the name oscclk1.
This oscclk1 is a fixed 48Mhz frequency clk in RV.
In Zork oscout system clock is linked to rt5682 mclk. Setting mclk-name to
oscclk1 tells rt5682 driver its mclk is oscclk1.
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
BUG=b:158906189
TEST=rt5682 driver get the correct clk and tested audio playback
Change-Id: Ic565e8e0573e085e5759b2d3688cc0a4533b67fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Observed thermal shutdown initiated by DPTF due to CPU temperature
reaching critical temperature trip value. During stress testing with
heavy workload like WebGL Aquarium, sometime CPU temperature spikes
till 99 degree Celsius and DPTF initiates system shutdown. This
updates CPU critical temperature trip value to 105 degree Celsius
to avoid system shutdown.
BUG=b:161993459
BRANCH=None
TEST=Built and tested on dedede system
Change-Id: If15a873a997aa80f20940f27bbafd4498908c091
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44054
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Support 8GB MT53E2G32D4NQ-046 discrete DDR bootup.
BUG=b:159301679
BRANCH=kukui
TEST=Boots correctly on Kukui.
Change-Id: Ide01f029c5ebd6c3ae6350f73f3c60b818d51353
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add RTL8822CE support for Madoo.
BUG=b:162390420
BRANCH=None
TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage, build successful
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I6e471be2b2856977e6f728d5a2ca78942725bea6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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1. Add Elan touchpad support.
2. Follow schematic to disable I2C1 and I2C3.
BUG=b:160869188,b:161407664
BRANCH=NONE
TEST=emerge-dedede coreboot chromeos-bootimage", build successful
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I154a1ff2597968d200d1d0693718f90cd2744616
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Add Goodix touchscreen support.
BUG=b:160868197
BRANCH=None
TEST=emerge-dedede coreboot chromeos-bootimage", build successful
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I9bf27d69d0895cb4ea8620a6da49e98d25e05c23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44012
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ACPI_GPIO_IRQ_EDGE_BOTH sets both edges as wake. The desired behavior is wake on rising edge, change to ACPI_GPIO_INPUT_ACTIVE_LOW.
Fixing for both Volteer and Volteer2 variants.
BUG=b:146083964
BRANCH=None
TEST=tested on a Volteer
Change-Id: I2d3339151bf4e2cbae60aaf97ba1bd7909a2b9a9
Signed-off-by: Alex Levin <levinale@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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The 'burnet' and 'esche' in Kconfig.name should have two spaces
after the arrow.
BUG=None
TEST=make menuconfig
BRANCH=kukui
Change-Id: If7cc31cf459082a797445fb8223b3d9cbde72901
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43986
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update ELAN i2c-hid touchpad configuration
BUG=b:160741785
BRANCH=None
TEST=Verify touchpad is working fine.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I2549048766d0707666910bd86c46ac9201bf3905
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43998
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For dirinboz
DRAMID 0x9: K4AAG165WA-BCTD
BUG=b:161579679
BRANCH=master
TEST=build
Change-Id: I28c0d23f96c5b9c975ffead3a1cac66cbda8c293
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Set platform defaults for SPI settings in Kconfig for EFS.
BUG=b:158755102
TEST=Build and boot test on Tremblye and Morphius. Verify
values in output image in a hex editor. Measure 1st x86
timestamp, perf improves by over a second.
Change-Id: I765dada14700f4800263d2d3844af07fad0e5b71
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43303
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There was a mix of open coding DXIO logical lane numbers and clkreq
pins. And there are separate macros depending on the baseboard
as well as processor type. Remove the indirection and supply the values
directly in the descriptors.
BUG=b:162423378
Change-Id: I779cb0a514e3b668265e6039d6e7e7bd0f3d49ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Configure the correct eMMC present flag for Ezkinil new added sku_id.
0x5A020015 NVME present
0x5A020016 eMMC present
0x5A020017 eMMC present
BUG=b:159761042
TEST:none
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: I1b89cc4568283d5dbebf0ab7ac578368d3a3637e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43753
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:162010077
Change-Id: Iba3e3ec62cdfd818077017abd28fa754c2ae7797
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add overridetree info for the touchscreen.
BUG=b:160129126
TEST=cros flash-ap -b dedede
Signed-off-by: Evan Green <evgreen@chromium.org>
Change-Id: I55fc0749b824a0bf4b615d02bd8bc39bcdd589e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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|
It is expected TCSS D3Hot is enabled. D3Cold configuration is
through SoC stepping determination. D3Cold is disabled on pre-QS
platform and enabled on QS platform.
BUG=None
TEST=Verified both of TCSS D3Hot and D3Cold configuration on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I9a8b838dcb449ca78d15b18543d97d84b59417ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44004
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently HDA gets enabled by the option EnableAzalia, but
this duplicates the devicetree on/off options. Therefore use
the on/off options for the enablement of the HDA controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableAzalia setting.
Change-Id: Id20d023b2f286753fb223050292c7514632e1dd3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43866
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently eMMC gets enabled by the option ScsEmmcEnabled, but this
duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the eMMC controller.
I checked all corresponding mainboards if the devicetree configuration
matches the ScsEmmcEnabled setting.
Change-Id: I3b86ff6e2f15991fb304b71d90c1b959cb6fcf43
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
|
|
Currently TraceHub gets enabled by the option EnableTraceHub, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the TraceHub controller.
I checked all corresponding mainboards if the devicetree
configuration matches the EnableTraceHub setting.
Change-Id: Idcd1e5035bc66c48620e4033d8b4988428e63db9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43847
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently SMBus gets enabled by the option SmbusEnable, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SMBus controller.
I checked all corresponding mainboards if the devicetree configuration
matches the SmbusEnable setting.
Change-Id: I0d9ec1888c82cc6d5ef86d0694269c885ba62c41
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
|
|
Currently LAN gets enabled by the option EnableLan, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the LAN controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableLan setting.
Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Currently SATA gets enabled by the option EnableSata, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SATA controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableSata setting.
Change-Id: I217dcb7178f29bbdeada54bdb774166126b47a5a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
|
|
sustained_power_limit = 12w
fast_ppt_limit = 24w
slow_ppt_limit = 20w
BUG=b:162377903
BRANCH=master
TEST=emerge-zork coreboot chromeos-bootimage
Change-Id: I9baf9990e26edbbadfba85bc16b380c46684033d
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory part being added is:
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
H9HCNNNBKMMLXR-NEE
MT53E1G32D2NP-046 WT:A
K4UBE3D4AA-MGCR
BUG=None
TEST=Build the magalor board.
Change-Id: I7bb19d6d4a66e66fed0564592c803c2af1045b0c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add bluetooth reset gpio 143 to dalboz baseboard devicetree
Add bluetooth reset gpio 14 to trembyle baseboard devicetree
Remove bluetooth reset_gpio when not supported on a specific board
variant.
BUG=b:157580724
TEST=Boot Ezkinil with Realtek 8822CE, observe log
[ 12.240720] Bluetooth: af_bluetooth.c:bt_init() HCI device and connection manager initialized
[ 12.249272] Bluetooth: hci_sock.c:hci_sock_init() HCI socket layer initialized
[ 12.256520] Bluetooth: l2cap_sock.c:l2cap_init_sockets() L2CAP socket layer initialized
[ 12.264575] Bluetooth: sco.c:sco_init() SCO socket layer initialized
[ 12.273700] usb 3-2: GPIO lookup for consumer reset
[ 12.273702] usb 3-2: using ACPI for GPIO lookup
[ 12.273705] acpi device:18: GPIO: looking up reset-gpios
[ 12.273707] acpi device:18: GPIO: looking up reset-gpio
[ 12.273711] acpi device:18: GPIO: _DSD returned device:18 0 0 0
[ 12.273737] gpio gpiochip0: Persistence not supported for GPIO 14
[ 12.273960] usbcore: registered new interface driver btusb
Change-Id: I14e3ef099d5b8f48c915b41284039b3508dec975
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
H9HCNNNBKMMLXR-NEE
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
BUG=b:161215903
BRANCH=NONE
TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ib61af2399541c4caf4a310a34e778e0ba1cbd3ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43802
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Select the drivers for ALC5682 codec and MX98360A spk amp
BUG=b:161407664
BRANCH=NONE
TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ibe3d878b1058bfae4143d96be854884e61394ad5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Follow schematic to modify USB port setting and clean up I2C clock tuning.
USB2 [0]: USB Type C Port 0
USB2 [1]: USB Type C Port 1
USB2 [2]: None
USB2 [3]: USB Type A Port 1
USB2 [4]: None
USB2 [5]: Camera
USB2 [6]: None
USB2 [7]: WLAN module - BlueTooth
USB3 [0]: USB Type C Port 0 (M/B side)
USB3 [1]: USB Type C Port 1 (Sub/B side)
USB3 [2]: None
USB3 [3]: USB Type A Port 1
USB3 [4]: None
USB3 [5]: None
BUG=b:161407664
BRANCH=NONE
TEST=Build the coreboot image on madoo board.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ia73593f52adee3806e725127891f084a08bf1360
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43750
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Follow schematic to modify some GPIO pins.
GPP_D12 - NC Pin
GPP_D13 - NC Pin
GPP_D14 - NC Pin
GPP_D15 - NC Pin
GPP_E0 - NC Pin
GPP_E2 - NC Pin
GPP_H6 - NC Pin
GPP_H7 - NC Pin
GPP_S02 - NC Pin
GPP_S03 - NC Pin
BUG=b:161407664
BRANCH=NONE
TEST=Build the coreboot image on madoo board.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I85aadfb0d020055eec921c7646c16ae6c95a606f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43745
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update dq/dqs mappings based on voxel schematics.
BUG=b:155062561
BRANCH=none
TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ida248094a1477fe457026e18f313385082ee71f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43794
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec.
This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring
the bus frequency closer to 400kHz.
BUG=b:153588771
TEST=Verified that I2C5 frequency is between 389-396kHz.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: If59502aec7c3ab55864a518d626cde52aee18373
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43746
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This copies over the USB daughterboard device tree config from volteer
to volteer2. These two boards are basically identical in this area so
the config should also be identical.
BUG=b:158673460
TEST=none
Change-Id: If8a82bc18b36d92a1c851b49612edfbefa18ec54
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
BUG=b:161734657
TEST=Ensure that the discrete WiFi information is built into ACPI table.
Scope (\_SB.PCI0.RP01)
{
Device (WF00)
{
Name (_UID, 0x923ACF1C) // _UID: Unique ID
Name (_DDN, "WIFI Device") // _DDN: DOS Device Name
Name (_ADR, 0x00000000) // _ADR: Address
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x43,
0x03
})
}
}
Change-Id: I9a9259e167fc213291b89e151729553ec4649eaf
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43769
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Todor is created to take the place of terrador therefore
copying terrador content into todor's setup.
BUG=b:162110806
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_TODOR
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I63151728a04f2252ca8a77158a2656ad8b1e1b51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Create the todor variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
In addition,
* sort the variant names in alphabetical order.
* todor uses the same config options as terrador.
BUG=b:162110806
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_TODOR
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I7aa7acf1f3c3cc14b92ded05d5868818a627a432
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
All boards disable PIRQs, except purism/librem_bdw. Since IRQ0 is
invalid and modern OSes don't use PIRQ routing, disable the PIRQs.
Change-Id: I93b074474c3c6d4329903cab928dc41e1d3a3fb3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
All boards disable PIRQs. They aren't used on modern OSes anyway.
Change-Id: I1351fd4a3910e8cf2e9afe51dc2e82c7464de403
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Create the eldrid variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:162115131
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_ELDRID
Signed-off-by: MiceLin <mice_lin@wistron.corp-partner.google.com>
Change-Id: I1cd07ee7a87335e1e0b51d65c26bffc3bc46037c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
Some smart battery patches have been backported to the ChromeOS 4.19 kernel,
and userspace can now access smart battery data from sysfs instead of using
the hacky ectool instead.
Also change all space indents into tab indents while we're here.
BUG=chromium:1047277
TEST=confirmed a /sys/class/power_supply/sbs-i2c device shows up
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I43687e63e4c1a7756c117129ced20749afc1b9e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
LPDDR4x DRAM table for burnet/esche:
[1] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB"
[2] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB"
[3] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB"
[4] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB"
BUG=b:161768221,b:159301679
BRANCH=master
TEST=emerge-jacuzzi coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Ida7ab877c3f7e10a67680b69a1d724ec734d2928
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Use gpio_keys driver to add ACPI node for pen eject event. Also
setting gpio wake pin for wake events.
Removal and insertion (both edges) triggers IRQ and only removal is a
wake event (rising edge).
Adding for both Volteer and Volteer2 variants.
BUG=b:146083964
BRANCH=None
TEST=tested on a Volteer
Change-Id: Ida3217a5b156320856ce3302c2623eba2230f28d
Signed-off-by: Alex Levin <levinale@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43764
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update delbin configuration include GPIO, memory SPD table, I2C devices
and USB type C.
BUG=b:158797761
BRANCH=None
TEST=emerge-volteer coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I59ce4720e0ffeeeb2c9440bb300686def80211ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42301
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
MRC automatically detects the DDR type and sets Rcomp resistor
and target values for JSL and does not require explicit programming.
Change-Id: Ia130765e2cb91d6a39ad00ebbab20e7e87fa42d1
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Create the magolor variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:58540772
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_MAGOLOR
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I3e39e650b82a0aa629a48a00227700b058effb34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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If bit 7 of a PIRQ route is set, it is disabled. Modern OSes don't use
PIRQ routing, so we might as well zero the other bits for consistency.
Tested on Asrock B85M Pro4 with SeaBIOS 1.13.0, still boots.
Change-Id: I78980b9ea5e878a6200df0f6c18c5e7d06a7950a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43861
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update ELAN i2c-hid touchpad configuration
BUG=b:160741785
BRANCH=None
TEST=Verify touchpad is working fine.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I098d8a305c6e04af1562a545ff4af6383665798b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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For devices sharing same firmware, there may be few customization based
on SKU ID - for example being clamshell or form factor. On Kukui and
Jacuzzi platforms the SKU ID is defined on AP SOC, so we have to send
the information to EC.
BUG=b:161767717
TEST=make -j # builds and boots on Juniper
BRANCH=kukui
Change-Id: I8ffdd9fd1e609c1dd4b0e22dc7aab560ccdc842e
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43788
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust GPIO setting to match boten design
BUG=b:160741777
BRANCH=NONE
TEST=Add gpio.c for boten
Signed-off-by: Yan Liu <yan.liu@bitland.corp-partner.google.com>
Change-Id: I4eafee608f657f8ec5a06caf6e99b08b3330512b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43277
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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HDMI DDC GPIOs were configured as NC till now in waddledoo.
This may cause HDMI i2c transfer to break and EDID read will
fail due to wrong configuration
Configuring these GPIOs as NF in coreboot to fix the issue.
BUG=b:160324327
BRANCH=None
TEST=HDMI works on DDI2 onn Type-C port
Change-Id: If02f062132d7c3b01b07ea9401e81f451df35c3c
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43294
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tune I2C bus3 frequency and insure it meets I2C spec.
BUG=b:161650117
TEST=flash coreboot to the DUT and actual measured I2C bus3
make sure it meet Spec.
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ifa9f0bce723f55a12fd2313788c995f8326e3e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43661
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Iac0f0c3d102a9a900ac168f8be907349d9a3dd42
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43565
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:155002684
TEST=build drawcia, and check touchscreen can work
Change-Id: I29a891e07bb3c1d8ebe17666c18bfcf3bc1c361d
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Change-Id: I7378aa7d6156ece3ab3959707a69f45886f86d21
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43593
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There's a `GPL-2.0-or-later` version of this file in volteer2, so use it
in place of these weirdly-licensed files.
Change-Id: Icde2f6539d9c726d6967350f74e7bc015e01e7b5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Put them in common code just in case something depends on the values.
Change-Id: Ief526efcbd5ba5546572da1bc6bb6d86729f4e54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43851
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This applies what commit 79572e4f32f844f60338d1aafdba6b94f4111a5c does
to the devicetree settings of the zork devices.
Change-Id: Ife94818d771f137e56c51ad1598148f60fcf5345
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43820
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:161923068
Change-Id: I67f23c0602e345fbd806e661a4462cf07f93ef64
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43783
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since FSP pre-populates the UPD struct with the non-zero default values,
coreboot shouldn't set them to zero in the case that they aren't
configured in the board's devicetree. Since all parameters being zero is
a valid case, this patch adds another devicetree option that applying
the devicetree settings for the USB2 PHY tuning depends on being set.
BUG=b:161923068
Change-Id: I66e5811ce64298b0644d2881420634a8ce1379d7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43781
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set power limits in devicetree for Tiger Lake Y-SKU based volteer
variant boards.
BUG=b:152639350
BRANCH=None
TEST=Built and tested power limits on volteer variant board.
Change-Id: If4f1226473b48365e5962df9fff29910c99007fc
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43607
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In the middle of the Great DPTF Refactor of 2020, new volteer variants
were added, but their dptf.asl files are no longer used, so delete them.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I52f2042aa870a29026eb9fe122340ad07654e706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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SKUID
51 - Garfour EVT (non-touch, TypeA DB)
52 - Garfour DVT (touch, HDMI DB)
BUG=b:161554087
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
Change-Id: I3cb17c2b665c303da210817a531c869c6324b249
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Henry Sun <henrysun@google.com>
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The Raydium ACPI entry currently provides a reset GPIO and an _ON/_OFF
method to the kernel. These are contradictory. The ownership of the GPIO
should be mutually exclusive between either the OS or the FW. Since we
have two methods exposed this causes the OS to reset the TS twice. Once
using the _ON method, and once using the GPIO. Additionally the _ON
method is waiting for 20ms after reset while the OS driver uses a 50ms
delay. The Raydium TS datasheet specifies 20ms for FW ready time, so the
OS driver is adding additional padding.
The reference design has a 32ms rise time on the reset line. So without
this patch, the OS tries to reset the TS using the _ON method and it
waits for 20ms. This is not enough time for the reset line to reach
high, let alone account for the FW ready time. The OS driver then tries
to reset the device by toggling the GPIO. It waits 50ms which is still
2ms less than required.
This CL removes the GPIO from being exported in the _CRS so the OS
driver won't try and reset the device. It also increases the reset delay
by 32ms to account for the rise time.
This isn't a complete fix. I think that the slow rise time is causing
some kind of metastability in the TS reset hardware. Using a script to
bind and unbind the TS driver, the TS device becomes unresponsive after
~200 iterations. The only way to reset the device is to power cycle.
The TS power is also not currently controlled by the power resource.
This means that we have no guarantee over when the reset line is
toggled. This will lead to issues while spending and resuming.
BUG=b:160854397
TEST=Boot trembyle and make sure TS works. Suspend/Resume trembyle 300+
times.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I23131be5d7109eed660a8bd6e2c156c015aa3c4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Earlier versions of Dalboz did not correctly handle HS400. One fix was
to add stitching vias, but these boards did not have them. b/156539551
Another possible fix is to add tuning parameters including drive
strength, but that is still a WIP. b/158959725
This should correct OS load failures in the meantime by running the bus
slower.
BUG=b:158845662
TEST=build, flash, boot sku 0x5a80000c to OS
BRANCH=None
Signed-off-by: Eric Peers <epeers@google.com>
Change-Id: Ia3e7a641bde04c5a7be29bf91c38dd8c110ed17a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43572
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the dirinboz variant of the dalboz reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:161579679
BRANCH=master
TEST=util/abuild/abuild -p none -t google/zork -x -a
make sure the build includes GOOGLE_DIRINBOZ
Change-Id: I33c03080ffbe0bca61acf4144417b9f5fff6389f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add PCIe-eMMC bridge bayhub 720 on Arcada to the devicetree.
BUG=b:157971972
BRANCH=sarien
TEST=local build and boot from SATA/PCIe-eMMC storage successfully
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I7e925730e57806e7398684dffd0d3bd1f4f9deeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43669
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add PCIe-eMMC bridge bayhub 720 on Sarien.
BUG=b:157971972
BRANCH=sarien
TEST=local build and boot from storage successfully
Change-Id: I28f40a420d51f476487655548f386cfbdc2e5329
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
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Reset the Touchscreen (TS) and disable the stop GPIO (report switch) at
the same time. Add a delay of 100 ms after disabling the stop GPIO. This
will ensure the required delay is inserted for both reset and stop
disable GPIOs simultaneously.
BUG=b:152936541
TEST=Build and boot the waddledoo mainboard. Ensure that the SiS
Touchscreen is functional.
Change-Id: Icbfb5e07a28ab72b1ff696ad1183a6c2173dcaac
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43453
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
H9HCNNNBKMMLXR-NEE
K4U6E3S4AA-MGCR
BUG=None
TEST=Build the drawcia board.
Change-Id: Id05c0b2a87b64bfedc761949cbc8ad6cf7dd73a5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43505
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change does the following:
a. USI_REPORT_EN is no longer set to high in coreboot. Instead
GPIO_144 is exposed as stop_gpio in ACPI to allow OS to control this
pad as required.
b. Appropriate delays are added for power-down sequencing:
- Delay after REPORT_EN is disabled - 1ms
- Delay after RESET is asserted - 1ms
BUG=b:159501288
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: If4d12fa0d4f4e5123d8fdccdabda996dcafa4523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Morphius uses Goodix touchscreen and not G2 touchscreen. This change
updates hid and desc properties in devicetree accordingly.
BUG=b:159501288
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I2527fa5409bb127ac225c6fb2a5f1bc24895f6cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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GPIO_91 is added to ACPI using the device tree entry for codec. So,
this change drops the TODO from GPIO table.
Change-Id: I9c2e91465ab554126531f8512028360ae5fb316d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change configures all missing pads in ramstage for dalboz
reference. This ensures that the state of all pads is set correctly
for the payload/OS. Also, all the pads for the platform are configured
in baseboard gpio table in ramstage to ensure that variants can
override any pads if required.
BUG=b:154351731
Change-Id: Ia30da908d3827177a7b3594ffba38bff81018ab9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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