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2021-05-12mb/google/dedede/var/boten: Probe and enable amplifier operation modeStanley Wu
Probe the fw_config for RT1015 speaker amplifier operation mode and enable it accordingly in the device tree. BUG=b:180570923 BRANCH=dedede TEST=ALC1015Q-VB drive speaker OK Change-Id: I756bfa6f604ed320de9a515821979aa95c869ebf Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-12mb/google/dedede: Add GPIO and SPD for pirika supportKirk Wang
Add support for GPIO and SPD driver for pirika BUG=b:184157747 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Change-Id: Id367a83b04aad62b7deabae99b3f91905a2fc46c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-11mb/google/dedede/var/metaknight: Update LTE USB port configurationKarthikeyan Ramasubramanian
Update LTE USB port configuration at run-time after probing the firmware config. By default the concerned USB port takes the Type-A port configuration. BUG=b:186380807 BRANCH=dedede TEST=Build and boot to OS in metaknight Change-Id: I5ad5a1670adef54075923cf912fb41a1ce776155 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Raymond Wong <wongraymond@google.com>
2021-05-11mb/google/dedede: Add a variant callback to update devicetree configDavid Wu
This callback is required to update the devicetree config at run-time after probing the firmware config. BUG=b:186380807 BRANCH=dedede TEST=Build and boot to OS in metaknight. Change-Id: I857211bfc4beb36ab225f3786c1707336a34aae9 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Raymond Wong <wongraymond@google.com>
2021-05-11mb/google/kukui: Add discrete EMCP LPDDR4X table for Kakadu/KatsuSunway
Add EMCP LPDDR4X DDR FEPRF6432-58A1930 for ram id 9. BUG=b:186141919 BRANCH=kukui TEST=New Emcp can boot normally on kakadu/katsu Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ieaf05a0a7b0c0671c07b0df29319ebd91fe63e57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54009 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10mb/google/cherry: Configure TPMYidi Lin
Change-Id: I1d6ecdb31eef65d2e96d9251348390aa8598be6c Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-10mb/google/cherry: Enable Chrome ECYidi Lin
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iab3549b5c4e7d845ddd284a0df3fb448e11fbdcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/53899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-10mb/google/mancomb: Fix TPM setting in devicetreeIvy Jian
Fix I2C3 setting for TPM in devicetree. BUG=b:187341277 TEST=Build and boot into OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I728da76cee0c92c29df4c6ee8bfb4cd07a6366c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-10mb/google/guybrush: Enable GFX HDA deviceKarthikeyan Ramasubramanian
Enable Display Controller Engine Audio endpoint to enable HDMI audio. BUG=b:186479763 TEST=Build and boot to OS in guybrush. Change-Id: I5e35440e8e70ee125d37c7ac30c9219ec69c7c6e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-10mb/google/guybrush: Enable PP5000_PENEric Peers
Everybody wants a stylish stylus. Enable the power system to it. BUG=b:186267293 TEST=connect multimeter to PP5000_PEN and see it go from 0 to 1. MAGIC! Signed-off-by: Eric Peers <epeers@google.com> Change-Id: I11d05c118ec9451d26136c320f3650c489e02c59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-10soc/mediatek/mt8195: Add RTC driverYuchen Huang
Both mt8192 and mt8195 use MT659P RTC. Move mt8192/rtc.c to common folder and rename to rtc_mt6359p.c. Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I73ea90512228a659657f2019249e7142c673e68e Reviewed-on: https://review.coreboot.org/c/coreboot/+/53897 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10soc/mediatek/mt8195: Add clk_buf driverYuchen Huang
Both mt8192 and mt8195 use mt6359p clk_buf. But mt8195 clk_buf uses legacy co-clock mode without srclken_rc. Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Change-Id: Ie9ee91449a7a14e77231493f807b321b2dbaa6a6 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-10soc/mediatek/mt8195: Configure eMMC and SDCardWenbin Mei
Change-Id: I0ed82e860612e8a62f361e60d217280f775ab239 Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53895 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-09mb/google/guybrush: Populate PIC IRQ dataRaul E Rangel
The PIC IRQs are required so we can correctly set up the PCI_INT registers. This only matters when booting in PIC mode. We don't need to set the IO-APIC registers since the linux kernel will auto-assign those to reduce conflicts. BUG=b:184766519 TEST=Boot guybrush with `pci=nomsi,noacpi amd_iommu=off noapic` and verify xhci and graphics continue to work. $ cat /proc/interrupts 12: 285064 XT-PIC nvme0q0, nvme0q1, rtw88_pci 13: 100000 XT-PIC xhci-hcd:usb1 14: 4032 XT-PIC amdgpu, xhci-hcd:usb3 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1d66ccd08a86a64242dbc909c57ff9685828f61f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52915 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-08mb/google/volteer: adjust the size for RO/RW mcacheZhuohao Lee
The mcache is overflowed in the latest build. In order to fix the mcache overflow, we increase the mcache size to 0x4000 and adjust the percentage to 50% for the ro/rw mcache. This change is for all of the volteer variants as we see many of the volteer variants which use the latest bios having the mcache overflow issue. BUG=b:187095474, b:187095765, b:187234881, b:162052593 TEST=no mcache overflow in the bios log Change-Id: If9552bc9fa5d36b1ca662c9da030ae7b137b60a8 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-05-08trogdor: Add backlight support for sn65dsi86bridge for HomestarVinod Polimera
Add backlight support in sn65dsi86bridge through the AUX channel using eDP DPCD registers, which is needed on the GOOGLE_HOMESTAR board. Change-Id: Ie700080f1feabe2d3397c38088a64cff27bfbe55 Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52663 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-07skylake mainboards: Use enum values for SaGvAngel Pons
Replace `3` with `SaGv_Enabled`, which has the same value. Change-Id: I05cfddfefc45ba5bfb0e684445a6d8e02d7865e3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-05-07mb/google/volteer: Create volet variantSheng-Liang Pan
Create the volet variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:186334008 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_VOLET Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ic6ca9a78494e3819b0fb39c0bcc70fed95c2c589 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-05-07mb/google/cherry: configure GPIOsYu-Ping Wu
Configure Chromebook specific GPIOs, including EC_AP_INT, SD_CD, EC_IN_RW, GSC_AP_INT and EN_SPK. Change-Id: Id553f632412af440d21a3b51e017cb74cc27fd22 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52924 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-07mb/google/volteer/var/elemi: Add spd for K4AAG165WB-BCWEWisley Chen
Add SPD support to elemi for K4AAG165WB-BCWE BUG=b:187379245 TEST=FW_NAME=elemi emerge-volteer coreboot chromeos-wqbootimage Change-Id: I839447a9e7c7b6558b2d0877c67dc9cf89ee792a Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-05-07mb/google/mancomb: Update AMDFW config fileMartin Roth
Mancomb uses DDR4 SODIMMs, but the default cezanne configuration is for the LPDDR4 version. This changes to use SODIMMS. Further changes may be needed for platform customization, so I put the config file in variants/baseboard instead of the root mancomb directory. BUG=b:187094481 TEST=Build only Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Icc4dc8aec2053cb177765f57e57cac7a099508fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-06mb/google/mancomb: Implement tis_plat_irq_statusMartin Roth
This patch was implemented on Guybrush at CB:52352 BUG=b:185397933 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I141a504a827f37724fab0aaed7498fd543e471d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-06mb/google/mancomb: Update Kconfig with needed optionsMartin Roth
DISABLE_KEYBOARD_RESET_PIN - This pin goes to a test point and is not used for the reset. DRIVERS_UART_ACPI - Add the UART ACPI code FW_CONFIG - Mancomb uses the firmware config interface PSP_DISABLE_POSTCODES - The PSP is not yet initializing eSPI correctly to send post codes to the EC, so disable them for now. BUG=None Test=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I39efcc8d1e0fb1e7ac0b0541a49db0ac0ee56481 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-06mb/google/mancomb: Fix EC SCI configurationMartin Roth
This change fixes two problems: 1) We had the enum values for .direction and .level swapped. The naming is very confusing... 2) ESPI_SYS is not a good event to use for EC SCI. It is a level/low event that is only cleared by reading the eSPI status register 0x9C. Cezanne has added a new event source that directly exposes the SCI bit. This is the correct event source to use for EC SCI. This same patch was added for Guybrush at CB:52673 BUG=b:186045622, b:181139095 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iac86d2ef5bdd21fbb0a0d4e235efe4fe621023b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52948 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06mb/google/mancomb: Switch eSPI ALERT# to in-bandRaul E Rangel
This matches what we are doing on guybrush. BUG=b:187122344, b:186135022 TEST=build Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id61de28cd0ee762693b287b29bdd7605d4176929 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52956 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06mb/google/guybrush: Switch eSPI ALERT# to in-bandRaul E Rangel
Using the push-pull alert was causing leakages when in S0i3. This is because the EC drives ALERT#, so when the AP enters S0i3, the extra current leaks into the SoC and ends up turning on the power regulators. By using in-band ALERT#, the EC no longer drives this pin high, thus fixing the leak. We could also have used an open drain alert, but the rise time is less than ideal. BUG=b:187122344, b:186135022 TEST=Measure S0i3 power on guybrush and validate it's no longer high. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6de771aeda8feca062652f0ea9eb57d31cb68562 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-05-06soc/amd/common/espi,mb/: Allow configuring open drain ALERT#Raul E Rangel
Some designs might wish to use an open drain eSPI ALERT#. This change adds an enum that allows setting the eSPI alert mode. BUG=b:187122344, b:186135022 TEST=Boot guybrush using all 3 alert modes Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia35fc59a699cf9444b53aad5c9bb71aa27ce9251 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06mb/google/octopus: add audio codec into SSFC support for BloogTony Huang
BUG=b:186380809 BRANCH=octopus TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check whether device tree is updated correspondingly by disabling unselected one. Change-Id: I0975a8b64452c3f636e6c5937c6918518ec5b4e9 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2021-05-06soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias padsTim Wawrzynczak
TGL boards using the Type-C subsystem for USB Type-C ports without a retimer attached may require a DC bias on the aux lines for certain modes to work. This patch adds native coreboot support for programming the IOM to handle this DC bias via a simple devicetree setting. Previously a UPD was required to tell the FSP which GPIOs were used for the pullup and pulldown biases, but the API for this UPD was effectively undocumented. BUG=b:174116646 TEST=Verified on volteer2 that a Type-C flash drive is enumerated succesfully on all ports. Verified all major power flows (boot, reboot, powerdown and S0ix/suspend) still work as expected. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-05mb/google/dedede: Create pirika variantkirk_wang
Create the pirika variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:184157747 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_PIRIKA Signed-off-by: kirk_wang <kirk_wang@pegatron.corp-partner.google.com> Change-Id: I57bf33deeadacc88800f9ce1d3d54385ba56c798 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52626 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05mb/google/guybrush: Configure Pen Detect deviceKarthikeyan Ramasubramanian
Pen Detect GPIO is exported through GPIO keys driver to the kernel so that stylus tools is popped on pen eject event. Hence enable the GPIO keys driver and configure the devicetree. BUG=b:186011392 TEST=Build and boot to OS in guybrush. Ensure that PRP0001 device is added to the ACPI SSDT table. Ensure that the Pen Eject events are detected. Event: time 1620159356.243180, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: time 1620159356.243180, -------------- SYN_REPORT ------------ Event: time 1620159356.735316, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Ensure that when the device is suspended, it wake on Pen Eject event and does not wake on Pen Insert event. Change-Id: I4d2aa29c0f1839c563b40734527a687a5618ba5c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-05mb/google/guybrush: Fix S0i3/S3 GPIO configurationRaul E Rangel
Using PAD_WAKE is actually wrong. The wake bits are only supposed to be set when using the GPIO controller to wake the system. coreboot's current architecture relies on using GPEs to wake the system. BUG=b:186011392 TEST=Wake system from S0i3 with EC and see GPE 3 increment. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If7f9d2c13503c01fb9d834c436dac723f2c3b24c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-05nb/intel: Don't select VBOOT_SEPARATE_VERSTAGEArthur Heymans
Now the bootblock is not limited to 64K so integrating vboot into the bootblock reduces the binary size. Change-Id: Ic92ecf8068f327a893d20924685ce571752d379f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52787 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05mb/google/cherry: Add NOR-Flash supportRex-BC Chen
TEST=boot to romstage on MT8195 EVB Change-Id: I356e6b1cba3c078bf99e056b290476c7179e8ccf Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-05mb/google/cherry: Initialize pmif/spmi/pmic in romstageRex-BC Chen
Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I2eeddb44b5495d05602c995a6103a56b09cf126a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-05mb/google/puff/var/dooly: enable touchscreen wakeupTony Huang
Configure GPP_A20 as PAD_CFG_GPI_IRQ_WAKE to enable interrupt and wake routes for touchscreen device. BUG=b:186070097 BRANCH=puff TEST=Build and make sure TS works to wakeup suspend/resume. Change-Id: I2bbaab56924849a22a4d05ce53bf5bdcf00265dd Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-04mb/google/dedede/var/cret: Modify reset setting for touchscreenDtrain Hsu
Modify reset pin setting to ACPI_GPIO_OUTPUT_ACTIVE_LOW for ELAN and Weida touchscreen. BUG=b:180547621 BRANCH=dedede TEST=Build the cret board and touchscreen is workable. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I912fe8a0e18a4c3527fb8587592b855c93b12406 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-04mb/google/zork/vilboz: Disable HDMI 2.0 for VilbozFrank Wu
Disable HDMI 2.0 for Vilboz and then support display resolution 4K 30Hz BUG=b:179170193 BRANCH=firmware-zork-13434.B TEST=verified that the resolution of the display is 4K 30Hz Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ib0dc0d584f0e87bc9c3da85a583cb8c8bed76440 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-05-03mb/google/mancomb: Fix S0i3/S3 GPIO configurationRaul E Rangel
Using PAD_WAKE is actually wrong. The wake bits are only supposed to be set when using the GPIO controller to wake the system. coreboot's current architecture relies on using GPEs to wake the system. BUG=b:186011392 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib956fc299fe21cd7ea0b465cbdc5c8da830a668d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-05-02mb/google/dedede/var/magolor: Support VBT for MagisterDavid Wu
Default VBT supports only integrated Display port. Magister supports a HDMI port and hence support a separate VBT for Magister. BUG=b:180666608 BRANCH=dedede TEST=Build and boot to OS. Cq-Depend: chrome-internal:3661227 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I52c10452887312959f68cfc4e25d5897dae388f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51279 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-30mb/google/brya: select GOOGLE_SMBIOS_MAINBOARD_VERSIONZhuohao Lee
Select GOOGLE_SMBIOS_MAINBOARD_VERSION allows querying board revision from the EC. BUG=b:186721096 TEST=1. emerge-brya coreboot chromeos-bootimage 2. flash the image to the device and check board rev by using command `dmidecode -t 1 | grep Version` Change-Id: I8eeb958f73607afb801794f91fbf91ec7bd5cd8b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-30mb/google/mancomb: Add SPI configuration to KconfigMartin Roth
Mancomb will have the boot flash on a daughterboard, so the SPI speeds need to be low for now. BUG=b:182211161 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Icacb68d65fb414197d7b8d45799527d8d2568dc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-30mb/google/guybrush: Remove the GPIO_SIGN_OF_LIFE codeMartin Roth
Guybrush is pretty definitely alive, so this can be removed, as the TODO line said. BUG=180721202 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I14f89f3e6f780c2da2136a838950ef2bcebc4c3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-30mb/google/mancomb: Remove lid swtichIvy Jian
There is no lid switch in mancomb so remove it. Will replace the lid switch with a fake gpio in depthcharge. BUG=b:182211161 TEST=Depthcharge no longer halts complaining that coreboot didn't sample the pin Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Ifd0fcec9557bf7ebad64ce9342d3b50eb511522b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-30soc/amd/common: Move external oscillator config away from commonKarthikeyan Ramasubramanian
The usage of external oscillator has got nothing to do with Audio Co-processor (ACP). Hence move it out of common config and put it into the SoC config where it is being used. BUG=None TEST=Build Dalboz and Vilboz mainboards. Change-Id: I8c5d98addfba750f9ddb87a846599541b4a8340a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-30mb/google/guybrush: update the telemetry settingChris Wang
Update the telemetry setting for guybrush vddcrvddfull_scale_current : 92165 #mA ddcrvddoffset : 412 vddcrsocfull_scale_current : 30233 #mA vddcrsocoffset : 457 BUG=b:182754399 TEST=Build, boot to guybrush Change-Id: Ib92bb169693634665fc8e165837e7ae3e6137bcf Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52736 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-30mb/google/mancomb: Add STAPM values to overridetreeChris Wang
Follow the FP6 IRM(#56328) to set the stapm parameter and allow other mancomb variants boards can customize those parameters. BUG=b:1181157669 TEST=build. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ib3ed76e5212a5a8b5fb4fcc3d6884ceff82377b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-30mb/google: Move ECFW_RW setting for non-ChromeEC boardsKyösti Mälkki
The boolean is stored in ChromeOS NVS, not GNVS. Change-Id: I5c424a052d484228a456f8f0ad4fb0bed3165e09 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-30mb/google/dedede/var/galith: Support Wifi SAR for DVT phaseFrankChu
Because galith/gallop both non-suport tablet mode, remove un-use fw_config conditional. BUG=b:176206495 TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ic9bb76c207ef033f81ecdd57849535b8ac8d13ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/52565 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-30mb/google/brya: Add CHROMEOS_DRAM_PART_NUMBER_IN_CBIEric Lai
Brya uses CBI to store dram part number. So enable the config. BUG=b:186571840 BRANCH=none TEST=dmidecode -t 17 can show the dram part number. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1b4fc4da31d8964763c3e671d84be71996fa5e2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-29mb/google/volteer/variants/copano: Modify touchpad I2C sequenceHao Chou
Modify touchpad I2C sequence to meet requirement. BUG=b:186372071 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot chromeos-bootimage build Pass And check the touchpad I2C5 sequence by EE. Change-Id: I9d4dcc764edfbdc14eef5ad82db20e40b31de295 Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52690 Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-29mb/google/volteer/variant/lindar: Modify ELAN touch screen IRQ trigger methodKevin Chang
According to SED team provided ELAN touch screen SPEC. IRQ trigger method need set with level trigger, that modify IRQ trigger to level from edge. BUG=b:174972088 TEST=Build FW and boot to OS and check with test result. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I9237d9aad6166a5754afe464ce8453129a58d283 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-29mb/google/guybrush,mancomb: only print warning in mainboard_smi_gpiFelix Held
guybrush and mancomb don't configure any GPIO as PAD_SMI. Since mainboard_smi_gpi will only get called for a GEVENT that will cause a non-SCI SMI, this isn't expected to be called. For the unexpected and very unlikely case that it still does get called, put a printk into mainboard_smi_gpi to see what is happening there. TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd6e3348ecc078932bf6cf5b0830b4b034d274bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/52360 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-29mb/google/zork/smihandler: only print warning in mainboard_smi_gpiFelix Held
zork doesn't configure any GPIO as PAD_SMI. Since mainboard_smi_gpi will only get called for a GEVENT that will cause a non-SCI SMI, this isn't expected to be called. For the unexpected and very unlikely case that it still does get called, put a printk into mainboard_smi_gpi to see what is happening there. TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I14c67b21a83b334558cdd54ebf700924aa9d0808 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52359 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-29mb/google/guybrush: Configure Audio Co-processorKarthikeyan Ramasubramanian
Configure Audio Co-processor(ACP) to operate in I2S TDM mode. Also fix the scope in which ACP is defined in the devicetree. BUG=b:182960979 TEST=Build and boot to OS in Guybrush. Ensure that the ACPD device is enabled in the appropriate scope in SSDT. Change-Id: Ic90fd82e5c34a9feb9a80c4538a45e7c2fb91add Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-29soc/amd/common/acp: Move Audio Co-processor driver to commonKarthikeyan Ramasubramanian
Audio Co-processor driver is similar for both Picasso and Cezanne SoCs. Hence move it to the common location. BUG=None. TEST=Builds Dalboz, Trembyle, Vilboz, Mandolin and Bilby mainboards. Change-Id: I91470ff68d1c183df9a2927d71b03371b535186a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-29mb/google/guybrush: Set system_config to 2 for guybrush boardsMartin Roth
All guybrush boards should have system_configuration set to 2, so put this in the main devicetree. BUG=b:185209734 TEST=Build & Boot guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I1ce2acb3b4ed51aa9a0aa379ed125f0b04f04d31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: chris wang <Chris.Wang@amd.com>
2021-04-29mb/google/asurada: Fix power on delayYu-Ping Wu
From ANX7625 spec, the delay between powering on power supplies and GPIO should be larger than 10ms. Since it takes about 4ms for the previous GPIO EN_PP3300_EDP_DX to be pulled up, increase the delay from 2ms to 14ms. BUG=b:157716104 TEST=emerge-asurada coreboot BRANCH=asurada Change-Id: If73747bdaec5ac069b048920d27e27178bc3cedc Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-04-29mb/google/brya: Enable ELAN9050 touchscreenEric Lai
Enable ELAN9050 touch screen. Follow below spec: eKTH7913U_eKTH7915U_eKTH7918U_Product Spec_V1.0_20200807 IPM-11 BUG=b:186342801 TEST=touchscreen is functional in the OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I4c247fae33b9178c8706552aba2f950c9a674ecc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-29mb/google/brya: Adjust WWAN power sequenceEric Lai
Follow L850GL spec to adjust power sequence. RST need to drive low before power on then drive to high. SPEC:FIBOCOM_L850-GL Hardware User Manual_V1.0.8 BUG=b:186374631 TEST=WWAN is detected by lsusb. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I13357677bb1ab185abf1d4c915a762a9d6894312 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-28mb/google/volteer: Add EC_HOST_EVENT_USB_MUXJohn Zhao
This changes adds the EC_HOST_EVENT_USB_MUX to be dark resume source. BUG=b:183140386 TEST=In S0ix, remove DP dongle, system does dark resume. AP and EC synchronized. AP got port partner disconnection. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I53bd4fee21e2e2d1f16f558ab0341a50ef9a0e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52716 Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28mb/google/dedede/var/metaknight: Define stop_gpio for goodix touch screenDavid Wu
Define TOUCH_RPT_EN pin(GPP_A11) as the stop_gpio for the touch screen and control TOUCH_RPT_EN pin to keep low. BUG=b:176253069 TEST=Build and boot metaknight to OS, confirm GPP_A11 pin keep low. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I816e29eccac0f1935aeaa3b94c907870e2451e3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52653 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28mb/google/brya: remove WLAN PCIE settingEric Lai
Brya uses CNVi WiFi module, PCIE setting is not required. TEST=WiFi is functional in the OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib82c98905ed3b30075e9830c1a2638817f140abe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-27mb/google/guybrush: Fix EC SCI configurationRaul E Rangel
This change fixes two problems: 1) We had the enum values for .direction and .level swapped. The naming is very confusing... 2) ESPI_SYS is not a good event to use for EC SCI. It is a level/low event that is only cleared by reading the eSPI status register 0x9C. Cezanne has added a new event source that directly exposes the SCI bit. This is the correct event source to use for EC SCI. BUG=b:186045622, b:181139095 TEST=`lpc sci` on EC console and see /proc/interrupts increase by 1 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I764b9ec202376d5124331a320767cbf79371dc07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-26mb/google/volteer/variant/lindar: Disable acoustic mitigationKevin Chang
Roll back CPU slow slew rate setting to Intel default "SLEW_FAST_2" Because baseboard modify slow slew rate setting to "SLEW_FASE_8" for all project, but Lindar and Lillipup is using "SLEW_FAST_2", so this setting need to roll back. BUG=b:186140230 TEST=Build FW and boot to OS checking with CPU log. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I7de252b26c75f8dad218f3eb79a0988e60964f4c Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52620 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26mb/google/guybrush: Add STAPM values to overridetreeMartin Roth
This enables STAPM power management. Values follow the AMD specification. BUG=b:185209734 TEST=Build & Boot guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ib9f2ec9a8ac118c55ae53b9419ea4ff74ce7b599 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: chris wang <Chris.Wang@amd.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-26mb/google/mancomb: Add mancomb APCBs into buildIvy Jian
This adds the Mancomb APCBs into the AMD firmware binary. BUG=b:182211161 TEST=Build and check log showing APCB sources present. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Ifdf1e813fce6f93378c2495cf76bdace81d87c16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52600 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26mb/google/mancomb: PCIe GPIOs - enable enables, disable resetsIvy Jian
To train PCIe devices, the devices need to be enabled and taken out of reset. This patch does the bare minimum needed to train PCIe. It is not intended to handle timings, which will be addressed later. Copy the enables for WLAN into early GPIO Init so that they're enabled before FSP-M runs and trains the PCIe busses. Again, this patch is the minimum to let the FSP train the PCIe busses. BUG=b:182202136 TEST=Boot guybrush from NVME. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I5e3e9fe21f44b832e26b0942759ae2ec96ec6c82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-26mb/google/volteer/variant/lindar: Create dynamic fan table mechanismKevin Chang
Add dynamic fan table mechanism for Lindar and Lillipup. Create different fan tables that provided from thermal team. BUG=b:185308432 TEST=Build FW and boot to OS modify CBI test with DPTF tool. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I1b79dbe1ae6ee7aa41cef832b4ee305cc8f4b753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-04-26mb/google/guybrush: Enable S0i3Karthikeyan Ramasubramanian
BUG=b:185939089 TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the sleep state configuration from the mainboard. Change-Id: I4b23b014ca45bd09c76b626b73b0332586dec056 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-26mb/google/brya: Enable GL9755 SD card readerEric Lai
Enable GL9755 SD card reader. BUG=b:185397257 TEST=SD card is functional in the OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib3be54274ca796bedda76ce807a0bd630d1d8e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-23mb/google/dedede/var/storo: Modify eeprom setting for MIPI cameraTao Xia
Currently, it fails to dump the nvme data by test command. It reports the following error: cat: '/sys/bus/i2c/devices/i2c-PRP0001:01/eeprom': Connection timed out So increase the value from 0x0400 to 0x2000 and double the address width from 0x08 to 0x10 to solve this problem. BUG=b:177393430 TEST=1. cat /sys/bus/i2c/devices/i2c-PRP0001:01/eeprom > /tmp/ov8856_eeprom.bin 2. hexdump -C /tmp/ov8856_eeprom.bin > ov8856_eeprom_dump.log 3. cat ov8856_eeprom_dump.log Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ia933927981f07e0f7954a4bc6d82f0bdd70181f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52048 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: ShawnX Tu <shawnx.tu@intel.com> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23mb/google/guybrush: Update memory configurationMartin Roth
The next guybrush build uses 2 new LPDDR4X memory chips: - Micro MT53E1G32D2NP-046 WT:B - Hynix H9HCNNNBKMMLXR-NEE The MT53E2G32D4NQ-046 WT:A chip has been added to the global LPDDR4X list since the last time guybrush was updated, so that's brought into the guybrush SPD directory as lp4x-spd-10.hex, but it's not used. BUG=b:186027256 TEST=Build only Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ia5efd548f8b9442fb3703518387175aba8933a33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-23mb/google/octopus/var/fleex: Add ssfc codec cs42l42 supportEric Lai
Add cs42l42 codec support in fleex. BUG=b:184103445 TEST=boot to check cs42l42 is functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1571003f8b272a573e6ab9fb525f17659bae8c4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-22mb/google/brya: Enable display and DSP audio UPDSugnan Prabhu S
This patch includes changes to enable display and DSP audio UPD. BUG=b:181219097,b:183482000 TEST=Audio sound card is detected and listed by the linux kernel. Audio playback and capture is working on the Brya. Change-Id: I3dab02bedb6df995b1efd27332d3aa26985e188e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-22mb/google/dedede/var/magolor: Select camera module based on SSFC valueSugnan Prabhu S
This patch has changes to support multiple cameras modules, based on the value set in the SSFC_CONFIG. BUG=b:176065425 TEST=Tested the changes with magolor 5MP and 8MP camera. Change-Id: I764abf70bacbe61452e7b0fd59c1b375227b5748 Signed-off-by: Shawn Tu <shawnx.tu@intel.com> Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-22guybrush: Increase eSPI bus frequency to 33MhzRob Barnes
Change eSPI bus frequency to 33Mhz. BUG=b:184356693, b:185514521 TEST=Boot guybrush, observe no eSPI bus errors Change-Id: Ie2c1b256531f5c7354600e35e9e5191567197feb Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52402 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22guybrush: Add Kconfig for PSP eSPI and port80Rob Barnes
Add PSP_DISABLE_POSTCODES and PSP_POSTCODES_ON_ESPI kconfig options for cezanne. Select PSP_DISABLE_DISABLE_POSTCODES and unselect PSP_POSTCODES_ON_ESPI for guybrush. Port80 codes from PSP can cause bus errors on guybrush. BUG=b:185514903, b:184356693 TEST=Boot guybrush, observe no port80 codes from PSP Change-Id: I7241e47ec1b89782e699135370c796eb251afcaa Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52401 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22soc/intel/cannonlake: Set DIMM_SPD_SIZE to 512Felix Singer
All related mainboards are setting DIMM_SPD_SIZE to 512. Therefore, default to 512 in the SoC Kconfig and drop it from related mainboard Kconfigs. Change-Id: Idb6a0e42961eeb490afd76b4aa7d940961991733 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52513 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21mb/google/volteer/variants/drobit: Update DPTF parametersWayne3 Wang
Update the DPTF parameters. Modify TDP, Critical Policy and Active Policy setting. BUG=b:177777472 BRANCH=firmware-volteer-13672.B TEST=build test firmware and verified by thermal team. Change-Id: Ib57de5535f3d37765ac7051c17445c311c098927 Signed-off-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-21ChromeOS: Use CHROMEOS_NVS guardKyösti Mälkki
Replace CONFIG(CHROMEOS) with CONFIG(CHROMEOS_NVS) for cases where the conditional and dependency are clearly about the presence of an ACPI NVS table specified by vendorcode. For couple locations also CONFIG(HAVE_ACPI_TABLES) changes to CONFIG(CHROMEOS_NVS). This also helps find some of the CONFIG(CHROMEOS) cases that might be more FMAP and VPD related and not about ChromeOS per-se, as suggested by followup works. Change-Id: Ife888ae43093949bb2d3e397565033037396f434 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21mb/google/volteer/variants/copano: Modify touch controller power sequenceHao Chou
Based on the measurement, adjust the delay time between the main power rail and reset signal to 7ms in order to match the spec. of touch controller, eKTH7918U. BUG=b:184126265 BRANCH=firmware-volteer-13672.B TEST=build test firmware and verified by EE team. Change-Id: Iea84046c1b1f3fe6ab8bb89d86d00b1e89325f71 Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-21mb/google/volteer/variants/copano: Fix pen ejection eventHao Chou
Modify PENH device GPIO GPP_E17 for pen ejection event. BUG=b:182867209 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot, check evtest if SW_PEN_INSERTED event (value:1/0) when insert/eject pen, and eject pen to wake system from s0ix Change-Id: I1b13d09ed6d065779de9441f2137dcf6559b8f27 Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52494 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul2 Huang <paul2_huang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21mb/google/dedede/var/sasuke: Update DPTF parametersSeunghwan Kim
Add control charging current from TSR0 and correct charger_perf table value. BUG=b:179067801 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: Ie0d969898defe76952e5c136fa93b7edffe51de3 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Edward Doan <edoan@google.com>
2021-04-21mb/google/*: allow LAN MAC to be read from VPD w/o ChromeOSMatt DeVillier
Condition use of RO_VPD for LAN MAC address on CONFIG_VPD rather than CONFIG_CHROMEOS. Test: build/boot google/{beltino,jecht} with RO_VPD propagated from stock firmware, verify MAC address set correctly. Change-Id: I1606fe1936ccee6e03dee145901767c8e73bfe2d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52517 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21mb/google/dedede/metaknight: Add device list and probe daughter-boardDavid Wu
Metaknight has two daughter-board (DB_PORTS_1A_HDMI and DB_PORTS_LTE_HDMI), LTE and USB Type A use the same usb port,so needs to probe daughter-board to avoid USB device cannot recognize correctly. BUG=b:184809456 TEST=build and verify USB device can recognize correctly Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie42d12c7ce5c7341751c3cf92b5f37b6cd4d479f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52369 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raymond Wong <wongraymond@google.com> Reviewed-by: Kaiyen Chang <kaiyen.chang@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19Revert "mb/google/mancomb: Enable early EC Software Sync"Karthikeyan Ramasubramanian
This reverts commit 800193414148d5f39be42110fc2c76ad1ceb7d2f. EC software sync needs to be enabled in payload once the EFS2 requirements are met. BUG=b:185277224 TEST=Build. Cq-Depend: chromium:2829948 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ib22a89e221e1e057d82ef76b7008e5d3f14df5e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52451 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19Revert "mb/google/guybrush: Enable early EC Software Sync"Karthikeyan Ramasubramanian
This reverts commit 1e36dc078e4012f884d67a32f1faac5f80406285. With EFS2 already enabled in EC, enabling early EC sync is not required. Also a workaround has been added in payload to address any boot issues. BUG=b:185277224 TEST=Build and boot to OS in Guybrush in both normal and recovery mode. Cq-Depend: chromium:2832032 Change-Id: I921dc5c814e5187dce283eeff43075b59885723a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52418 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/hatch: Guard ChromeOS fmd selection on CHROMEOSMatt DeVillier
Ensure the ChromeOS FMAPs are used only when CONFIG_CHROMEOS is selected, so non-ChromeOS targets use the default x86 FMAP. Change-Id: Id5d3e7a44973f2fadba3ea15e0e544eee7fa53e6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18mb/google/mancomb: Remove PS/2 mouse configEric Lai
Sync from guybrush. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I02b375b6fc134e56b7f55e1421f694daa4aa994d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52407 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/guybrush/var/guybrush: Add GPIO override tableKarthikeyan Ramasubramanian
EN_SPKR is routed to SD pin in the ALC1019 speaker amplifier. The concerned pin has a voltage rating of 1.8V whereas the EN_SPKR GPIO has a voltage rating of 3.3 V. The schematics has been updated to bridge the gap. So enable the speaker amplifier by default and add a gpio override table to disable the speakers before board version 2. Also update the codec ACPI HID name for the kernel machine driver to probe the codec successfully. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the GPIO output state is high. Change-Id: I32b29bfae9bc94b5119b33a535d8bc825ef89445 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52355 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/guybrush: Enable AMD I2S Machine DriverKarthikeyan Ramasubramanian
Enable AMD I2S machine driver and configure the devicetree with HID information so that the machine driver ACPI objects can be passed to the kernel. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the ACPI objects for machine driver is populated. Change-Id: I8ed474d25273082d1e0742ba93746d97930deb19 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-18soc/intel/cnl and mainboards: Drop `cnl_configure_pads()`Furquan Shaikh
CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is done") introduced a workaround in coreboot for `soc/intel/cannonlake` platforms to save and restore GPIO configuration performed by mainboard across call to FSP Silicon Init (FSP-S). This workaround was required because FSP-S was configuring GPIOs differently than mainboard resulting in boot and runtime issues because of misconfigured GPIOs. This issue has since been fixed in FSP (verified with FSP v1263 on hatch). However, there were still 4 boards in coreboot using `cnl_configure_pads()`. As part of RFC CB:50829, librem_cnl, clevo/cml-u and system76/lemp9 were tested to ensure that this workaround is no longer required. This change drops the workaround using `cnl_configure_pads()` and updates all mainboards to use `gpio_configure_pads()` instead. Signed-off-by: Furquan Shaikh <furquan@google.com> Tested-by: Angel Pons <th3fanbus@gmail.com> (Tested purism/librem_cnl) Tested-by: Michael Niewöhner <foss@mniewoehner.de> (Tested clevo/cml-u which is similar to system76/lemp9) Change-Id: I7a4facbf23fc81707cb111859600e641fde34fc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52248 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/guybrush/var/guybrush: Add FPMCU configrationIvy Jian
Enable CRFP in devicetree and configure GPIOs. BUG=b:182201937 BRANCH=None TEST=Boot into OS and confirm FPMCU is responding. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-16mb/google/guybrush: Enable backlight in the OSMartin Roth
Add ACPI code to enable the backlight when we enter the OS. BUG=b:184198808 TEST=Backlight enabled in the OS Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I3e0a6c06120ac5abf0a0d82494e03d9cf80c1f8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52113 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16mb/google/zork: Configure HID over I2C related GPIO as level-triggeredVictor Ding
Both touchpads supported by zork use level-triggered wakeup signal. BRANCH=zork BUG=b:172846122,b:182911201 TEST=1. cros build-ap -b zork 2. both Synaptics and ELAN touchpads work fine on Vilboz 3. Wakeup source is correctly reported on Vilboz Signed-off-by: Victor Ding <victording@google.com> Change-Id: Icc2b5ad3bd434c9759a0fdfc121aa3c94f46630e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52367 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16mb/google/zork: Configure IRQs as level triggered for ELAN touchpadVictor Ding
Based on the datasheet provided by ELAN, the /INT pin is "low active" and "indicates touchpad likes to send data to system(host) when low". The signal is level-triggered. BRANCH=zork BUG=b:172846122 TEST=cros build-ap -b zork Signed-off-by: Victor Ding <victording@google.com> Change-Id: I1f2182aaf483932304591ab14592f35214ea6efd Reviewed-on: https://review.coreboot.org/c/coreboot/+/52366 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16mb/google/dedede/var/galith: support Audio AMP I2C/Auto modeFrankChu
support audio AMP selection with fw_config. BUG=b:185082705 BRANCH=dedede TEST=build pass Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ieb169c69a6716082dd218d05479bca46bbc09a3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-16mb/google/dedede: Add AUDIO_AMP FW_CONFIG in devicetreeFrankChu
Add AUDIO_AMP ports bit field in devicetree. UNPROVISIONED 0 MAX98360 1 RT1015_I2C 2 RT1015P_AUTO 3 BUG=b:185082705 BRANCH=dedede TEST=build pass Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I54f1e44036857dc00df074c38fde0fa82e589320 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52317 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16mb/google/dedede/var/storo:Add P-sensor for storoZanxi Chen
Modify GPIO_D22/D23/E11 configuration for P-sensor BUG=b:185214363 BRANCH=dedede TEST=built storo firmware and verified P-sensor function Change-Id: Ia2df1a227b04688a6b98384cd3a4e63023c0c1d9 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 16:37:56 +0000