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This change updates _v3 version of romstage and wifi GPIO tables to
match v3 schematics.
BUG=b:157088093, b:154676993, b:157098434
TEST=Compiles
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic605559b3226e2ad9b5b3f3fa45c4aa9f9b5fe22
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251391
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42722
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change updates variant_romstage_gpio_table() and
variant_wifi_romstage_gpio_table() to support v3 version of schematics
for dalboz and trembyle reference designs. gpio_set_stage_rom and
gpio_set_wifi are divided into two groups:
a) Pre-v3 (GPIO table for pre v3 schematics):
* gpio_set_stage_rom_pre_v3
* gpio_set_wifi_pre_v3
b) v3 (GPIO table for v3+ schematics):
* gpio_set_stage_v3
* gpio_set_wifi_v3
Currently, both _v3 is a copy of _pre_v3, but will be updated in
follow-up CLs to make it easier to identify what changed from _pre_v3
to _v3.
BUG=b:157088093, b:154676993, b:157098434, b:157165628, b:157744136, b:157743835
TEST=Compiles
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I444875d93100c2f2abdb6dec4312861fd89d9b78
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251390
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42721
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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RAM_ID GPIOs are configured by ABL based on the information added to
APCB. coreboot does not need to configure these pads. This change
drops the RAM_ID configuration from trembyle baseboard. Dalboz never
really configured RAM_IDs in coreboot.
BUG=b:154351731
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie1dfcc3c185304d917ab4386920445ba0119ac69
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252710
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change moves the GPIOs that need to be configured for early
access in coreboot to early_gpio_table[] in
gpio_baseboard_common.c. These GPIOs include:
* Pads to talk to EC
* Pads to talk to TPM
* Pads to talk to serial console
These should be configured in the first stage that runs coreboot
i.e. in case of VBOOT_STARTS_BEFORE_BOOTBLOCK, it should be done as
part of verstage (which starts on PSP), else it should be done as part
of bootblock (which is the first stage that runs on x86).
This change drops GPIO_137 from early_gpio_table since that is not
really required in early stages.
BUG=b:154351731
TEST=Verified that trembyle still boots.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ifbdbb02cbfc65ddb68f0ae75cf4b1f2ea1656b91
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252709
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable DPTF functionality on jasperlake based dedede platform
BRANCH=None
BUG=None
TEST=Built for dedede system
Change-Id: I17b6e4e96abee6181b0d1f94c356a32aa82c19b9
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41668
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add UPD xhci0_force_gen1 for Trembyle and Ezkinil.
The default setting is set to disable, and set enabled for Ezkinil.
Trambyle -> set default as disable.
Ezkinil -> set enable by request.
BUG=b:156314787
BRANCH=trembyle-bringup
TEST=Build. Verified the setting will be applied on Ezkinil/Trembyle.
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: I65d06bfe379f9e42101bfae1a02a619ee2f24052
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2216090
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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1) Based on malefor schematics, disable unused I2C port, USB port, TBT
PCIe
2) Add audio device to the tree
BUG=b:150653745, b:154973095
TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage
Boot to kernel and check the devices' function worked properly.
Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com>
Change-Id: I9ce465705e8b8f67ddbc9e4eb06c5a8bfac65fcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42246
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the volteer2 variant of the volteer reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
Modified to alphabetize and update to duplicate latest volteer changes
currently in the review and merge pipeline.
Added the following missing files from the variants/volteer2/ folder:
- gpio.c
- include/variant/acpi/dptf.asl
- acpi/mipi_camera.asl
- Makefile.inc
- memory/dram_id.generated.txt
- memory/Makefile.inc
- memory/mem_list_variant.txt
- overridetree.cb
BUG=b:159135047
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_VOLTEER2
Change-Id: I987c72b83dc993af248a753a2caa56be0f26c1ad
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42605
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These are the simple cbmem_find() cases. Also drop the redundant
error messages.
Change-Id: I78e5445eb09c322ff94fe4f65345eb2997bd10ef
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Create the delbin variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:158797761
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_DELBIN
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Change-Id: Icf5fc6b9cc6a7c47e52103b2d396bcddb26adf50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Create the wyvern variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:158269582
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_WYVERN
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Id7a090058d2926707495387f7e90b3b8ed83dac7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42551
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the faffy variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
V.2: Manually modified to keep Kconfig sorted.
BUG=b:157448038
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_FAFFY
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: I5f14c2d6144ce3c2e48488ca81f31b3c04dc5fb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42717
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds support for fingerprint device in overridetree for
the following variants:
1. berknip
2. morphius
3. trembyle
Generates the following node in SSDT1:
Scope (\_SB.FUR1)
{
Device (CRFP)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_DDN, "Fingerprint Reader") // _DDN: DOS Device Name
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
UartSerialBusV2 (0x002DC6C0, DataBitsEight, StopBitsOne,
0x00, LittleEndian, ParityTypeNone, FlowControlNone,
0x0040, 0x0040, "\\_SB.FUR1",
0x00, ResourceConsumer, , Exclusive,
)
GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault, 0x0000,
"\\_SB.GPIO", 0x00, ResourceConsumer, ,
)
{ // Pin list
0x0006
}
})
Name (_S0W, 0x04) // _S0W: S0 Device Wake State
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x0A,
0x03
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x01)
{
Package (0x02)
{
"compatible",
"google,cros-ec-uart"
}
}
})
}
}
BUG=b:147853944
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7ccb3633332ce3e388293872af7b22f1867c8465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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There are two touch screen controllers on the Palkia device.
One is on the lid; another is on the base. To support
the different control path (for example: turning off the base's
touch event when we don't want to use it however still keeping
the lid's touch event), we use the different gpio pins to control
the second touch. As a result, we need to modify the devicetree
to adopt this change. With this change, we can control the
primary and secondary touch screen controller respectively.
BUG=b:149714955
TEST=lid/base touch screen works correctly
Change-Id: I1f896e334e51c78300af724cbef8d57641ae5612
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Here we consolidate some of the mainboard.c duplication between
Puff and it's variants.
Customizations can be done later via introducing a devicetree
parameterisation.
BUG=b:154071868
BRANCH=none
TEST=none
Change-Id: I75c2de7ae8efd544d800bc77e34e667c3afa4b01
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42672
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable CmdMirror for Terrador to achieve optimum routing from SoC to
DRAMs
BUG=b:156435028
BRANCH=none
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I0db9fff0dddf35c99a6cb2a90d40886ed8e18686
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Remove an unneccessary comment and group the variant_early_gpio_table
together based on GPIO group.
Changed static variable name gpio_table to override_gpio_table to be
more descriptive.
BUG=none
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer to kernel.
Change-Id: Iabe810df1e5a3df35e3543ab81b9fdb6f76c223a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42577
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move the following volteer-specific devices from baseboard's
devicetree.cb into volteer's overridetree.cb file:
- Goodix Touchscreen
- ELAN Touchscreen
- ELAN Touchpad
- SAR0 Proximity Sensor
Adjust the other variant's overridetree.cb files to correspond to
the changes made to the baseboard's devicetree.cb in this change.
BUG=b:159241303, b:154646959
TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot
volteer to kernel and verify that the trackpad works.
Change-Id: I30f8266ec87a7cde293c84d3e687d133207b8d59
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Update fw_config definition in devicetree.cb to match current
definition for volteer.
BUG=b:159157584
TEST=none
Change-Id: I761893818231880d86fd13cfa61319157d06a7d5
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42331
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The pass through mode (SW CM) RTD3 is not supported until QS platform.
D3Cold is needed to be disabled along with upstream TBT firmware
signed_TGL_HR_4C_A0_rev6_pre4_SW_CM_PM_support_ENG_VER_perst_check_fix.
This temporary patch will need to be reverted once PM RTD3 support is
validated on QS platform.
BUG=b:159050315
TEST=Verfiy PM S0ix along with upstream TBT firmware.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I98ed991e4185abf1f3168e33b099e0e97c9075f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42504
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Using guidance from Intel, a new set of power limits (PL1, PL2 & PL4)
are available for TGL-U. They are dependent upon the SKU of the CPU
that the mainboard is running on. Volteer is updated here to use these
new limits.
To accomplish this, the SoC chip config's power_limits_config member
was expanded to an array, which can be indexed by POWER_LIMITS_*_CORE
macros. Just before power limits are applied, the correct set of them
is chosen from the array based on System Agent PCI ID. Therefore, a
TGL board should have two sets of power limits available in the
devicetree.
BUG=b:152639350
TEST=On a Volteer SKU4 (4-core), verified the following console output:
CPU PL1 = 15 Watts
CPU PL2 = 60 Watts
CPU PL4 = 105 Watts
Change-Id: I18a66fc3aacbb3ab594b2e3d6e2a4ad84c10d8f0
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Support 4GB H9HCNNNCPMMLXR-NEE discrete DDR bootup.
BUG=b:156691665
BRANCH=none
TEST=Boots correctly and stress test passes on Kukui.
test cmd: memtester 1000M
Change-Id: I0b29cc1cf0d51eb9d6af112858563193ffa88652
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42502
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TGL RVP and Volteer use ov8856 camera module from different vendors.
TGL RVP from Foxlink and Volteer from Sunny. ov8856 sensor is identical
for the two modules but VCM and EEPROM are different. Originally,
Volteer ACPI was set to align with Sunny module, GT9679. But it turned
out GT9679 is compatible with Foxlink's DW9768. So Volteer camera ACPI
configuration doesn't need to keep GT9679.
BUG=b:158188369
BRANCH=none
TEST=Build and boot volteer proto 2 board. Start a camera app
and check user-facing camera functionalities.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: I792608f86a59b16545dfa4edf6508de7a444bb26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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In waddledee and waddledoo, discrete & integrated BT signals are routed to
different USB ports. In all the other variant boards, discrete &
integrated BT signals are routed to the same USB port (port 8 - index 7).
Re-configure the USB devices accordingly.
Also device configuration in override tree are applied only if there is a
matching device in base devicetree. So configure all the USB devices in
base devicetree and turn them off.
BUG=b:154064148
TEST=Ensure that the SSDT contains the ACPI objects for enabled USB
devices.
Change-Id: I1b8bf7f4db1d2661f310bf4874428a6d1de222c6
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42554
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add DW9768 VCM device and add its entry in the OV8856's _DSD
to allow the V4L2 driver to use the VCM functionality.
Also add ACPI entries for AT24 NVM device, this will enumerated
as a generic NVM device and not part of the V4L2 framework.
BUG=b:155285666
BRANCH=None
TEST=Build and able to see DW9768 and AT24 getting listed I2C3 lanes
and able to capture image using world facing camera.
Change-Id: I19e4a4107c5bc9d96f718d654df50e2705b98c03
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Ie9635e10dffe2f5fbef7cfbd556c3152dee58ccc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Fix Puff and its variants to not shutdown the AP before the cr50 reboot.
This is the same approach that Sarien do to remain on during a cr50
cycle.
BUG=b:154071064
BRANCH=none
TEST=none
Change-Id: I5f92b4f769654b67c10c91e4cc7b2bce785e302f
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42497
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Here we consolidate some of the dptf.asl duplication between
Puff and it's variants. Customizations can be done later
either as a direct copy or preferably via introducing a #define.
BUG=b:154071868
BRANCH=none
TEST=none
Change-Id: I35fa1e152adb5f04fb6ef1bd2448376cf9f37980
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
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Here we consolidate some of the ec.h duplication between
Puff and it's variants.
BUG=b:154071868
BRANCH=none
TEST=none
Change-Id: I13dfe09da5c7a19677b156063bb51a58bc059b93
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
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Commit 0148fcb4 [Combine Broadwell Chromeboxes using variant board scheme]
incorrectly flipped the mic pin configs for verb NIDs 0x18 and 0x19,
so set them back to the correct values, which match the original
Chromium sources (where the NID identifiers in the pin config comments
were reversed, which was the source of the confusion originally.
Test: build/boot guado variant, verify mic attached to 3.5mm jack functional
Change-Id: I65b813c8f801303682762ce5a7446e07af117b9f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42518
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit 0558d0c [mb/google/beltino/**/hda_verb.c: Correct pin configs]
incorrectly flipped the mic pin configs for verb NIDs 0x18 and 0x19,
so set them back to the correct values, which match the original
Chromium sources (where the NID identifiers in the pin config comments
were reversed, which was the source of the confusion originally.
Test: build/boot panther and zako variants, verify mic attached
to 3.5mm jack functional
Change-Id: I172a0bb299049d113a0272ee9c790b25b6242cad
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42499
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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fch_apic_routing is used as name of an array that init_tables()
populates with the APIC IRQ routing information. Also the fch_pirq array
where fch_apic_routing was used as struct name contains the IRQ mapping
for both PIC and APIC mode, so rename it to fch_irq_routing.
Change-Id: Iba7a2416c6e07cde1b8618bdabf31b00e3ca4dd1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The PIC and APIC IRQ routing tables are pre-populated with PIRQ_NC in
init_tables(), so the fch_pirq table entries where both IRQ numbers are
set to fch_pirq are redundant and can be removed.
Change-Id: I0d9b4f25e12a66cf86d1ad541955c3d2fe336c5a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Files are both identical and common for both SoCs.
Change-Id: I54b78108d342a0fd03bf70ffe6a09695c5678eb4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42545
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We don't use these on zork, so lets save the power.
BUG=b:153001807
TEST=Boot OS and make sure UART 1, 2 and 3 are not probed and remain
powered off.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2fadeba779b66ec2fb13951b9487118ef0737a94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add unique new acpi device ids for dptf for Tiger Lake soc based platforms
and update volteer speficic dsdt.asl file accordingly. The Linux kernel
driver expects these new acpi device ids for dptf functionalities.
BUG=None
BRANCH=None
TEST=Build and boot on volteer system
Change-Id: I7dbb812c0fc0f5084c98cf2752ce7ddce8e4d50e
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Kconfig 4.17 started using the $(..) syntax for environment variable
expansion while we want to keep expansion to the build system.
Older Kconfig versions (like ours) simply drop the escapes, not
changing the behavior.
While we could let Kconfig expand some of the variables, that only
splits the handling in two places, making debugging harder and
potentially messing with reproducible builds (e.g. when paths end up
in configs), so escape them all.
Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
|
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New kconfig dislikes unquoted slashes.
Change-Id: Ief242de081071021b9c904a24535d025f6674270
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42480
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Upcoming variant boards will use 16 MiB SPI ROM. So add support for 16
MiB flash map descriptor.
BUG=b:155107866,b:152981693
TEST=Build different variant boards. Ensure that waddledoo which is using
32 MiB SPI ROM boots.
Cq-Depend: chrome-internal:3107306
Change-Id: I8a6868da3280a662ff3a30623804ff135e6cbfbc
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Remove cannonlake dptf.asl include file from all the dsdt files
as per soc/intel/common/acpi code changes for dptf.
BUG=None
BRANCH=None
TEST=Build and boot on the system
Change-Id: I961a3ecb27e7bb7bb0b98c8630900bada0531639
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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CHROMEOS_DSM_CALIB requires/selects CHROMEOS, so only select if
CHROMEOS already selected, otherwise building for non-ChromeOS
targets fails.
Test: build HELIOS for non-ChromeOS target (Tianocore payload)
Change-Id: Ic0fd3b0a0efbc5a1f6896eb379569a55cb0f67f8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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It is the reference board of TGL-Y platform, we want to disable EC SW
sync for Proto stage, it would be re-enabled before EVT stage.
BUG=b:156435028
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ie7999e24e9c173d4870b35ce1728f3dcc8dcac29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42090
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:157567939
TEST="emerge-volteer coreboot chromeos-bootimage", flash and
boot volteer to kernel.
Change-Id: I3046cf3a359e833a5d204f78ab84312e8665061f
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42411
Reviewed-by: Jes Klinke <jbk@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Temporary workaround for S0ix issues related to FSP's handling of 0 value.
When IomTypeCPortPadCfg is 0 FSP completely skips any flow related to this
value which seems to be causing issues with s0ix.
This is still being debugged and a final solution will be made when available
BUG=b:159151238
TEST=flash image with workaround to volteer and verify that s0ix
cycles correctly.
Change-Id: Id79dd1c49958389cdb666b3760abd821bc1973a8
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42268
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
The PICASSO_UART Kconfig option is about using the internal MMIO UART
controllers in Picasso for console, so rename it to PICASSO_CONSOLE_UART
Change-Id: I38ac9ee96af826fe49307b4d0e055a43fcbd4334
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Update the following in dptf.asl
- Add support for TSR3
- Change TSR0/TSR1/TSR2/TSR3
From: Charger, 5V, GPU , None
To: Charger, GPU, F75303_GPU, F75303_GPU_POWER
- Adjust fan/cpu trip point accordingly
- Fix formating in dptf.asl
- Throttle charger when TSR0 (charger) is hot instead of throttle CPU
BUG=b:158676970
BRANCH=None
TEST=grep . /sys/class/thermal/thermal_zone5/{type,temp}
/sys/class/thermal/thermal_zone5/type:TSR3
/sys/class/thermal/thermal_zone5/temp:50800
Change-Id: Iedbb6bc7c1e59a027119c70791b9bc8a4d83ff87
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42270
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Bob Moragues <moragues@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Added device hid info to the MST and LSPCON devices on
kaisa, duffy and noibat.
BRANCH=None
BUG=b:156546414
TEST=None
Signed-off-by: Shiyu Sun <sshiyu@chromium.org>
Change-Id: I7b54512cd88e7280374c188315cabc2fba197f69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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|
ULT only has 4 threads, but we are not changing it here to preserve
binary reproducibility.
Change-Id: I041c5dff2de514244f9c919c4c475cca979c34ce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41842
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Also update autoport accordingly.
Change-Id: I12481363cf0e7afc54e2e339504f70632e8d72e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41839
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
If there is no installed audio daughter board on volteer then the
HDA driver in the kernel will crash on resume. In order to prevent
this disable the PCI device when AUDIO=NONE probe match is true.
BUG=b:147462631
TEST=boot on volteer and ensure that the PCI device at 0:1f.3 is gone
Change-Id: I4a436e1b76418030bf635427e490b54a713fdd33
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Zork family does not use OEM binary and so this change drops the
configs required for adding this binary.
Change-Id: Id38c67030e4055ab16934d1a900ee1cea5843b54
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
This change enables following ELOG options for zork family:
ELOG
ELOG_BOOT_COUNT
ELOG_GSMI
ELOG_BOOT_COUNT_CMOS_OFFSET
BUG=b:158875638
TEST=Verified that kernel reports GSMI loading correctly:
[ 5.308982] gsmi version 1.0 loaded
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4f34a814e744e863f1fbfc19e37209cb7febbdcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Update dq/dqs mappings based on terrador schematics.
BUG=b:156435028,b:151978872
BRANCH=none
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I97697a3dd9b88eaffe6e2b1be7bd346979cbc956
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Enables the fourth thermal sensor for fan in DPTF for volteer
BRANCH=None
BUG=b:149722146
TEST= On volteer system check
`cat /sys/class/thermal/thermal_zone5/type` for TSR3
Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com>
Change-Id: Ie11496828133aa71f1017f759516e2e5d3dff2d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
|
|
Added device hid info to the MST and LSPCON devices.
BRANCH=None
BUG=b:156546414
TEST=Manual tested and able to see update on sysfs and ssdt table
Signed-off-by: Shiyu Sun <sshiyu@chromium.org>
Change-Id: Iaef6c08f241ea671d1487a8524162dbb438b8e98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This patch adds correct PL2 baseline setting and PsysPL2 for different
SKUs. There is no way to identify the barral jack power rating, the
assumption is following that ships with the product:
1. i3/i5/i7: 90W BJ
2. Celeron/Pentium: 65W BJ
For Type-C adapter, we don't have Pcritcial (10ms) data, keeps the
original settings as 90% of adapter rating for PsyspL2/PL4 and PL2
as min(PL2, 0.9n) where n is adapter rating power.
BUG=b:143246320
TEST=Run with U62 and Celeron CPU and ensure the PL2 settings are correct
Change-Id: Ib16d4f65707801b430f06892ab45ecfa7551593f
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
The Endeavour variant does not have a DisplayPort input so there's no
need to wait for it.
BUG=b:147830399
BRANCH=none
TEST=boot endeavour; check coreboot logs
Signed-off-by: Jeff Chase <jnchase@google.com>
Change-Id: I30c7c47f19a61ce66c6c923864d80870d2761859
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
BUG=none
BRANCH=none
TEST=Verify sysjump from EC console, EC sync in romstage in AP
console and crossystem reflect ecfw_act as RW
Change-Id: Ief96fe481c94acef3754881cf1f453699fbfa52e
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41396
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=none
BRANCH=none
TEST=Boot WaddleDoo in recovery and populate the recovery MRC cache.
The subsequent recovery boot should boot out of the stored
recovery MRC cache and skip memory training.
Change-Id: Ief86fe481c94abef3754881cf1f454699fbfa52e
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41162
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Switch USB2 port1 and port3 for noibat due to circuit change.
BUG=b:154585046,b:156429564
BRANCH=none
TEST=none
Change-Id: I711038624f3efe397be73c29a940b3e17802598f
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42296
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows
SoC/mainboard to provide a linker file for the platform. x86 already
provides a default memlayout.ld under src/arch/x86. With this new
Kconfig variable, it is possible for the SoC/mainboard code for x86 to
provide a custom linker file as well.
Makefile.inc is updated for all architectures to use this new Kconfig
variable instead of assuming memlayout.ld files under a certain
path. All non-x86 boards used memlayout.ld under mainboard
directory. However, a lot of these boards were simply including the
memlayout from SoC. So, this change also updates these mainboards and
SoCs to define the Kconfig as required.
BUG=b:155322763
TEST=Verified that abuild with --timeless option results in the same
coreboot.rom image for all boards.
Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add DRAM support for vilboz:
Hynix H5AN8G6NCJR-VKC # 0b0000
Hynix H5ANAG6NCMR-VKC # 0b0001
Samsung K4A8G165WC-BCWE # 0b0010
Hynix H5AN8G6NDJR-XNC # 0b0011
Micron MT40A512M16TB-062E-J # 0b0100
Samsung K4AAG165WA-BCWE # 0b0101
Micron MT40A1G16KD-062E-E # 0b0110
BUG=b:157523051
BRANCH=none
TEST=build
Change-Id: I251fd9cc7bc51bfdeaa577f7034da750e684dc99
Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
This change adds memory parts used by variant voxel to
mem_list_variant.txt and generates DRAM IDs allocated to these parts.
This variant is not yet supported by coreboot but DRAM IDs need to be
generated for it. In the coming days, variant voxel will be added to
coreboot.
BUG=b:157732528
Change-Id: I8780beec987deb8fed11bb8f84275dcba4768514
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
For Volteer mainboard, this patch set optimized values for PCH external
VR settings and ext rail voltage/current, to achieve better power
savings in sleep states.
v1p05 and vnn power rails can be used as an alternative source
by-passing vccin_aux during Sx. This by-pass feature, enables us to
shutdown vccin_aux rail which is higher voltage rail compared to v1p05
and vnn. These both rails were disabled by default in FSP. Changes in
this patch are:
1. v1p05 and vnn rails are enabled and enabled supported voltage types
in S0i1, S0i2, S0i3, S3, S4, S5 states. They were disabled by default.
2. Icc Max for v1p05 changed to 500 mA from default 100 mA.
3. vnn rail's voltage is changed to 5 V from default 4.2 V.
BUG=None
BRANCH=None
TEST="Build and boot volteer and check VR settings with Intel ITP-XDP
debugger and verify approx 250 mW power savings in Sx"
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Ib46423872c956af9aaa92902fce552d5447237c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42223
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add initial support for boten variant board.
BUG=b:158023819
BRANCH=None
TEST=build
Change-Id: I56fe901c6aec781fac217ab08f7583cc25788688
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
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This port isn't packed on the board, so remove from
the devicetree.
BUG=b:154585046,b:156429564
BRANCH=none
TEST=none
Change-Id: Ib4aee337f67453adcebff7e93e25db7a838e3b2d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42269
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BRANCH=none
BUG=b:158713330
TEST=Flashing the LSPCON firmware works
Change-Id: Ib371f6954115145047c70cfd25262026cce087fd
Signed-off-by: Sam McNally <sammc@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
The picasso_ prefix on the fsp_pcie_descriptor and fsp_ddi_descriptor
structs isn't needed, since this code is picasso-specific, so drop it.
Change-Id: Ia6a0ddb411aa64becc3c23a876f2ea43cb68e028
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42252
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add initial support for drawcia
BUG=b:158540280
BRANCH=None
TEST=build
Change-Id: Ic775bb2a93581e422379ca90127e3581bbf3c89e
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
|
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Update DPTF_TSR2_SENSOR_ID to 2. Fixes the issue where TSR1 and
TSR2 have the same DPTF_TSR#_SENSOR_ID value causing them to
report the same temperature under /sys/class/thermal
and also swap TSR0 and TSR1 in DTRT to match physical sensor
in volteer schematics
BRANCH=None
BUG=b:149722146
TEST=On volteer system check TSR1 and TSR2 temperatures, should
report different values
`cat /sys/class/thermal/thermal_zone[3,4]/temp`
Also verify other TSRs using `cat /sys/class/thermal/thermal_zone*/temp`
and `ectool tempsinfo all ; ectool temps all`
Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com>
Change-Id: Idc5f35e4faf59b0ee726eb32a08eab4654fb342d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42232
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Selecting VBOOT_LID_SWITCH under BOARD_GOOGLE_BASEBOARD_HATCH creates a
requirement for VBOOT, and prevents building in the non-vboot/non-ChromeOS
case. As this symbol is already selected by CHROMEOS below, there's no need
for the baseboard (and only one of the two) to select it, so don't.
Change-Id: I060e82185997bce451648173dd97dd6a3d5d237f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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After adjustment on waddledoo
Touch Pad CLK: 392.9 KHz
Touch Screen CLK: 387.4 KHz
Audio CLK: 350.9 KHz
BUG=b:151302522
BRANCH=master
TEST=emerge-dedede coreboot chromeos-bootimage
measure by scope with waddledoo.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Iec02a751f1effdbefbb2969db2fd57f27ecdd033
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42187
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This change sets FMDFILE for zork family so that coreboot builds pick
up the right flash layout.
BUG=b:155990176
Change-Id: Ia1673622ccd14a2ff7bde555ed33d5b51cf4272a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42106
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I4cadfe69e36f959b54e374800c32629a7481ea94
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Setting the default values for GPIO community power management, causes
issues in detecting TPM interrupts. So to avoid that GPIO PM has to be
disabled in devicetree. But for S0ix it is needed. This patch implements
a workaround in ASL code to enable GPIO PM on S0ix entry and disable it
on S0ix exit.
This patch adds the following three platform specific methods.
1. MS0X to enable power management features for GPIO communities on
low power mode entry and disables it on exit.
2. MPTS to enable power management features for GPIO communities when
preparing to sleep.
3. MWAK to disable power management features for GPIO communities on
waking up.
BUG=b:153847814
TEST=Verify S0ix is working. GPIO PM configuration is upadated on low
power mode entry and exit.
Change-Id: I7225b78ab2ac5bf17f93230cd85cd21e836d807d
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41502
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
- Move the GPIOs that are likely to be volteer-specific (mostly
peripherals) to reside in variants/volteer/gpio.c so that
variants don't have to override too many GPIO settings.
- Modify malefor's gpio.c to adjust for the changes to baseboard's
gpio.c.
- Remove unused GPP_C3 (USB4_SMB_SCL) and GPP_C4 (USB4_SMB_SCA)
settings.
- Remove unused GPP_D9, GPP_D10, GPP_D11, and GPP_D12 settings.
- Remove unused GPP_E8 (SLP_S0IX), COEX, WWAN, and SNDW related
settings for malefor.
- Remove unused GPP_R4 (HDA_RST_L) setting.
BUG=b:157597158
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer SKU4 to kernel.
Change-Id: Ib2f384f539d55a3a8d4a7608336ef22aca3d8c4f
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
This patch adds correct PL2 baseline setting and PsysPL2 for different
SKUs. There is no way to identify the barral jack power rating, the
assumption is following that ships with the product:
1. i3/i5/i7: 90W BJ
2. Celeron/Pentium: 65W BJ
For Type-C adapter, we don't have Pcritcial (10ms) data, keeps the
original settings as 90% of adapter rating for PsyspL2/PL4 and PL2
as min(PL2, 0.9n) where n is adapter rating power.
BUG=b:143246320
TEST=Run with U62 and Celeron CPU and ensure the PL2 settings are correct
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: If7de614d58366158a566563990ee1ecc8c0110bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
Taken from Chrome OS update information. Looks like nami encompasses
many different devices, which would not fit in one line, so skip it.
Change-Id: I53405cba269cbfc25bd4618777b946500f173e7e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
The max98357a_platform_driver will turn on/off the speaker enable gpio
based on use, so configure it low to save power.
BUG=None
TEST=Built dedede and tested speaker playback working.
We are seeing a power saving of ~10mW.
Change-Id: I070679457b06cb82633c1197b893a5d89c8b2cf0
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
|
|
All variants are overriding soc_common_config, so source it from
overridetree and remove entry from baseboard devicetree.
Only keeping chipset lockdown config in baseboard which will be
common across all the variants.
BUG=None
BRANCH=None
TEST=Checked code compilation and lockdown config is applied to all variants
Change-Id: I23714b721a6bb0bac785f046586790a98dc5b646
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
|
|
The prefix mainboard_ was used everywhere else.
Change-Id: Ie576fd47301aa484cb1396e0c6f7260b7698af4d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Some of the boards do not select SYSTEM_TYPE_LAPTOP or _CONVERTIBLE
so their FADT preffered_pm_profile would change from PM_MOBILE without
the added overrides here.
Change-Id: I04b602b2c23fbd163fcd110a44ad25c6be07ab66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41920
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This change allows treating the PMC as a 'hidden' PCI device on Jasper
Lake, so that the MMIO & I/O resources can be exposed as belonging to
this device, instead of the system agent and LPC/eSPI.
Change-Id: Ie07987c68388d03359c43f64a849dc6e3f94676e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Change-Id: I9025ca3b6b438e5f9a790076fc84460342362fc2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41919
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:156564296
BRANCH=octopus
TEST=emerge-octopus coreboot
Change-Id: I99b04fec88da481e21b7a05807a4f1edeb3a5bdf
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
Change-Id: I1632d03a7a73de3e3d3a83bf447480b0513873e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41685
Reviewed-by: David Guckian
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This change adds memory parts used by variant wheelie to
mem_list_variant.txt and generates DRAM IDs allocated to these parts.
BUG=b:157862308
Change-Id: I53f6f5c832cd40068a6d4379ace849f6e8ad7a91
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41990
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Now that dedede is moved to using the auto-generated SPDs, we no
longer need the .spd.hex files in spd/ folder. Hence, this change
drops the files.
Change-Id: I026b3c61a2a88a7cd2c9842a26eb336324853add
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41882
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change switches dedede and family to using auto-generated SPDs
obtained using gen_spd.go and gen_part_id.go.
Change-Id: I6fadae0abcfb6e50d3cc502098ace9b668667a51
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41881
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
GENERIC_SPD_BIN assumes that the SPDs are all placed in mainboard and
have .spd.hex as the suffix. Disable GENERIC_SPD_BIN for dedede as it
already provides its own rules for SPD inclusion. In follow up
changes, GENERIC_SPD_BIN can be re-enabled by updating gen_spd.go tool
to use similar suffixes and allowing different paths to be provided
for SPD by mainboard.
Change-Id: If10144e0b2bd67884af69f60e5117e388a3ae5da
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42054
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
gen_part_id.go
This change adds mem_list_variant.txt that contains the list of
memory parts used by waddledoo and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.
In the final change of the series, all dedede variants will be
switched from using the current SPDs to new auto-generated SPDs.
Differences in auto-generated SPD from current SPD are as follows:
Part: MT53E512M32D2NP-046 WT:E
Byte# Current New Explanation
4 0x15 0x16 This part has only 1 die. Hence,
density per die is 16Gb.
6 0x90 0x04 1 die in package and 2 channels per
die.
9 0x40 0x00 Unused by MRC.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xFF as
per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
Additionally, manufacturer name bytes are set to 0.
Part: NT6AP256T32AV-J2
Waddledoo started assigning DRAM part IDs from 1. So, this change
fills in Nanya part as ID 0 (though it is currently unused).
Change-Id: I3879c4f3ad942eb349b52aad397333f576599bbd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
gen_part_id.go
This change adds mem_list_variant.txt that contains the list of
memory parts used by wheelie and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.
In the final change of the series, all dedede variants will be
switched from using the current SPDs to new auto-generated SPDs.
Differences in auto-generated SPD from current SPD are as follows:
Part: MT53E512M32D2NP-046 WT:E
Byte# Current New Explanation
4 0x15 0x16 This part has only 1 die. Hence,
density per die is 16Gb.
6 0x90 0x04 1 die in package and 2 channels per
die.
9 0x40 0x00 Unused by MRC.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xFF as
per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
Additionally, manufacturer name bytes are set to 0.
Change-Id: If307bfb1d376e32af08af4f020f9e125f6a415dd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
gen_part_id.go
This change adds mem_list_variant.txt that contains the list of
memory parts used by waddledee and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.
In the final change of the series, all dedede variants will be
switched from using the current SPDs to new auto-generated SPDs.
Differences in auto-generated SPD from current SPD are as follows:
Part: MT53E512M32D2NP-046 WT:E
Byte# Current New Explanation
4 0x15 0x16 This part has only 1 die. Hence,
density per die is 16Gb.
6 0x90 0x04 1 die in package and 2 channels per
die.
9 0x40 0x00 Unused by MRC.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xFF as
per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
Additionally, manufacturer name bytes are set to 0.
Part: NT6AP256T32AV-J2
Byte# Current New Explanation
4 0x14 0x15 This part has only 1 die. Hence,
density per die is 8Gb.
6 0x90 0x04 1 die in package and 2 channels per
die.
Manufacturer name bytes are set to 0.
Change-Id: I7a68a29ca3632e22f3960c9fc44acf3ce4f87c9c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Now that volteer is moved to using the auto-generated SPDs, we no
longer need the spd/ folder under each variant. Hence, this change
drops the spd/ folders and the SPD files within them.
BUG=b:156126658
Change-Id: Icb36adeb11fd68a84df5b225db32fb8d840a530f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41619
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change switches volteer and family to using auto-generated SPDs
obtained using gen_spd.go and gen_part_id.go.
BUG=b:147321551,b:155423877
Change-Id: I9ed48f0b51714b072a0459d0b70b5417a49db54f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
gen_part_id.go
This change adds mem_list_variant.txt that contains the list of
memory parts used by volteer and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.
In the final change of the series, all volteer variants will be
switched from using the current SPDs to new auto-generated SPDs.
Differences in auto-generated SPD from current SPD are as follows:
Part: K4U6E3S4AA-MGCL
Byte# Current New Explanation
6 0x95 0x94 Signal loading is not used by
MRC. Set bits 1:0 to 00.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS
latencies 20,24,28,32,36. So value
should be 0x54, 0x05.
24 0x8C 0x87 taa is .468ns * CAS-36 which results
in byte 24 being 0x87 as per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
124 0x7F 0x00 Fine offset for tckMax. Expected
value is 0x00 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
Part: K4UBE3D4AA-MGCL
Byte# Current New Explanation
6 0xB5 0xB4 Signal loading is not used by
MRC. Set bits 1:0 to 00.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
Part: H9HCNNNBKMMLXR-NEE
Byte# Current New Explanation
6 0x95 0x94 Signal loading is not used by
MRC. Set bits 1:0 to 00.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS
latencies 20,24,28,32,36. So value
should be 0x54, 0x05.
24 0x8C 0x87 taa is .468ns * CAS-36 which results
in byte 24 being 0x87 as per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
124 0x7F 0x00 Fine offset for tckMax. Expected
value is 0x00 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. tckMin is
calculated as (1/4267)*2 which comes
out to be 0.46871. Some datasheets
round this down to 0.468 and others
round it up to 0.469. JEDEC spec uses
0.468. As per that, this value comes
out to be 0xE0.
Part: H9HCNNNFAMMLXR-NEE
Byte# Current New Explanation
4 0x15 0x16 As per datasheet, density is 16Gb per
logical channel. So value should be 0x16.
6 0xF9 0xB8 This device has 4 logical dies
instead of 8. Also, signal loading is
not used by MRC.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
20,21, 0x92,0x55, 0x12,0x29, As per datasheet, part supports CAS
22 0x00 0x15 latencies 6,10,16,22,26,32,36,40. So value
should be 0x12,0x29,0x15.
24 0x8C 0x96 taa is .468ns * CAS-40 which results
in byte 24 being 0x96 as per datasheet.
29,30 0xE0,0x0B 0xC0,0x08 As per datasheet, this corresponds to
280ns in MTB units which is 0x08C0.
31,32 0xF0,0x05 0x60,0x04 As per datasheet, this corresponds to
140ns in MTB units which is 0x04C0.
123 0x00 0xE2 Fine offset for taa. Expected value
is 0xE2 as per datasheet.
124 0x7F 0x00 Fine offset for tckMax. Expected
value is 0x00 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. tckMin is
calculated as (1/4267)*2 which comes
out to be 0.46871. Some datasheets
round this down to 0.468 and others
round it up to 0.469. JEDEC spec uses
0.468. As per that, this value comes
out to be 0xE0.
Part: MT53E1G32D2NP-046 WT:A
Byte# Current New Explanation
4 0x15 0x16 As per datasheet, density is 16Gb per
logical channel. So value should be 0x16.
5 0x21 0x29 As per datasheet, this part has 17row
address bits and 10column address
bits. This results in 0x29.
6 0xB5 0x94 This device has 2 logical dies. Also,
MRC does not use signal loading.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
12 0x0A 0x02 As per datasheet, this is 1rank and
16-bit wide channel. So, value should
be 0x02.
21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS
latencies 20,24,28,32,36. So value
should be 0x54, 0x05.
24 0x8C 0x87 taa is .468ns * CAS-36 which results
in byte 24 being 0x87 as per datasheet.
29,30 0xC0,0x08 0xE0,0x0B As per datasheet, this corresponds to
380ns in MTB units which is 0x0BE0.
31,32 0x60,0x04 0xF0,0x05 As per datasheet, this corresponds to
190ns in MTB units which is 0x05F0.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
124 0x7F 0x00 Fine offset for tckMax. Expected
value is 0x00 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
BUG=b:147321551,b:155423877
Change-Id: I3998b2cd91020130bacf371fce9b0d307304acbe
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
gen_part_id.go
This change adds mem_list_variant.txt that contains the list of
memory parts used by halvor and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.
In the final change of the series, all volteer variants will be
switched from using the current SPDs to new auto-generated SPDs.
Differences in auto-generated SPD from current SPD are as follows:
Part: H9HKNNNCRMBVAR-NEH
Byte# Current New Explanation
4 0x16 0x15 As per datasheet, density is 8Gb per
logical channel. So value should be 0x15.
6 0xB9 0x94 Signal loading is not used by
MRC. Set bits 1:0 to 00. 2 channels 2
dies. Hence, 0x94
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
29,30 0xE0,0x0B 0xC0,0x08 As per datasheet, this corresponds to
280ns in MTB units which is 0x08C0.
31,32 0xF0,0x05 0x60,0x04 As per datasheet, this corresponds to
140ns in MTB units which is 0x0460.
125 0xE1 0xE0 Fine offset for tckMin. tckMin is
calculated as (1/4267)*2 which comes
out to be 0.46871. Some datasheets
round this down to 0.468 and others
round it up to 0.469. JEDEC spec uses
0.468. As per that, this value comes
out to be 0xE0.
Part: MT53E1G64D4SQ-046 WT:A
Byte# Current New Explanation
5 0x21 0x29 As per datasheet, this part has 17row
address bits and 10column address
bits. This results in 0x29.
6 0xB9 0x94 Signal loading is not used by
MRC. Set bits 1:0 to 00. 2 channels,
2 dies. Hence, 0x94.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
BUG=b:147321551,b:155423877
Change-Id: I28b065a00380516d8686279a92ef68b9f17e2f65
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41616
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
gen_part_id.go
This change adds mem_list_variant.txt that contains the list of
memory parts used by malefor and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.
In the final change of the series, all volteer variants will be
switched from using the current SPDs to new auto-generated SPDs.
Differences in auto-generated SPD from current SPD are as follows:
Part: K4U6E3S4AA-MGCL
Byte# Current New Explanation
6 0x95 0x94 Signal loading is not used by
MRC. Bits 1:0 set to 0.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS
latencies 20,24,28,32,36. So value
should be 0x54, 0x05.
24 0x8C 0x87 taa is .468ns * CAS-36 which results
in byte 24 being 0x87 as per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
124 0x7F 0x00 Fine offset for tckMax. Expected
value is 0x00 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
BUG=b:155239397,b:147321551
Change-Id: I8b8bdc55314f538aff4dd1944a0b745357744d8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41615
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
gen_part_id.go
This change adds mem_list_variant.txt that contains the list of
memory parts used by ripto and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.
In the final change of the series, all volteer variants will be
switched from using the current SPDs to new auto-generated SPDs.
Differences in auto-generated SPD from current SPD are as follows:
Part: K4U6E3S4AA-MGCL
Byte# Current New Explanation
6 0x95 0x94 Signal loading is not used by
MRC. Bits 1:0 set to 0.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS
latencies 20,24,28,32,36. So value
should be 0x54, 0x05.
24 0x8C 0x87 taa is .468ns * CAS-36 which results
in byte 24 being 0x87 as per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
124 0x7F 0x00 Fine offset for tckMax. Expected
value is 0x00 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
BUG=b:155239397,b:147321551
Change-Id: Ibb06443a5c7fd80915f66b806cdd7c3ae1275b05
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41614
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Remove unused includes
Change-Id: I7e8109870168db7f477f205a0b3020b7b2be5f5f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41541
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
