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path: root/src/mainboard/google
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2023-09-21mb/google/zork: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Iaa73bf7f85f840299c467b7d712546d3f72a4e75 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-21mb/google/cherry: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id1b0d375670f9e59047eff737bc17e61bf93175e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75016 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/mistral: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I1033a974a818308b31e1334cad5869d2cd81bd9e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75017 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/corsola: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I207e25059a9fb9e6a951018e954662931b3f8b93 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75018 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/kahlee: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id060f781b87567da2756c89275002b9ea4f4976c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75015 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/zork/morphius: Hide FPR, PENH from Windows OSMatt DeVillier
No drivers exists or are needed, so use devicetree hidden keyword to set the ACPI status to hidden to prevent unknown devices from showing in Windows Device Manager. TEST=build/boot Win11 on morphius, verify unknown devices for the fingerprint reader and stylus detection are no longer shown. Change-Id: I992c0ec8d97c6041e3a268445613bfa42dd8b279 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-21mainboard/google/skyrim: Enable wake-on-DPRobert Zieba
Enable wake-on-DP by adding USB mux events to the wake mask. The EC wakes the AP with these events for DP connect/disconnect. BUG=b:294307786 TEST=DP connect/disconnect wakes the DUT appropriately. Change-Id: I864b03d08ce3d756bf4987d886db621d937483ce Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78034 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-21mb/google/rex/var/karis: Enable PIXA touchpadTyler Wang
Karis uses PIXA touchpad, update related settings. BUG=b:294155897 TEST=(1) emerge-rex coreboot (2) Test on karis, touchpad function works Change-Id: I26e3257485c4abe050de7a79c6d3b72dbd048710 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77517 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-20mb/google/rex/var/karis: Set VPU disable as defaultTyler Wang
BUG=b:299374763 TEST=emerge-rex coreboot Change-Id: I40fc768522e8679337c3b9f5497278e9f4639c3e Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77888 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-20mb/google/rex: Select MIPI pre-prod if MTL pre-prod Si setSubrata Banik
This patch ensures that the `DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC` config is enabled if the underlying platform is built with a pre-production SoC (aka `SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON` config is enabled). BUG=b:300652989 TEST=Ensures `DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC` is enabled for google/rex4es aka all variants with ES silicon. Change-Id: Ieda39427915fa3973b832376ec20fc414ac2bedd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77993 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2023-09-20mb/{google,intel}: Choose platforms with pre-prod Meteor Lake SoCSubrata Banik
The tree contains engineering sample boards, that ship with pre-production Meteor Lake SoC. These boards are not sold. BUG=b:300652989 TEST=Ensure mainboards like google/rex4es and screebo4es have `SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON` config enabled. Change-Id: I1a875a0f1d2c38582f35250ebe645e53599f62de Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77992 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-09-19soc/amd/picasso: add eMMC MMIO device to devicetreeFelix Held
Add the eMMC MMIO device to the devicetree and make it use the common AMD eMMC driver. Since there is now a device for this in the devicetree, also use this device to determine if the FSP should be told if the eMMC controller is supposed to be disabled. TEST=On Mandolin the eMMC controller both disappears in the Windows 10 device manager and in dmesg on Ubuntu 2022.04 LTS TEST=Morphius with NVMe SSD still works Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5453b69df776d2ce1f3be11e37cd26c8c64f0cd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-19mb/google/rex/var/screebo: Change GPP_C06 to NCZhongtian Wu
GPP_C06 is the report pin of the touchpanel and has no actual function. Disable this pin to solve the leakage problem. BUG=b:298529441 BRANCH=none TEST=Test success by EE. Change-Id: I13f25788c0258639da4e277e7a15454a08d1599b Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77716 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-18drivers/tpm: Make temp test value naming consistentJon Murphy
Make naming convention consistent across all functions return values. BUG=b:296439237 TEST=Boot to OS on Skyrim BRANCH=None Change-Id: If86805b39048800276ab90b7687644ec2a0d4bee Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77536 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-18mb/google/skyrim: Re-enable USE_SELECTIVE_GOP_INIT for SkyrimMatt DeVillier
This reverts commit dc7cc5bc6edf ("mb/google/skyrim: Disable USE_SELECTIVE_GOP_INIT") but limits the default enablement to Skyrim variant only, to allow for continued testing. BUG=b:271850970 BRANCH=skyrim TEST=build/boot ChromeOS R117+ on google/skyrim, verify no display init failures with feature enabled on cold/warm boots or S0i3 resume. Change-Id: I21c70111a5f407a7e8dd1ad1f2c2759ddb91893e Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-09-18mb/google/dedede/var/taranza: Update USB PLDsReka Norman
Update PLDs to match the port layout: Front (left to right): A4, A3, A2 Back (left to right): C0, A0, A1 BUG=b:264960828 TEST=USB2 and USB3 ports are peered correctly in the kernel: Before: $ cd /sys/devices/pci0000:00/0000:00:14.0 $ ls -l $(find . -name peer) ./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1 ./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port2 ./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port3 ./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port4 ./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5 ./usb1/1-0:1.0/usb1-port6/peer -> ../../../usb2/2-0:1.0/usb2-port6 ./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1 ./usb2/2-0:1.0/usb2-port2/peer -> ../../../usb1/1-0:1.0/usb1-port2 ./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port3 ./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port4 ./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5 ./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port6 After: $ cd /sys/devices/pci0000:00/0000:00:14.0 $ ls -l $(find . -name peer) ./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1 ./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3 ./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4 ./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port6 ./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5 ./usb1/1-0:1.0/usb1-port7/peer -> ../../../usb2/2-0:1.0/usb2-port2 ./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1 ./usb2/2-0:1.0/usb2-port2/peer -> ../../../usb1/1-0:1.0/usb1-port7 ./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2 ./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3 ./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5 ./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port4 Change-Id: I682a153d6b757e1b66373c622a6fcfbf389184e3 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77877 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-18mb/google/dedede/var/boxy: Update USB PLDsReka Norman
Update PLDs to match the port layout: Front (left to right): C0, A1, A0 Left side: C1 Also enable the usb 3.1 device. BUG=b:264960828 TEST=USB2 and USB3 ports are peered correctly in the kernel: Before: $ cd /sys/devices/pci0000:00/0000:00:14.0 $ ls -l $(find . -name peer) ./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1 ./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port3 ./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port4 ./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5 ./usb1/1-0:1.0/usb1-port6/peer -> ../../../usb2/2-0:1.0/usb2-port6 ./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1 ./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port3 ./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port4 ./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5 ./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port6 After: $ cd /sys/devices/pci0000:00/0000:00:14.0 $ ls -l $(find . -name peer) ./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1 ./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3 ./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4 ./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port2 ./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5 ./usb1/1-0:1.0/usb1-port6/peer -> ../../../usb2/2-0:1.0/usb2-port6 ./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1 ./usb2/2-0:1.0/usb2-port2/peer -> ../../../usb1/1-0:1.0/usb1-port4 ./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2 ./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3 ./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5 ./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port6 (Ports 5 and 6 are not used on boxy but are peered by default) Change-Id: I1563d9eaa27353c8c97225a0a6ecc238e9275ce2 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2023-09-16mb/google/rex: Optimize FMD usage for rex variantsSubrata Banik
This patch eliminates the need to maintain separate FMD files for rex variants and rex variants with ISH. It does this by using the BOARD_GOOGLE_MODEL_REX_EC_ISH config to differentiate between ME-RW layout sizes. TEST=Able to build and boot google/rex and google/rex_ec_ish. Change-Id: Ibb6ee9aad9fb68198c6c1a1d5978f77d53a2e3ac Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77895 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-16Revert "mb/google/rex/var/screebo: Reduce TCC from 90°C to 80°C"Subrata Banik
This reverts commit 449c6d981c216e05d5238056f03c7794e43600ec. Reason for revert: (EVT board build does not exhibit shutdown followed by warm reboot) This commit reverts the workaround that limits the TCC activation temperature. The original issue that was reported (shutdown followed by warm reboot) was not seen in the EVT board build, so this change is likely unnecessary. Change-Id: I22adcdee6512e57ad0b6d531f2611e22a95c863e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-16mb/google/brya0: Configure _DSC for camera devicesBora Guvendik
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that the driver skips initial probe during kernel boot and prevent privacy LED blink. TEST=Boot to OS, check camera LEDs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib9375d602171aa5018b1add1deac3021724dc207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-09-15mb/google/brya/var/craask: Disable C1 PMC mux conn for HDMIRen Kuo
Add fw_config - DB_1A_HDMI for craaskana, and disable C1 PMC mux conn for HDMI. BUG=b:296791122 TEST=build and check HDMI function works on craaskana Change-Id: Ibaa0cd917a23b7f670ecd648765d1eb566edfe61 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77890 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2023-09-15mb/google/rex/var/karis: Disable stylus/FP module based on fw_configTyler Wang
There are going to be skus without stylus and fingerprint module. Disable stylus and fingerprint module based on fw_config. BUG=b:290689824 TEST=emerge-rex coreboot Change-Id: I047aae06c4a915d0392edc836757b882a261c178 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77647 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-15mb/google/rex/var/karis: Update fw_config settingsTyler Wang
Update fw_config settings for karis: | | | 0 --> STYLUS_ABSENT | | Bit 2 | STYLUS | 1 --> STYLUS_PRESENT | | | | | | Bit 3-5 | AUDIO | 0 --> ALC5650_NO_AMP_I2S | | | | | | Bit 8-9 | MIPI_CAM | 0 --> UF_CAM_HI556 | | | | | | | | 0 --> FP_ABSENT | | Bit 10-11 | FP_MCU | 1 --> FP_MCU_NUVOTON | | | | | | | | 0 --> WIFI_CNVI | | Bit 13 | WIFI_TYPE | 1 --> WIFI_PCIE | BUG=b:290689824 TEST=emerge-rex coreboot Change-Id: I1df30ad32d212a36b8a5bd7324f3eb8045b2795c Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-15mb/google/dedede/var/dibbi: Swap USB3 ports for A2 and A3Reka Norman
BUG=b:264960828 TEST=USB2 and USB3 ports are peered correctly in the kernel: Before: $ cd /sys/devices/pci0000:00/0000:00:14.0 $ ls -l $(find . -name peer) ./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1 ./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3 ./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4 ./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port5 ./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port6 ./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1 ./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2 ./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3 ./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port4 ./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port5 After: $ cd /sys/devices/pci0000:00/0000:00:14.0 $ ls -l $(find . -name peer) ./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1 ./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3 ./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4 ./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port6 ./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5 ./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1 ./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2 ./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3 ./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5 ./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port4 Change-Id: I5fe8066e361da62b747464b2ec09bcc6e7dda0fe Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77867 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-15mb/google/rex: add support for UWBEran Mitrani
UWB on Rex will have 2 options to connect to the SoC: 1. Through GSPI1 (muxed with FP) 2. bit-bang over GPP This CL adds GSPI1 option. BB may be added later. BUG=b:263413448, b:263499898 TEST=UWB ranging works on Rex with this CL Change-Id: I93b3bcef84d775866df43d00c934f013e9f85c47 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76665 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-15mb/google/brya/var/pujjo: modify wifi sar table for pujjo1eLeo Chou
1. WIFI_SAR_ID_4: AX211 2. WIFI_SAR_ID_5: AX203 (without WiFi-6E) BUG=b:293360900 TEST=emerge-nissa coreboot Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I6c4705d25d927aaefbc8814ea1df3b4c36b30968 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77790 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-15mb/google/brask/var/kuldax: Add fw_config probe for USB HubDavid Wu
Kuldax-refresh use USB Hub, add fw_config probe for USB Hub. BUG=b:275335023 BRANCH=brya TEST=Built and check firmware log. Change-Id: Ib983ca527a891718f317336597faad66d076247f Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-14mb/google/rex: Enable DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC for ES ↵Jamie Ryu
variants This enables DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC for rex variants boards with ES SoC to load pre-production signed IPU FW from IPU kernel driver to make Camera function properly. BUG=None TEST=Build rex and check if SSDT-IPU0 includes the correct value for "is_es" with Meteorlake ES and QS SoC. Change-Id: I407d1932762622652939e8568fe34c704bc3b433 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77855 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-14mb/google/dedede: Update dibbi ec.h settingsReka Norman
Update the dibbi ec.h so that it's correct for a chromebox. Remove everything related to: - Lid - Battery - Built-in keyboard - AC connect/disconnect - Mode changes BUG=b:294963793 TEST=Boot dibbi and check the APCI tables no longer contain lid and PS/2 keyboard devices. Change-Id: Idfa5adcec308d68555d292fddc1db43c9a64d649 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77863 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-14mb/google/dedede: Use a separate ec.h for dibbi variantsReka Norman
Dibbi variants are chromeboxes, so they need different settings in ec.h. Add a new dibbi baseboard ec.h and use it for dibbi variants. For now it's identical to the dedede baseboard ec.h. It will be updated in the following CL. BUG=b:294963793 TEST=With the following CL, boot dibbi and check the APCI tables no longer contain lid and PS/2 keyboard devices. Change-Id: I4075041ab8f02026623d1a26a555bee5eb09e77b Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77782 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
2023-09-13mb/google/brya: Create dochi variantMorris Hsu
Create the dochi variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:299570339 BRANCH=firmware-brya-14505.B TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_DOCHI Change-Id: Iadeb97bd217278cdf777ae350100313b4345ecf3 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77756 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-13mb/google/brya/var/craask: Add audio codec ALC5650Ren Kuo
Add audio codec ALC5650 related settings. BUG=b:289969623 TEST=emerge-nissa coreboot confirm the device in kernel log. Change-Id: I4b8a19e6248bd91cfc31feb84c6108413cd719e2 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77701 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-13mb/google/nissa/var/pujjo: Select VBT based on FW_CONFIG for pujjo1eLeo Chou
Select pujjo1e vbt bin files based on PANEL_IVO_BOE field of FW_CONFIG. BUG=b:299852789 TEST=emerge-nissa coreboot Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I344f97331e79e713af47ad743e27794e21be4ca3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-09-13mb/google/brya/var/pujjo: modify fw_config to separate pujjo1e wifi sar tableLeo Chou
Use fw_config for a dedicated pujjo1e intel wifi sar table. BUG=b:293360900 Test=emerge-nissa coreboot Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I635d3d23384cc4efd85b0c420817dd18a65d2872 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77648 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-11mb/google: Remove space between function name and '('Elyes Haouas
Change-Id: I0909f24844fab3dfc859ea8c5325344a9872799f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-08mb/google/rex: Fix ACPI MPTS method for non-5G board SKUsCliff Huang
MPTS method should only be generated for the board sku with 5G. BUG=NA TEST=Check kernel messages when going to S3. The following errors should not be seen: ACPI BIOS Error (bug): Could not resolve symbol [\_SB.PCI0.RP06.RTD3._STA] ACPI Error: Aborting method \_SB.MPTS due to previous error (AE_NOT_FOUND) ACPI Error: Aborting method \_PTS due to previous error (AE_NOT_FOUND) Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I78f434c9049773cf5229d3a1f3934ae82d1fe46d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77690 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-08mb/google/rex: Require VBOOT_LID_SWITCH for Chromebook designSubrata Banik
This patch ensures that platforms with lids, such as Chromebooks, only select the VBOOT_LID_SWITCH configuration option. Only samples the LID GPIO if VBOOT_LID_SWITCH config is enabled, otherwise fake LID is open to avoid shutdown after reaching depthcharge. Tested by building and booting Google/Rex with the VBOOT_LID_SWITCH configuration option enabled, and verifying that google/ovis does not required VBOOT_LID_SWITCH config. Change-Id: Ic5123b822a5a7021023319cb08a3f9e5225961ba Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77693 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-07mb/google/myst: Set i2c2 to hidden in devicetreeMatt DeVillier
Allows ACPI SSDT generator to hide the device from Windows via _STA Change-Id: I41fc7f847ef08138cb0f430bfd1a170f209163f1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77681 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-07mb/google/zork: Set i2c3 to hidden in devicetreeMatt DeVillier
Allows ACPI SSDT generator to hide the device from Windows via _STA Change-Id: I19f0a5a72ec409b306be7bc4bb53425870fc6298 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-07mb/google/skyrim: Set i2c3 to hidden in devicetreeMatt DeVillier
Allows ACPI SSDT generator to hide the device from Windows via _STA Change-Id: Idb5d2cd6eca2a2746e89a371005332e9f621df83 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77675 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-07mb/google/guybrush: Set i2c3 to hidden in devicetreeMatt DeVillier
Allows ACPI SSDT generator to hide the device from Windows via _STA Change-Id: I22b3ccc2c89a3f7ababd0eaf4e35604880aa0ce7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-07mb/google/nissa/var/craask: Modify SD_CARD element to prevent confuseTyler Wang
Modify SD_CARD element "SD_GL9750S" to "SD_PRESENT" to prevent confusion. Origin: 0 --> SD_GL9750S Modify: 0 --> SD_PRESENT BUG=b:296505165 TEST=emerge-nissa coreboot Change-Id: Ic355b7df9f9added4489a764f774851f2e4451c3 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-09-07mb/google/rex/var/karis: Update MIPI User facing camera settingsTyler Wang
Update overridetree and GPIO settings for MIPI UFC due to updated schematic updates. BUG=b:298133153 TEST=emerge-rex coreboot Change-Id: I4c3197e3f15e0cb3fc640b1749d8681299981563 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77591 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eran Mitrani <mitrani@google.com>
2023-09-07mb/google/brya/var/{kano,osiris,taeko}: Add null pointer checkWisley Chen
Without part no. in CBI, mainboard_get_dram_part_num returns null. To prevent passing this null pointer to strcmp and avoid unexpected behavior, proper handling is necessary. BUG=none TEST=emerge-brya coreboot Change-Id: I47e42376c6b1347c56afaec218aed63c5469f0aa Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77646 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-07mb/google/brya/var/yavilla: Add VBT data fileRobert Chen
Add data.vbt file for yavilla recovery image. Select INTEL_GMA_HAVE_VBT for yavilla which currently have a VBT file. BUG=b:298320552 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I72f98181b3487f8ae9acf6e0f2382a0204f7989c Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-06google/puff: Enable ASPM of RTL8111HAlexis Savery
With kernel 5.15, puff hangs during power idle tests because the NIC does not enter ASPM L1.2. We add "enable_aspm_l1_2" in devicetree for RTL8111H to enable ASPM L1.2. BUG=b:268859220, b:279618219 TEST=emerge and run power.Idle Change-Id: I129dfd79e8112191453be513b2e3a260429b3030 Signed-off-by: Alexis Savery <asavery@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77570 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-06google/puff: remove workaround that toggled the #ISOLATE pinAlexis Savery
A workaround was added for puff to assert/deassert the #ISOLATE pin during suspend/resume to resolve the situation where the realtek ethernet device cannot enter L1.2 mode when its ASPM is disabled. The realtek driver has since been fixed and ASPM of realtek devices have been enabled on kernel 5.10 and 5.15 and this original workaround is now causing suspend/resume errors on kernel 5.15: r8169 0000:01:00.0: Unable to change power state from D3cold to D0, device inaccessible Puff devices were originally shipped with kernel 4.19, and applying this change to the firmware on a device running 4.19 causes suspend/resume failures, basically reversing the problem. We are upreving the puff kernel to 5.15 so we need this patch, but since it is incompatible with 4.19 we will have to take that into consideration when pushing new firmware and potentially will need to backport the necessary fixes to 4.19. BUG=b:268859220 TEST=suspend_stress_test -c 500 on wyvern Change-Id: I5eead2d70cd9528b3ca3fadd11f98c0330601324 Signed-off-by: Alexis Savery <asavery@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77378 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2023-09-06mb/google/nissa/yaviks: Disable V1P05 control pinWisley Chen
Yaviks already disabled external V1P05, so disable V1P05 control pin which controls the VCC_V1P105_EXT_1P05. BUG=b:294456574 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I4128cfcfa5be0d141f0173e87518407331d79e8e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77645 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-05mb/google/nissa/var/yavilla: Disable SUSCLK based on fw_configShon Wang
Disable SUSCLK for MT7922 based on FW_CONFIG to avoid power leakage. SAR_ID_0 : Yaviks_Gfp2 SAR_ID_1 : Yaviks & Yavilla_MT7921 SAR_ID_2 : Yahiko_Gfp2 SAR_ID_3 : Yavilla_MT7922 BUG=b:298138654 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I2f191683d0623aa5dce815998a24fddce2a36b2c Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77559 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-05mb/google/nissa/var/yaviks: Disable AUX pins based on FW_CONFIGWisley Chen
Configure the AUX pins as NC based on the FW_CONFIG setting when the C1 port is not present. BUG=b:294456574 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I24fb8f16c2e3b05edf1056b5687ae5ea28c022c0 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-05mb/google/nissa/var/yavilla: Restore WLAN_PERST_L power sequenceTony Huang
Restore TPERST_HIGH to 160ms since it has beed validated in other OEM projects and haven't heard any issue so far. This change back commit d710c6d5a773 ("mb/google/nissa/var/yavilla: Adjust WLAN_PERST_L power sequence"). BUG=b:295277868 TEST=emerge coreboot boot to system and check wifi connection is fine Change-Id: Ifc66e596fc7b6efdc0c286ee187969c8774bdc80 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-05mb/google/nissa/var/pirrha: Use GpioInt instead of GPE for digitizer penSeunghwan Kim
Currently pirrha's digitizer pen uses GPP_F12 for I2C HID interrupt signal. But its IRQ number is the same as GPD2, which is used as EC_SYNC_IRQ. It caused EC driver loading error from dmesg: cros_ec_lpcs GOOG0004:00: Failed to request IRQ 98: -16 cros_ec_lpcs GOOG0004:00: couldn't register ec_dev (-16) cros_ec_lpcs: probe of GOOG0004:00 failed with error -16 So change the digitizer pen interrupt type to GpioInt to prevent the conflict. BUG=b:292134655 TEST=Verified EC driver reported no error and pen device worked Change-Id: Ieb88e87fcfb06544a4b5b5133b752aa821fab76a Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77346 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-05mb/google/nissa/var/pirrha: Update device configurationsSeunghwan Kim
Based on schematics and gpio table of pirrha, generate overridetree.cb to configure internal devices and generate fw_config.c to override GPIO configurations following FW_CONFIG. BUG=b:292134655 TEST=FW_NAME=pirrha emerge-nissa coreboot chromeos-bootimage Change-Id: I91013b0ad89e26f0a4c433c305c6b883d000f042 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77116 Reviewed-by: Jamie Chen <jamie.chen@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jimmy Su <jimmy.su@intel.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-09-04mb/google/rex/var/screebo: Set `SAGV_POINTS_0_1_2` to avoid hangWentao Qin
Setting SaGvWpMask to SAGV_POINTS_0_1_2 in dev tree can effectively avoid the idle hang issue, but it will affect the system power. (Before root cause, this is a short term workaround to unblock function test.) BUG=b:287170545 TEST=Able to idle for more than 5+ hours without any hang. Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Change-Id: I0947815ab79b470d2ae922cffdd8250c60cf1afd Reviewed-on: https://review.coreboot.org/c/coreboot/+/77520 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
2023-09-02mb/google/rex/var/karis: Drop unused audio codecs and amplifiersTyler Wang
BUG=b:294155897, b:295112765 TEST=emerge-rex coreboot Change-Id: Ic7e272a484ea76dfc3a314b3597cbc18c856a9ca Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-02mb/google/rex/var/karis: Add audio codec ALC5650Tyler Wang
Add audio codec ALC5650 related settings. BUG=b:294155897, b:295112765 TEST=emerge-rex coreboot Change-Id: I2b54dd600b47ecdfd1f488a8c623bc0599c8936f Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77360 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-02mb/google/rex/var/screebo: add hook for WiFi SAR tableYH Lin
As a preparation for WiFi SAR table addition, adding hook for it. BUG=b:291155207 TEST=emerge-rex coreboot Change-Id: Ia313cfddec278e6bf8498407b242c027a5891deb Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77598 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-02mb/google/rex/var/screebo: add FP_MCU fw_configYH Lin
Add FP_MCU definitions for fw_config according to the current build matrix. BUG=b:291155207 TEST=emerge-rex coreboot Change-Id: Id67b20a750d14eb23c62be9a30a5ef21d80e486a Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-02mb/google/rex/var/screebo: remove SD_ABSENTYH Lin
Remove SD_ABSENT since it's not being used, and CBI FW_CONFIG in current build does not reflect this config neither. BUG=b:291155207 TEST=emerge-rex coreboot Change-Id: Icfa472ff5570ac728038ec67a762289407760812 Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77596 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-02mb/google/nissa/var/uldren: Enable Weida touchscreenDtrain Hsu
Support Weida WDT8790A touchscreen. BUG=b:297453122 BRANCH=firmware-brya-14505.B TEST=touchscreen is workable and evtest shows WDHT2601 $evtest No device specified, trying to scan all of /dev/input/event* Available devices: /dev/input/event0: Lid Switch /dev/input/event1: Power Button /dev/input/event10: sof-cs42l42 HDMI/DP,pcm=2 /dev/input/event11: sof-cs42l42 HDMI/DP,pcm=3 /dev/input/event12: sof-cs42l42 HDMI/DP,pcm=4 /dev/input/event13: sof-cs42l42 HDMI/DP,pcm=5 /dev/input/event2: AT Translated Set 2 keyboard /dev/input/event3: cros_ec_buttons /dev/input/event4: Elan Touchpad /dev/input/event5: WDHT2601:00 2575:0921 /dev/input/event6: WDHT2601:00 2575:0921 Stylus /dev/input/event7: WDHT2601:00 2575:0921 Stylus /dev/input/event8: DELL Dell USB Entry Keyboard /dev/input/event9: sof-cs42l42 Headset Jack Change-Id: If9539afaf891c8352bc7fc8e548fd77ea57ea6ca Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77575 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-02mb/google/rex/var/karis: Enable ELAN touchscreenTyler Wang
BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I179df1e0e544783f77a485ad08293530e8a86ecd Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77592 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-02mb/google/nissa/var/yaviks: Add wifi sar for yahikoWisley Chen
Add intel wifi sar table for yahiko BUG=b:298280621 BRANCH=firmware-nissa-15217.B TEST=build, enable iwlwifi debug option, and check dmesg Change-Id: I38d2e640fc2f7cbde3986474ca1bf7de9b2d25b4 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77585 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-02mb/google/brya/var/skolas: add nau8318 speaker supportMac Chiang
Add variant of NAU8318(SPK) + NAU88L25B(Headphone) audio support on brya and skolas board. In fw_config settings, reuse max98360_enable_pads[] due to identical i2s configurations as nau8318. In addition, separated GPP_R7 as SPK_BEEP_EN pin. BUG=b:236561637 TEST=emerge-brya coreboot BRANCH=none Signed-off-by: Mac Chiang <mac.chiang@intel.com> Suggested-by: David Lin <CTLIN0@nuvoton.com> Signed-off-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com> Change-Id: Ife47a83fca902cf63e09d11206e9d99fac0dc9a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-01mainboard/google/skyrim: Enable MP2 FW loadingRobert Zieba
This board will use custom MP2 FW to dump the contents of the STB when the SOC fails to enter/exit S0i3. Enable `PSP_LOAD_MP2_FW` by default. BUG=b:259554520 TEST=Built and ran on skyrim device, verified that MP2 FW loads. Change-Id: I4222521d01e2c98708f0e5b6693a8aee9e59edf2 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72118 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01mb/google/rex: Add `rex4es_ec_ish` variantBernardo Perez Priego
This patch creates rex ES variant with EC ISH enabled. BUG=b:296886409 TEST=Able to build and boot rex4es_ec_ish variant. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I2b1cdb8cffd66badd90a7bf9825d9decb07941a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-01util/amdfwtool: Deal with psp position in flash offset directlyZheng Bao
It is based on work by Arthur Heymans, 69852. Get rid of the confusing "position index" and use the relative flash offset as the Kconfig setting instead. TEST=binary identical on amd/birman amd/majolica amd/gardenia amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon pcengines/apu2 google/skyrim google/guybrush google/zork google/kahlee google/myst (The test should be done with INCLUDE_CONFIG_FILE=n) Change-Id: I26bde0b7c70efe9f5762109f431329ea7f95b7f2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-31mb/google/dedede/var/pirika: Add FW_CONFIG probe for EXT_VRDaniel_Peng
Add FW_CONFIG probe for absent FIVR bypass mode on peezer. BUG=b:296982082 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage Change-Id: I0b2053b2d732fd9462686ed7b0c9225539b28fb2 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77396 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-31mb/google/rex/var/karis: Update GPIO settings for NC pinsTyler Wang
According to the schematic, set below GPIO to NC: 1. GPP_C18 2. GPP_C19 3. GPP_S04 4. GPP_S05 BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: If1f847d2db83b63a351203f0449cc1368bef27f4 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77558 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-31mb/google/rex/var/rex0: Add HDMI GPIOs to early GPIO listAnil Kumar
Add HDMI GPIO configuration to early GPIO list to support VGA text o/p in Pre-RAM stage on HDMI. BUG=b:279173035 TEST=If CONFIG_UGOP_EARLY_GRAPHICS is set to y, check SOL text on HDMI during Pre-RAM boot stage. Change-Id: I13691850d09a442d5d5493a2b1dcf1145cf9797a Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-31mb/google/rex: Enable Fast V-Mode for MTL-U 15WSubrata Banik
This patch sets the Fast V-Mode (FVM) configuration parameter as suggested in Intel doc 640982. As per the doc, Intel MTL-U 15W CPU supports FVM on IA and SA. Fast V-Mode (FVM): Intel Meteor Lake introduces the ability to manage the peak power events it calls "reactive peak power management". The Fast V-Mode is one such technique to perform the reactive peak power management. It relies on the detector integrated inside the processor which senses when the processor load current exceeds a present threshold by monitoring the processor power domain IMVP (Intel Mobile Voltage Positioning) VR sense point. The baseline ITRIP for IA is 66A and 21A for SA. BUG=b:286809233 TEST=Able to build and boot google/rex without seeing any performance regression. Change-Id: Ia7157bddf2e9586e4a91cc55e48693561072cd05 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75763 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-30mb/google/rex/var/karis: Remove USB cameraTyler Wang
Karis use MIPI camera only, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I96316d63c068c48b5bec75d3b4c5444d15fd985f Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77510 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-30mb/google/rex/var/karis: Remove SAR sensorTyler Wang
According to the schematic, karis does not have a SAR sensor. Update GPIO settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ib3b66b9594f2d0fddbbfc56e99f06b6587487f2a Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-30mb/google/rex/var/karis: Set GPP_D04 to NCTyler Wang
Follow schematic, set GPP_D04 to NC. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ie222a2773ff7d2b87641f55b4d37ff3bdf761cd2 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-30mb/google/rex/var/screebo: Enable GL9750 invert WP functionKun Liu
enable GL9750 invert WP function BRANCH=none BUG=b:297244291 TEST=emerge-rex coreboot Change-Id: I7fdc94b5ca6b316ee0291c38e39c5f8b08cbc127 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77414 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-28Revert "mb/google/brya: fix MRC cache failure for hynix parts"Nick Vaccaro
This change causes a freeze during boot on an RPL-UR that does not have the memory part string in the CBI. BUG=b:296353047 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage', flash and boot problematic DUT to kernel. This reverts commit c51a7cdde4e1cb9014be401136c3f07f220ef365. Change-Id: I99fe5111b5294673d9e0a5d13f9c240e0f4a92c3 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77516 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: <srinivas.kulkarni@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-28mb/google/rex/var/rex0: Enable BT offload audio for Intel MtP2 moduleAnil Kumar
Enable the required GPIO and FW_CONFIG support to configure BT offload audio in discrete mode for Intel Mysty Peak module on google/rex Proto2 HW. BUG=b:297125514 Test=Verified BT audio playback on google/rex Proto2. Change-Id: I560f1700f78f8b653dfcc2f26764f0ebf2652689 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77357 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-08-28mb/google/rex/var/karis: Remove UWBTyler Wang
According to the schematic, karis does not have a UWB, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I8a442518c2007cde883183871cef96db416850c0 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77437 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-26mb/google/rex/var/karis: memory: Add Micron MT62F512M32D2DR-031Tyler Wang
Add new memory part in the mem_parts_used.txt and generate the SPD ID. 1. MICRON MT62F512M32D2DR-031 WT:B BUG=b:291018417 TEST=emerge-rex coreboot Change-Id: I6e05c0d41a4899ed64dbab7efd8904cd361cb50e Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77426 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26mb/google/dedede/var/taranza: Add Wifi SAR for taranzaSheng-Liang Pan
BUG=b:297276380 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage Cq-Depend: chrome-internal:6373154 Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: If21c7a7d329b0b1cc2c73dadb0c5b8a5b8ab27e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77399 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2023-08-26mb/google/rex/var/karis: Remove WWAN moduleTyler Wang
According to the schematic, karis does not have a WWAN module, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I653e3b4fae8a53018a6004528d1cfb3a6c883687 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77427 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26mb/google/rex/var/rex0: Use FW_CONFIG to select the correct SAR tableSubrata Banik
This patch changes the SAR table selection logic to use FW_CONFIG which will eventually help to support different WiFi SAR tables. TEST=Able to build and boot google/rex. Change-Id: I8f1244e3c3715bc3fbe6be1ade87817ff19836de Signed-off-by: YH Lin <yueherngl@google.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77428 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26mb/google/nissa/var/yaviks: Disable SUSCLK based on fw_configWisley Chen
Disable SUSCLK for MT7922 based on FW_CONFIG to avoid power leakage. BUG=b:296511904, b:294456574 BRANCH=firmware-nissa-15217.B TEST=build and verified by EE Change-Id: I9a6bf0ab7cc77f95e0d64f1380eac9e022fc08e4 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77383 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-25mb/google/brask/var/kuldax: Set customized_leds value for RTL8111KDavid Wu
Set customized_leds value for RTL8111K to fix led can't work. BUG=b:297093096 BRANCH=firmware-brya-14505.B TEST=Verified RTL8125 and RTL8111K led can work normally. Change-Id: Icb8624005e7e24398abdd242570970c6bfa8a09f Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77390 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-25mb/google/brya: Create nokris variantChen-Tsung Hsieh
Create the nokris variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:285838647 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_NOKRIS Change-Id: If7cb00ce978236746dfe4d097d1f20aeebb96a35 Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-08-25mb/google/rex/var/ovis: Update PWM_BUZZER GPIO configJakub Czapiga
BUG=b:271491845 TEST=Build and boot google/ovis on Rex P1 with buzzer added on GPP_B08 Change-Id: I44718ea15c93a075b6468f335a869a2cfa585273 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76049 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-25mb/google/nissa/var/joxer: set the DB_USB field in FW_CONFIGMark Hsieh
Joxer will have SKUs with no type-c on daughter board, add fw_config for EC control it. BUG=b:297131468 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie8098f72e29a10ebbaf3ba3b09d6a002d09fd35a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77394 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-25mb/google/rex/var/karis: Add SOC_TCHSCR_INT settings to gpio tableTyler Wang
Karis use I2C touchscreen only, add SOC_TCHSCR_INT(GPP_C07) to ramstage gpio table. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ie715cfbe1984dbe38cd933312304b42ce9088806 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-25mb/google/rex/var/karis: Fix incorrect GPIO pad numbersKapil Porwal
Fix incorrect GPIO pad numbers. GPP_F19 was mistakenly used instead of GPP_F14, GPP_F15 and GPP_F16 GPIOs. BUG=none TEST=none Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I219b78a5e92d9c56799964ea88615c27aed2e92e Reviewed-on: https://review.coreboot.org/c/coreboot/+/77401 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24mb/google/dedede/var/boxy: Enable 100M mode blink in RTL8111H LAN LED configStanley Wu
Enable bit 9 for 100M mode green LED blink. Reference: - RTL8111H-CG Datasheet 1.92 section 7.2 for customizable led configuration BUG=b:293983804 TEST=emerge-dedede coreboot and verify LAN LED behavior Change-Id: Ice5686affcc014a2dfd35b7f579c8eaa38c2d3fe Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-08-24mb/google/nissa/var/yaviks: rename DB_NONE to DB_1AWisley Chen
Yaviks doesn't have none DB sku, and rename to DB_1A for yahiko. BUG=b:294928078, b:294456574 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Icb952c0716d446d5feb5580f357120a27193284e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77384 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24mb/google/brya/var/vell: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I62103563ec49769cd842fedf8c2c55118c55aa14 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/taniks: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I12fa83987869b9a52940a49e9f7897d62abf59ff Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/taeko: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I07e85f28c4f260d04317ec594e162db20f3d4ddd Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/volmar: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Ie7982d1001c4a65322b4e6fdbd70b20c8eee6f0e Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/primus: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I78eee4c5f11b06fbc104182a4313c20be91b821b Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76905 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24mb/google/brya/var/osiris: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I6157894b96da2e9faed229a1f18c0c0b7c60897b Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/omnigul: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Ie0304ea4343361ff0395c7204ebb76bffb5a6d97 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/mithrax: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Icdb8e9a20ab536f80fa7358472cca01996faf447 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/rex/var/karis: Disable GSPI0Tyler Wang
According to the schematic, karis does not have a SPI touchscreen, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I55eb9e3cebe426fcd023789831ce64a18d075d69 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-24mb/google/brya/var/marasov: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Ie2c089c0418f76ac7c8ce2e531dbbc91c66f34a0 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76901 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 19:49:55 +0000