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2023-01-05mb/google/brya/var/marasov: Disable FPMCU interfaceFrank Chu
Set fingerprint control GPIO to NC by HW design. BUG=b:264340020 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I304862f0dd201da100b89c79a473eb116fc8263e Reviewed-on: https://review.coreboot.org/c/coreboot/+/71650 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-01-05mb/google/brya: Create omnigul variantjamie_chen
Create the omnigul variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:263060849 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_OMNIGUL Change-Id: I6b4123db9cb77dc050a81f1cb83ef10e2fbffe8d Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-04Revert "mb/google/brya: Define a more suitable MRC training text message"Jakub Czapiga
This reverts commit e45f70423e5da8509bae83aba84b08f8fc0f624e. Reason for revert: Merged out of order, broke tree Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I38a7be6b94199d3a23e78114fb6708c535f241cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-01-04Revert "mb/google/brya: Add romstage early graphics for brya"Jakub Czapiga
This reverts commit 96d9b756690839c17b307a93b8a1898bd1c02ff5. Reason for revert: Merged out of order, broke tree Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Iac2d78f2d6c687f52dc720e8d8dcb5cf7a171c9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/71280 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04mb/google/brya: Define a more suitable MRC training text messageJeremy Compostella
This message is designed to reduce end-user confusion who may not know what memory training is. It also provides a maximum time estimation calibrated for brya devices. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=New message observed on skolas Change-Id: Ie71cd86746427789b3694d41224bf2c170af0f91 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70796 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04mb/google/brya: Add romstage early graphics for bryaJeremy Compostella
BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=On-screen text message seen during MRC training on skolas with a few extra patches Change-Id: I41c9cccb09dea52e2318f8f9ebeeda3697a7b513 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-01-04mb/google/skyrim/var/markarth: Generate RAM IDs for new memory partsJohn Su
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) BUG=b:263296326, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I4f00d444bd59443ecba29c6c155d676bab7a3d82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-04mb/google/skyrim: Create markarth variantChao Gui
Create the markarth variant of the skyrim reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:262092858 BRANCH=None TEST=util/abuild/abuild -p none -t google/skyrim -x -a make sure the build includes GOOGLE_MARKARTH Change-Id: Ifbace841ca56d8659aaffdc31fb2bc4367d96f82 Signed-off-by: Chao Gui <chaogui@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-01-04mb/google/nissa/var/yaviks: Disable external fivrWisley Chen
In next phase, yaviks will remove external fivr. Use the board version to config external fivr for backward compatibility and show message. BUG=b:263842258 TEST=build, boot to OS, suspend/resume work normally. Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Id85570046c5b8e9d90a112793c1ec8604e6bf533 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-01-04mb/google/rex: Configure EN_DMIC_SOC_DATA to GPO and LOWSubrata Banik
This patch configures GPP_H15 (EN_DMIC_SOC_DATA) as GPO and put into safe state aka LOW/PD. BUG=b:263411621 TEST=Able to build and boot Google, Rex to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3d376f895b2f0882c9fa6fe7b98686907bde4321 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71631 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04mb/google/brya/var/gaelin: Use RPL FSP headersMike Shih
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers for FSP. Since we use RPL FSP and it will support ADL as well, we rename "Gaelin4ADL" to "Gaelin". BUG=b:258603624 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot Cq-Depend: chrome-internal:5227091, chromium:4113361 Change-Id: Ie7349f3670aeec166228e7df55300cd30d0ca16c Signed-off-by: Mike Shih <mikeshih@msi.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-03mb/google/brya/var/lisbon: Update audio codec i2c timingKevin Chiu
Adjust audio codec i2c timing to 399 kHz. BUG=b:263050944 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I8495a88f2034e5e4ccf28ff53c81e0d6561e2e0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/70898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-03mb/google/skyrim/var/winterhold: Enable RTD3 support for eMMC as NVMeChris.Wang
winterhold/whiterun has different H/W topology to skyrim that the eMMC device is on a different GPP: skyrim: GPP1 -> SD winterhold : GPP1 -> eMMC BUG=b:263763288 BRANCH=none TEST=s0i3 stress over 2500 cycles. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ie6af4287057c6befa0b787ac28d7898166401b29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-01-03mb/google/samus: Set hidden flag for RT5677AA ACPI deviceMatt DeVillier
Coolstar's Windows drivers don't utilize it, and the Linux drivers don't care about _STA, so hide it from Windows to tidy up Device Manager. Change-Id: I2eb4b3aeed50b9f3ee9f73a57d6585068aa31fbb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-03mb/google/slippy/peppy: Set cypress TP IRQ to Level vs EdgeMatt DeVillier
Change the IRQ triggering from edge to level for cypress touchpad on peppy variant for compatibility with Windows drivers. TEST=boot Linux 5.x/6.x, Windows 10/11 on peppy, verify touchpad functional. Change-Id: Iecf6cb919bf16ec9180ca050e7eafe55247337ed Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02mb/google/drallion: Use runtime detection for touchscreensMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on drallion, verify touchscreen functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I67c3d1fc3d34e9b67ddb26afcaad3a47ffa92e2f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02mb/google/drallion: Set touchpad/screen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I1bdbf017bc7480f59cec85c70d6e71dac294dcd2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02mb/google/drallion: Implement touchscreen power sequencingMatt DeVillier
For touchscreens on drallion, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: I6825345f35a7415020e77edf781139f0c9b5f875 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02mb/google/drallion: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty implementation to be used in a subsequent commit for touchscreen power sequencing. Call method in romstage to program any GPIOs that may need to be set. TEST=tested with rest of patch train Change-Id: I0ad0c18a8b61e59a943a453882bf74762bac4700 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02mb/google/rex: Update USB2-C1 mappingSubrata Banik
This patch updates the USB2-C1 mapping from USB2 Port 4 to USB2 Port 1 as per latest Rex schematics dated 12/06/2022. TEST=Hardward awaited. Change-Id: Ifc82200e6eafcea7e820a96df81325f3c8849fd1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70426 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-02mb/google/rex: Remove USB2_8 ConnectionSubrata Banik
DCI interface deprecated for Proto1. USB2_8 port becomes no-connect. BUG=b:263494661 TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6f03d600acd8ceaa5a5630fc19c1c7e34a4ea28f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71237 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-02mb/google/rex: Revise config for the Proto 1 buildSubrata Banik
1. Rename DB_USB4 for KB8010 while adding ANX7452 as different DB_USB4 option. 2. Add audio component for Soundwire. 3. Rename MAX98357_ALC5682I_I2S to MAX98360_ALC5682I_I2S. Change-Id: I9f04c644b8a392feb2609f906bc9db945bf5fce2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70867 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-31mb/google/brya/var/gladios: Update audio codec i2c timingKevin Chiu
Adjust audio codec i2c timing to 399 kHz. BUG=b:262959586 TEST=FW_NAME=gladios emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I2f621e3af39fb40ab270c9de35d51dd43147b8f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-31Enable VBOOT_VBNV_FLASH for SOC_INTEL_BRASWELLYu-Ping Wu
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with VBOOT_VBNV_FLASH for boards using SOC_INTEL_BRASWELL. Currently BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is selected for CPU_INTEL_HASWELL, SOC_INTEL_BRASWELL and others (see [2]). However, there seems to be no particular reason on those platforms. We've dropped the config for haswell. Now do the same for SOC_INTEL_BRASWELL, so that VBOOT_VBNV_FLASH can be enabled. VBOOT_VBNV_FLASH is enabled for the following boards: - facebook/fbg1701: A 0x2000 RW_NVRAM region is allocated, with the FW_MAIN_A(CBFS) size reduced by 0x2000. - google/cyan, intel/strago: Repurpose RW_UNUSED as RW_NVRAM. [1] https://issuetracker.google.com/issues/235293589 [2] commit 6c2568f4f58b9a1b209c9af36d7f980fde784f08 ("drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config") BUG=b:235293589 TEST=./util/abuild/abuild -t FACEBOOK_FBG1701 -a (with VBOOT selected) TEST=./util/abuild/abuild -x -t GOOGLE_CYAN -a TEST=./util/abuild/abuild -x -t INTEL_STRAGO -a Change-Id: I46542c2887b254f59245f20b8642b023a7871708 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2022-12-31mb/google/rambi: Drop ChromeOS supportYu-Ping Wu
There is an ongoing effort to deprecate VBOOT_VBNV_CMOS [1] and replace with VBOOT_VBNV_FLASH. However, the rambi's CAR is too small for early flash access in romstage: /usr/local/google/home/yupingso/projects/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: Cache as RAM area is too full /usr/local/google/home/yupingso/projects/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: section .car.mrc_var VMA [00000000fe008000,00000000fe00ffff] overlaps section .car.data VMA [00000000fe000000,00000000fe008787] make: *** [src/arch/x86/Makefile.inc:194: coreboot-builds/GOOGLE_RAMBI/cbfs/fallback/romstage.debug] Error 1 More precisely, DCACHE_RAM_SIZE is 0x8000, and the current .car.data size is 0x76c0. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is unselected, then the _bss region will increase by 0x10c8 bytes (for global variables such as `elog_mirror_buf` and `sfg`), so that .car.data will exceed 0x8000. Since rambi has reached its AUE (2021-09-01), disable MAINBOARD_HAS_CHROMEOS and VBOOT configs. [1] https://issuetracker.google.com/issues/235293589 BUG=b:235293589 TEST=./util/abuild/abuild -t GOOGLE_RAMBI -a TEST=./util/abuild/abuild -x -t GOOGLE_RAMBI -a Change-Id: Id56795dd0653784b4d7141142ebef0b19a46ddc3 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71545 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-30mb/google/skyrim/var/frostflow: Update I2C setting for touchpadJohn Su
Update setting for touchpad I2C frequency. And meet touchpad i2c SPEC (380 ~ 400 kHz). BUG=b:261159229 TEST=On frostflow, touchpad i2c spec from EE measure Frequencies: I2C0 (Touchpad): 390.1 kHz Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ied00e43e87404489af2b570206a70b685e554b78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71564 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-28mb/google/brya/var/kuldax: Add wifi sar tableDavid Wu
Add wifi sar table for kuldax BUG=b:248367859 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Change-Id: I5ade590c739aae391e47e8bb66ee03c086e8d56e Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71270 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27mb/google/brya/var/kano: Enable Fast VMode for kanoDavid Wu
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP threshold. BUG=b:252966799 BRANCH=firmware-brya-14505.B TEST=Verify that the feature is enabled by reading from fsp log Change-Id: I15c3eea6ebb7f104bce0ba8cb544ecde7f488343 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27mb/google/rex: Enable PMC IPC configSubrata Banik
TEST=Able to build and boot Google/Rex. Device (PMC) { Name (_HID, "INTC1026") // _HID: Hardware ID Name (_DDN, "Intel(R) Meteor Lake IPC Controller") // _DDN: DOS Dev ice Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0B) } ... } Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I28c0153a770b36cde0653ac92d2e5ad1b8dd3449 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71268 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27mainboard/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I4f2f02623b060ef0ebefc5aceb713c77a8b1e9a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71523 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27mainboard/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: Id1078b14a805eea53d2a7c5a8183a5413f26e115 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71521 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27mb/google/brya/var/marasov: Add DmaProperty for ISHSubrata Banik
On Marasov, the ISH is running closed source firmware, so the ChromeOS security requirements specify it must be behind an IOMMU. Add DmaProperty to the ISH _DSD on Marasov. TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the IOMMU group type to "DMA". Also, device still goes to S0i3. Before: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 0 After: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 1 Change-Id: I4b65b8909c41b06852fe7771375029bd2e76e111 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71263 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27mb/google/brya/var/marasov: Remove ISH firmware-nameSubrata Banik
For marasov, the ISH main firmware will be included in the CSE region in flash instead of loading it from rootfs. So remove the ISH firmware-name. TEST=Boot to OS on Marasov UFS SKUs. Check ISH firmware is not loaded by kernel, and device still goes to S0i3. Change-Id: I278e5d403ef9515e538a527f43949e505d750bb1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71261 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyle Lin <kylelinck@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.com>
2022-12-24mb/google/rex: Enable DPTF functionality for Rexzhaojohn
Enable DPTF functionality for Meteor Lake Rex board. BUG=b:262498724 TEST=Booted to OS and verified DPTF entries in ACPI SSDT on Rex board. Change-Id: I87b2d71650be9ce940d9452bf4a76d4cd1ddba52 Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70884 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24mb/google/volteer/eldrid: Correct DDR4 SPDs for EldridJohnny Li
Correct DDR4 SPDs from H5AG36EXNDX019 to H5AG36EXNDX017. DRAM Part Name ID to assign H5AG36EXNDX017 0 (0000) BUG=b:236739240 BRANCH=Volteer TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: If248714088835eb5dd48fa12223c273199297228 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71160 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24mb/google/brya/var/zydron: Use SSFC for mipi instead of fw_configDavid Wu
Kano didn't use SSFC in mass production, however Zydron needs SSFC for 2rd source mipi instead of fw_config. BUG=b:262939431 TEST=Boot to OS and check functional with ov2740/hi556 camera. Change-Id: Idb2a35d67af0b5a7dedc66b0f7eccd8a3b4612d1 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-12-24mb/google/rex: Use GPP_C15 as WWAN_DPR_SAR_ODLSubrata Banik
BUG=b:263413949 TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I453fe8e1f4b4b8d4730ade259899d76aec949a44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71231 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-24mb/google/rex: Rename GPP_D07 to FPMCU_UWB_MUX_SELSubrata Banik
BUG=b:263412235 TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia444cc8e3666fe15479ece81d068f9e8f1d339ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/71228 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-24mb/google/nissa/var/craask: Use get_wifi_sar_fw_config_filenameEric Lai
Use get_wifi_sar_fw_config_filename to remove the duplicate code. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I04176fee373e534d42c72506df73a092ad55e65b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-24mb/google/volteer/var/lindar: Use get_wifi_sar_fw_config_filenameEric Lai
Use get_wifi_sar_fw_config_filename to remove the duplicate code. WIFI_SAR_CBFS_DEFAULT_FILENAME is not exist, so return the non-exist id has the same outcome. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib34e6b4f435880d62936ae54f19ba2ec752eced2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-24mb/google/brya/var/taeko: Use get_wifi_sar_fw_config_filenameEric Lai
Use get_wifi_sar_fw_config_filename to remove the duplicate code. WIFI_SAR_CBFS_DEFAULT_FILENAME is not exist, so return the non-exist id has the same outcome. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib7a764d8cc3160c26abad9c1757812b955bef066 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-24mb/google/nissa/var/pujjo: Use get_wifi_sar_fw_config_filenameEric Lai
Use get_wifi_sar_fw_config_filename to remove the duplicate code. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ifde714c19f7ab9fe08f870060037db190a80dbd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-23mb/google/poppy: Use runtime detection for touchscreens/digitizersMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens/digitizers. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on all poppy variants, verify all touchscreens functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I4c1d8ae8c41c1f4283718a86fccbf5ae4fc399b6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70921 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb/google/poppy: Set touchpad/touchscreen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: Iee01dac943b6c2955f7af42ce0e9395fc609682f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70920 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb/google/poppy: Implement touchscreen,digitizer power sequencingMatt DeVillier
For touchscreens/digitizers on poppy variants, drive the enable GPIO high and hold in reset in romstage, then release from reset in ramstage. This will allow coreboot to detect the presence of i2c touchscreens/digitizers during ACPI SSDT generation (enabled in a subsequent commit). TEST=tested with the rest of patch train Change-Id: I90ac4f09c343a28328f7d30254f0448cbe0c78b3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-23mb/google/geralt: Pass SD card detect GPIO to payloadsLiju-Clr Chen
1. Add an option for SD card initialization. 2. If CONFIG SDCARD_INIT is configured, pass SD card detect GPIO to payloads for SD card detection and initialize MSDC for SD card configuration. BUG=b:244250437 TEST=build pass Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Change-Id: I2d3683eb673f438c9190c11d4679a3ca97c76a98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71136 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-23tree: Replace And(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `And (a, b, c)` with `c = a & b`, respectively `c &= b` where possible. Change-Id: Ie558f9d0b597c56ca3b31498edb68de8877d3a2f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70850 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace ShiftRight(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `ShiftRight (a, b, c)` with `c = a >> b`. One case was simplified to just `a >> b`. Change-Id: I889012b0a3067138e6f02d3fe8e97151effb5c2a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70840 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-23mb/google/poppy/nocturne: Fix touchscreen reset GPIO configMatt DeVillier
The touchscreen reset GPIO is configured as PAD_CFG_TERM_GPO with an internal pull-down, which puts it in a state of contention when the reset pin is released / set to high. Fix this by changing the reset GPIO to PAD_CFG_GPO like all other poppy variants use for the touchscreen reset. TEST=build/boot nocturne, touchscreen still works. Change-Id: I1ad4bb9d4194485990f54ffa7bae05f5c9a39deb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71185 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb/google/sarien: Add default fmap for non-ChromeOS buildsMatt DeVillier
Test: build/boot google/sarien with non-ChromeOS build, edk2 payload. Linux 5.15, Windows 11 tested. Change-Id: Ibc1857e6b120b0bb827ed610981c4d2bf8f78d1f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23mb/google/hatch: Use runtime detection for touchscreens/digitizersMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on multiple hatch variants, verify all touchscreens functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I2eae486eaa5e42cfe42ecc066a58b09fe2bd9138 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71062 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb/google/hatch: Set touchpad/screen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I580348d0aabb24f0241d6e9992c5a17942bd57ab Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23mb/google/hatch/*: Add missing enable GPIO for ELAN touchscreensMatt DeVillier
Some ELAN touchscreens were missing the entries for the enable GPIO and associated delays. Add them to variants with ELAN0001 touchscreens missing the entries. TEST=tested with rest of patch train Change-Id: I9ce81ad6ee8183c522d05fbe3f57af87e5895df3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-23mb/google/hatch: Implement touchscreen power sequencingMatt DeVillier
For touchscreens on hatch variants, drive the enable GPIO high starting in romstage, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: I86c5f41b7820eaf5252c276ae854a4206e09385f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71059 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb/google/hatch: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty weak implementation to allow variants to override as needed for touchscreen power sequencing (to be implemented in a subsequent commit). Call method in romstage to program any GPIOs the variant may need to set. TEST=tested with rest of patch train Change-Id: I1939387b5bb98d6d282fd044e9ce8780dbe0d2c5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23mb/google/poppy/rammus: disable USB xDCIMatt DeVillier
With xDCI enabled, the right USB-C port does not work for USB data. Additionally, it was disabled in stock ChromeOS firmware. TEST=build/boot rammus, confirm right USB-C port works for booting, under OS in Windows/Linux. Change-Id: Ie343577d772563fa7d432b62aa8faa41d760102a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23mb/google/zork: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on berknip/morphius, verify all touchpad functions work correctly. Change-Id: I9d8362719ddbfe523dd83964556b05bb8f1bb1ba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23mb/google/volteer: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on lindar, verify all touchpad functions work correctly. Change-Id: If2deedbd572b771c1e7793a3b3c37a3114aa2a48 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/reef: update ACPI HID/CID for Synaptics touchpadMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on coral, verify all touchpad functions work correctly. Change-Id: I161eb953bf8bceb353cf43803ee948c522928892 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/poppy: update ACPI HID/CID for Synaptics touchpadMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on nami, verify all touchpad functions work correctly. Change-Id: I0611da8bbea41565e603a1a1b7cc20226ba21c62 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/hatch: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on bobba, verify all touchpad functions work correctly. Change-Id: I4fd66be21eeff5f37b58a8922c49683a28685064 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/kahlee: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on liara, verify all touchpad functions work correctly. Change-Id: I89ca02629803882e7ed2048a5a26868fc2de41a9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/hatch: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on akemi/kohaku, verify all touchpad functions work correctly. Change-Id: Icb552caa69428908e5e3342139b578a145fa2797 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/guybrush: update ACPI HID/CID for Synaptics touchpadMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot ChromeOS, Linux 5.1x, Windows 10 on dewatt, verify all touchpad functions work correctly. Change-Id: I00efde6f007d57166cd82f76d2f389dedce57466 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/dedede: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on drawcia, verify all touchpad functions work correctly. Change-Id: I43eb5bc394a3fbfd4109f2e6c274ec66fc01d46d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/brya: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=untested on brya, but tested under Windows/Linux on all other boards in the tree using Synaptics touchpads. Change-Id: Ia9351185b918f2d6f2d2be110b88e8310d37a03f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/volteer: Add missing audio codec to HDA probeMatt DeVillier
Audio codec RT1011_ALC5682I_I2S is listed as a fw_config option in the baseboard, but missing from the HDA device probe list in the variant overridetrees, preventing it from being detected at boot. TEST=build/boot lindar, verify audio codec identified and HDA device not disabled by fw_config. Change-Id: Ib40b095688aac5cf4e0a60dcac250023c4f04c9f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/reef: Use runtime detection for touchscreensMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on multiple reef variants, verify all touchscreens functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I8c90074515b1c7d3ab742768d7bbd904fec256d4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71154 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22mb/google/reef: Set touchpad/screen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I1000df10eea5670bf1bc8d04c736150b6a5e26a1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/reef: Implement touchscreen power sequencingMatt DeVillier
For touchscreens on reef variants, drive the enable GPIO high starting in romstage, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). As the GPIOs are already correct in ramstage, only the romstage ones need to be set. BUG=b:121309055 TEST=tested with rest of patch train Change-Id: I10d1789c8de23653bac81e1f9604a47f93fa3f7d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71152 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22mb/google/reef: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty weak implementation to allow variants to override as needed for touchscreen power sequencing (to be implemented in a subsequent commit). Call method in romstage to program any GPIOs the variant may need to set. TEST=tested with rest of patch train Change-Id: Id3ab412183e5c5d534b2e1dea3222c729c25118b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/volteer: Use runtime detection for touchscreensMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on multiple volteer variants, verify all touchscreens functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I0448d12a36f522b715e1fbeb8d37eb5a925ebc93 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71183 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22mb/google/volteer: Set touchscreen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I269361f90a838d7766ad429afe82ef885f0d9371 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71182 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22mb/google/volteer: Implement touchscreen power sequencingMatt DeVillier
For touchscreens on volteer variants, drive the enable GPIO high starting in romstage, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: Ie4c3b94594253ced6a875af78e6390cda8dcbc7d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71181 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22mb/google/volteer: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty weak implementation to allow variants to override as needed for touchscreen power sequencing (to be implemented in a subsequent commit). Call method in romstage to program any GPIOs the variant may need to set. TEST=tested with rest of patch train Change-Id: Ib3c2a0e849006b7bf70cbd0bf6f32aa01ccf1bc4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71180 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22mb/skyrim/var/frostflow: enable dptc tablet mode switchChris.Wang
add dptc power parameter for tablet mode sustained_power_limit_mW_tablet : 12w BUG=b:257187831 BRANCH=none TEST= validate the parameter changes for each mode by AGT Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I22d3f9c79a1eaaccfbef3766019516edb3523964 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70674 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
2022-12-22mb/google/nissa/var/yaviks: Extend sd_hold for touchpad/touchscreenWisley Chen
Extend sd_hold to meet touchpad/touchscreen SPEC. touchscreen: tHD > 0.2 us touchpad: 0.3 us < tHD < 0.9 us After applied the change, the tHD meets reqirement. touchscreen: 0.056 us -> 0.28 us touchpad: 0.056 us -> 0.384 us BUG=b:263340540 TEST=build and measure the timing meet SPEC Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I172d2ec8a4b16d8005106f55a37795cc72d69e98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-22mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization errorLeo Chou
Configure eMMC DLL tuning values for Pujjo board Kioxia sku. BUG=b:261676386 TEST=Use the value to boot on Pujjo successfully. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I46991f26571771620dcd94b90e1112484ade63bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/71129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-12-21mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKENick Vaccaro
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers for FSP as kano is using a converged firmware image. BUG=b:253337338 BRANCH=firmware-brya-14505.B TEST=Cherry-pick Cq-Depends, then "FW_NAME=kano emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage", disable hardware write protect and software write protect, flash and boot kano in end-of-manufacturing mode to kernel. Cq-Depend: chrome-internal:5246998, chromium:4119763 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Change-Id: I30ab7d829a6cb45b4e0cd38747501ba0eb6bd6cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/71175 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21soc/intel/skl; mb/google/eve,poppy: Update NHLT methodsMatt DeVillier
Adapted from WIP (and now abandoned) patches CB:25334, 26308, 26309. Update the nhlt_soc_add_*() methods for max98373, max98927, and rt5514 codecs to program the render and feedback slot numbers as appropriate. TEST=boot Windows on google/eve, atlas, nocturne, and rammus. Verify audio functional with both Google project campfire drivers as well as coolstar's AVS audio drivers. Change-Id: Ib8c6e24ba539e205bd5bbd856ecff43b2c016c2e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com>
2022-12-21mb/google/octopus: Use runtime detection for touchscreens/digitizersMatt DeVillier
Switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens and digitizers. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. Test: build/boot Windows/Linux on various octopus variants, verify touchscreens/digitizers functional, dump ACPI tables and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I67c5bbae42e96ae21d37309e382b635321e6ef01 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63214 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/google/octopus: Set touchpad/screen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I13bc6920a0dfaf769091b1764a7584902d1f85d6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63213 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/google/octopus: Implement touchscreen/digitizer power sequencingMatt DeVillier
For octopus variants with a touchscreen/digitizer, drive the enable and reset GPIOs high in romstage, then disable the reset GPIOs in ramstage. Where available, only set the GPIOs for SKUs which have a touchscreen. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). TEST=tested with rest of patch train Change-Id: Ia725b4054069c0a4f60afd7e0bca6e2fd5fdcbba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63212 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/google/octopus: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty weak implementation to allow variants to override as needed for touchscreen power sequencing (to be implemented in a subsequent commit). Call method in romstage to program any GPIOs the variant may need to set. TEST=tested with rest of patch train Change-Id: I4a8e11945ae64b000051989089e0ebae22896c6b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70905 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/google/skyrim: Fix Bluetooth configurationKarthikeyan Ramasubramanian
Power resource for Bluetooth device is not configured correctly in the device tree. Fix Bluetooth devicetree configuration. BUG=b:262785310 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the DUT is able to connect to a Bluetooth headset. Change-Id: Id980424349537be35860dec04cc823d419cefe2f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71068 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20soc/amd/mendocino: add dptc tablet mode supportChris.Wang
add dptc support for different power parameter on tablet/clamshell mode. BUG=b:257187831 BRANCH=none TEST=validate the parameter change for each mode by AGT. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I96e04d113d18b42f3457056a5e4fa311ceccffb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-12-20mb/google/skyrim/var/frostflow: Config I2C frequency for touchpad.Rex Chou
1.Config setting for touchpad I2C BUG=b:261159229 TEST=On frostflow, touchpad i2c spec from EE measure Frequencies: 1.I2C0 (Touchpad): 385.7kHz Change-Id: I4ca72ee7fabd4b641eb17451ed8d942c5df52dde Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-12-19tree: Replace XOr(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `XOr (a, b, c)` with `c = a ^ b`, respectively `c ^= b` where possible. Change-Id: Ic5f67684bbd4ea115c4dae8a4417d88bea0d6b77 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70843 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-19mb/google/octopus: Add NHLT endpoints for Cirrus Logic codecMatt DeVillier
Add NHLT endpoints for octopus boards using CS42L42 codec. Reuse method to add da7219 endpoint as the routing is identical. TEST=boot Windows, verify audio working with coolstar's audio drivers. Change-Id: Id68997073752f5d90b6fe21f666a6140e22d65eb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-19mb/google/octopus: update variant VBTsMatt DeVillier
Remove flag in VBTs for 'Use fixed resolution at boot' to allow FSP/GOP display init to use native panel resolution instead. TEST=build/boot multiple google/octopus variants with edk2 payload, verify boot logo not distorted/stretched. Change-Id: Ia31ff28379282619dfa22a955bee1a768bb54bb8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-19mb/google/hatch/kohaku: set VBT boot resolution to 1080pMatt DeVillier
Boot menus are too small at native 4K res on some panels, so set fixed display resolution to 1920x1090p TEST=build/boot KOHAKU with 4K display, verify boot menu text legible. Change-Id: I82563c83de7ab302151f60d86b8a6824330d03ea Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-19mb/google/brya/var/marasov: Configure I2C high and low timeFrank Chu
Adjust I2C speed for codec, TPM, touchpad, touchscreen. BUG=b:260565911 TEST=Built and verified adjusted I2C speed Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Idcec6e401992d30dff01940c50473cba48cffc19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
2022-12-17mb/google/nissa/var/yaviks: Enable wifi SARWisley Chen
Enable wifi sar function for yaviks. Use the fw_config to separate SAR setting for different wifi card. BUG=259199095 TEST=build, enabled iwlwifi debug, and check dmesg Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I3ced65368ee66e084e58d66cff8f75147f665d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-12-17mb/google/nissa/var/pujjo: Tunning RegProxCtrl0 register for SX9324Stanley Wu
Update SX9324 RegProxCtrl0 register settings based on tunning value from P-sensor vendor. BUG=b:242662878 TEST=i2cdump -y -f 13 0x28 on Pujjo Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: If471a6fee5a3daeac1958709415b2d5e1329b81b Reviewed-on: https://review.coreboot.org/c/coreboot/+/70824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-12-17mb/google/skyrim: Configure RO and RW SPL filesKarthikeyan Ramasubramanian
This will help to integrate RO SPL table in RO partitions such that it is used before PSP verstage is loaded. After PSP verstage, SPL table in RW partition gets used. BUG=b:243470283 TEST=Build Skyrim BIOS image and boot to OS. Change-Id: Ic2061f66381d7e9a8018e6f28aa0bc2ca6010f6f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70777 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-16mb/google/brya/var/lisbon: Use RPL FSP headersKevin Chiu
To support an RPL SKU on lisbon, lisbon must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for lisbon so that it will use the RPL FSP headers for lisbon. BUG=b:246657849 BRANCH=firmware-brya-14505.B TEST=FW_NAME=lisbon emerge-brask intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage flash and boot lisbon to kernel. Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Ie60c357ef0a2af2fec90df4a54e56f51ceb927d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-16mb/google/brya/var/marasov: Update gpio table for EVTFrank Chu
BUG=b:260565911 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Id5a73126737a3abbe6f0ef37276ce20f687b47fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/70236 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-12-16mb/google/brya/var/marasov: Disable unused PCIE8 for s0ixFrank Chu
Disable unused PCIE8 for fix system can not enter S0ix completely. BUG=b:261915226 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I06f8bd06e1fe92c03bd5625a41469830ce37a11c Reviewed-on: https://review.coreboot.org/c/coreboot/+/70660 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-16mb/google/geralt: Revise the naming of MIPI PWM control GPIOLiju-Clr Chen
Rename the MIPI PWM control GPIO to be consistent with the schematic. BUG=b:244208960 TEST=test firmware display pass for eDP and MIPI panels on MT8188 EVB Change-Id: I6a3368d438cb50b257992260d1388f0b7e0f5ace Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70822 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-16mb/google/geralt: Pass GPIOs to allow backlight control in payloadsBo-Chen Chen
There are two ways to control backlight in geralt: 1. MIPI/eDP panel => control backlight via the GPIOs. (`backlight chip enable` and `PWM dimming control`) 2. eDP OLED panel => enable backlight via `backlight chip enable` and control dimming over AUX. For MIPI/eDP panels(#1), both "backlight enable" and "PWM control" GPIOs will be passed from coreboot. For eDP OLED panel(#2), only the "backlight enable" GPIO will be passed. If depthcharge successfully gets the GPIOs, it will use them to control backlight. BUG=b:244208960 TEST=test firmware display pass for eDP and MIPI panels on MT8188 EVB Change-Id: I866fa219722241008e2b0d566b29edf2f6d9321f Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70744 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 12:55:04 +0000