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Replace `3` with `SaGv_Enabled`, which has the same value.
Change-Id: I05cfddfefc45ba5bfb0e684445a6d8e02d7865e3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Create the volet variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:186334008
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_VOLET
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ic6ca9a78494e3819b0fb39c0bcc70fed95c2c589
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Configure Chromebook specific GPIOs, including EC_AP_INT,
SD_CD, EC_IN_RW, GSC_AP_INT and EN_SPK.
Change-Id: Id553f632412af440d21a3b51e017cb74cc27fd22
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52924
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add SPD support to elemi for K4AAG165WB-BCWE
BUG=b:187379245
TEST=FW_NAME=elemi emerge-volteer coreboot chromeos-wqbootimage
Change-Id: I839447a9e7c7b6558b2d0877c67dc9cf89ee792a
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Mancomb uses DDR4 SODIMMs, but the default cezanne configuration is for
the LPDDR4 version. This changes to use SODIMMS.
Further changes may be needed for platform customization, so I put the
config file in variants/baseboard instead of the root mancomb directory.
BUG=b:187094481
TEST=Build only
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Icc4dc8aec2053cb177765f57e57cac7a099508fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This patch was implemented on Guybrush at CB:52352
BUG=b:185397933
TEST=Build
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I141a504a827f37724fab0aaed7498fd543e471d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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DISABLE_KEYBOARD_RESET_PIN - This pin goes to a test point and is not
used for the reset.
DRIVERS_UART_ACPI - Add the UART ACPI code
FW_CONFIG - Mancomb uses the firmware config interface
PSP_DISABLE_POSTCODES - The PSP is not yet initializing eSPI correctly
to send post codes to the EC, so disable them for now.
BUG=None
Test=Build
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I39efcc8d1e0fb1e7ac0b0541a49db0ac0ee56481
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This change fixes two problems:
1) We had the enum values for .direction and .level swapped. The naming
is very confusing...
2) ESPI_SYS is not a good event to use for EC SCI. It is a level/low
event that is only cleared by reading the eSPI status register 0x9C.
Cezanne has added a new event source that directly exposes the SCI bit.
This is the correct event source to use for EC SCI.
This same patch was added for Guybrush at CB:52673
BUG=b:186045622, b:181139095
TEST=Build
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iac86d2ef5bdd21fbb0a0d4e235efe4fe621023b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52948
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This matches what we are doing on guybrush.
BUG=b:187122344, b:186135022
TEST=build
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id61de28cd0ee762693b287b29bdd7605d4176929
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52956
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Using the push-pull alert was causing leakages when in S0i3. This is
because the EC drives ALERT#, so when the AP enters S0i3, the extra
current leaks into the SoC and ends up turning on the power regulators.
By using in-band ALERT#, the EC no longer drives this pin high, thus
fixing the leak. We could also have used an open drain alert, but the
rise time is less than ideal.
BUG=b:187122344, b:186135022
TEST=Measure S0i3 power on guybrush and validate it's no longer high.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6de771aeda8feca062652f0ea9eb57d31cb68562
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Some designs might wish to use an open drain eSPI ALERT#. This change
adds an enum that allows setting the eSPI alert mode.
BUG=b:187122344, b:186135022
TEST=Boot guybrush using all 3 alert modes
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia35fc59a699cf9444b53aad5c9bb71aa27ce9251
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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BUG=b:186380809
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.
Change-Id: I0975a8b64452c3f636e6c5937c6918518ec5b4e9
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
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TGL boards using the Type-C subsystem for USB Type-C ports without a
retimer attached may require a DC bias on the aux lines for certain
modes to work. This patch adds native coreboot support for programming
the IOM to handle this DC bias via a simple devicetree
setting. Previously a UPD was required to tell the FSP which GPIOs were
used for the pullup and pulldown biases, but the API for this UPD was
effectively undocumented.
BUG=b:174116646
TEST=Verified on volteer2 that a Type-C flash drive is enumerated
succesfully on all ports. Verified all major power flows (boot, reboot,
powerdown and S0ix/suspend) still work as expected.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Create the pirika variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:184157747
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_PIRIKA
Signed-off-by: kirk_wang <kirk_wang@pegatron.corp-partner.google.com>
Change-Id: I57bf33deeadacc88800f9ce1d3d54385ba56c798
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52626
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Pen Detect GPIO is exported through GPIO keys driver to the kernel so
that stylus tools is popped on pen eject event. Hence enable the GPIO
keys driver and configure the devicetree.
BUG=b:186011392
TEST=Build and boot to OS in guybrush. Ensure that PRP0001 device is
added to the ACPI SSDT table. Ensure that the Pen Eject events are
detected.
Event: time 1620159356.243180, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: time 1620159356.243180, -------------- SYN_REPORT ------------
Event: time 1620159356.735316, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Ensure that when the device is suspended, it wake on Pen Eject event and
does not wake on Pen Insert event.
Change-Id: I4d2aa29c0f1839c563b40734527a687a5618ba5c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Using PAD_WAKE is actually wrong. The wake bits are only supposed to be
set when using the GPIO controller to wake the system. coreboot's
current architecture relies on using GPEs to wake the system.
BUG=b:186011392
TEST=Wake system from S0i3 with EC and see GPE 3 increment.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If7f9d2c13503c01fb9d834c436dac723f2c3b24c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Now the bootblock is not limited to 64K so integrating vboot into the
bootblock reduces the binary size.
Change-Id: Ic92ecf8068f327a893d20924685ce571752d379f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52787
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=boot to romstage on MT8195 EVB
Change-Id: I356e6b1cba3c078bf99e056b290476c7179e8ccf
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I2eeddb44b5495d05602c995a6103a56b09cf126a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Configure GPP_A20 as PAD_CFG_GPI_IRQ_WAKE to enable interrupt and wake routes for touchscreen device.
BUG=b:186070097
BRANCH=puff
TEST=Build and make sure TS works to wakeup suspend/resume.
Change-Id: I2bbaab56924849a22a4d05ce53bf5bdcf00265dd
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Modify reset pin setting to ACPI_GPIO_OUTPUT_ACTIVE_LOW for
ELAN and Weida touchscreen.
BUG=b:180547621
BRANCH=dedede
TEST=Build the cret board and touchscreen is workable.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I912fe8a0e18a4c3527fb8587592b855c93b12406
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Disable HDMI 2.0 for Vilboz and then support display resolution 4K 30Hz
BUG=b:179170193
BRANCH=firmware-zork-13434.B
TEST=verified that the resolution of the display is 4K 30Hz
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ib0dc0d584f0e87bc9c3da85a583cb8c8bed76440
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Using PAD_WAKE is actually wrong. The wake bits are only supposed to be
set when using the GPIO controller to wake the system. coreboot's
current architecture relies on using GPEs to wake the system.
BUG=b:186011392
TEST=none
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib956fc299fe21cd7ea0b465cbdc5c8da830a668d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Default VBT supports only integrated Display port. Magister supports a
HDMI port and hence support a separate VBT for Magister.
BUG=b:180666608
BRANCH=dedede
TEST=Build and boot to OS.
Cq-Depend: chrome-internal:3661227
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I52c10452887312959f68cfc4e25d5897dae388f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51279
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Select GOOGLE_SMBIOS_MAINBOARD_VERSION allows querying
board revision from the EC.
BUG=b:186721096
TEST=1. emerge-brya coreboot chromeos-bootimage
2. flash the image to the device and check board rev
by using command `dmidecode -t 1 | grep Version`
Change-Id: I8eeb958f73607afb801794f91fbf91ec7bd5cd8b
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Mancomb will have the boot flash on a daughterboard, so the SPI speeds
need to be low for now.
BUG=b:182211161
TEST=Build
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Icacb68d65fb414197d7b8d45799527d8d2568dc7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Guybrush is pretty definitely alive, so this can be removed, as the
TODO line said.
BUG=180721202
TEST=Build
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I14f89f3e6f780c2da2136a838950ef2bcebc4c3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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There is no lid switch in mancomb so remove it.
Will replace the lid switch with a fake gpio in depthcharge.
BUG=b:182211161
TEST=Depthcharge no longer halts complaining that coreboot didn't sample
the pin
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Ifd0fcec9557bf7ebad64ce9342d3b50eb511522b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The usage of external oscillator has got nothing to do with Audio
Co-processor (ACP). Hence move it out of common config and put it into
the SoC config where it is being used.
BUG=None
TEST=Build Dalboz and Vilboz mainboards.
Change-Id: I8c5d98addfba750f9ddb87a846599541b4a8340a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Update the telemetry setting for guybrush
vddcrvddfull_scale_current : 92165 #mA
ddcrvddoffset : 412
vddcrsocfull_scale_current : 30233 #mA
vddcrsocoffset : 457
BUG=b:182754399
TEST=Build, boot to guybrush
Change-Id: Ib92bb169693634665fc8e165837e7ae3e6137bcf
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52736
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow the FP6 IRM(#56328) to set the stapm parameter
and allow other mancomb variants boards can customize those parameters.
BUG=b:1181157669
TEST=build.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ib3ed76e5212a5a8b5fb4fcc3d6884ceff82377b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The boolean is stored in ChromeOS NVS, not GNVS.
Change-Id: I5c424a052d484228a456f8f0ad4fb0bed3165e09
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Because galith/gallop both non-suport tablet mode,
remove un-use fw_config conditional.
BUG=b:176206495
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ic9bb76c207ef033f81ecdd57849535b8ac8d13ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52565
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Brya uses CBI to store dram part number. So enable the config.
BUG=b:186571840
BRANCH=none
TEST=dmidecode -t 17 can show the dram part number.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1b4fc4da31d8964763c3e671d84be71996fa5e2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Modify touchpad I2C sequence to meet requirement.
BUG=b:186372071
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot chromeos-bootimage
build Pass
And check the touchpad I2C5 sequence by EE.
Change-Id: I9d4dcc764edfbdc14eef5ad82db20e40b31de295
Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52690
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to SED team provided ELAN touch screen SPEC. IRQ trigger
method need set with level trigger, that modify IRQ trigger to level
from edge.
BUG=b:174972088
TEST=Build FW and boot to OS and check with test result.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I9237d9aad6166a5754afe464ce8453129a58d283
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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guybrush and mancomb don't configure any GPIO as PAD_SMI. Since
mainboard_smi_gpi will only get called for a GEVENT that will cause a
non-SCI SMI, this isn't expected to be called. For the unexpected and
very unlikely case that it still does get called, put a printk into
mainboard_smi_gpi to see what is happening there.
TEST=none
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd6e3348ecc078932bf6cf5b0830b4b034d274bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52360
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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zork doesn't configure any GPIO as PAD_SMI. Since mainboard_smi_gpi will
only get called for a GEVENT that will cause a non-SCI SMI, this isn't
expected to be called. For the unexpected and very unlikely case that it
still does get called, put a printk into mainboard_smi_gpi to see what
is happening there.
TEST=none
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I14c67b21a83b334558cdd54ebf700924aa9d0808
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52359
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure Audio Co-processor(ACP) to operate in I2S TDM mode. Also fix
the scope in which ACP is defined in the devicetree.
BUG=b:182960979
TEST=Build and boot to OS in Guybrush. Ensure that the ACPD device is
enabled in the appropriate scope in SSDT.
Change-Id: Ic90fd82e5c34a9feb9a80c4538a45e7c2fb91add
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Audio Co-processor driver is similar for both Picasso and Cezanne SoCs.
Hence move it to the common location.
BUG=None.
TEST=Builds Dalboz, Trembyle, Vilboz, Mandolin and Bilby mainboards.
Change-Id: I91470ff68d1c183df9a2927d71b03371b535186a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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All guybrush boards should have system_configuration set to 2, so
put this in the main devicetree.
BUG=b:185209734
TEST=Build & Boot guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I1ce2acb3b4ed51aa9a0aa379ed125f0b04f04d31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: chris wang <Chris.Wang@amd.com>
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From ANX7625 spec, the delay between powering on power supplies and GPIO
should be larger than 10ms. Since it takes about 4ms for the previous
GPIO EN_PP3300_EDP_DX to be pulled up, increase the delay from 2ms to
14ms.
BUG=b:157716104
TEST=emerge-asurada coreboot
BRANCH=asurada
Change-Id: If73747bdaec5ac069b048920d27e27178bc3cedc
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Enable ELAN9050 touch screen. Follow below spec:
eKTH7913U_eKTH7915U_eKTH7918U_Product Spec_V1.0_20200807 IPM-11
BUG=b:186342801
TEST=touchscreen is functional in the OS.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I4c247fae33b9178c8706552aba2f950c9a674ecc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Follow L850GL spec to adjust power sequence. RST need to drive low
before power on then drive to high.
SPEC:FIBOCOM_L850-GL Hardware User Manual_V1.0.8
BUG=b:186374631
TEST=WWAN is detected by lsusb.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I13357677bb1ab185abf1d4c915a762a9d6894312
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This changes adds the EC_HOST_EVENT_USB_MUX to be dark resume source.
BUG=b:183140386
TEST=In S0ix, remove DP dongle, system does dark resume. AP and EC
synchronized. AP got port partner disconnection.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I53bd4fee21e2e2d1f16f558ab0341a50ef9a0e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52716
Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Define TOUCH_RPT_EN pin(GPP_A11) as the stop_gpio for the touch screen
and control TOUCH_RPT_EN pin to keep low.
BUG=b:176253069
TEST=Build and boot metaknight to OS, confirm GPP_A11 pin keep low.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I816e29eccac0f1935aeaa3b94c907870e2451e3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52653
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Brya uses CNVi WiFi module, PCIE setting is not required.
TEST=WiFi is functional in the OS.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib82c98905ed3b30075e9830c1a2638817f140abe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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This change fixes two problems:
1) We had the enum values for .direction and .level swapped. The naming
is very confusing...
2) ESPI_SYS is not a good event to use for EC SCI. It is a level/low
event that is only cleared by reading the eSPI status register 0x9C.
Cezanne has added a new event source that directly exposes the SCI bit.
This is the correct event source to use for EC SCI.
BUG=b:186045622, b:181139095
TEST=`lpc sci` on EC console and see /proc/interrupts increase by 1
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I764b9ec202376d5124331a320767cbf79371dc07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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Roll back CPU slow slew rate setting to Intel default "SLEW_FAST_2"
Because baseboard modify slow slew rate setting to "SLEW_FASE_8"
for all project, but Lindar and Lillipup is using "SLEW_FAST_2",
so this setting need to roll back.
BUG=b:186140230
TEST=Build FW and boot to OS checking with CPU log.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I7de252b26c75f8dad218f3eb79a0988e60964f4c
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52620
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This enables STAPM power management. Values follow the AMD
specification.
BUG=b:185209734
TEST=Build & Boot guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ib9f2ec9a8ac118c55ae53b9419ea4ff74ce7b599
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: chris wang <Chris.Wang@amd.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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This adds the Mancomb APCBs into the AMD firmware binary.
BUG=b:182211161
TEST=Build and check log showing APCB sources present.
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Ifdf1e813fce6f93378c2495cf76bdace81d87c16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52600
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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To train PCIe devices, the devices need to be enabled and taken out of
reset. This patch does the bare minimum needed to train PCIe. It is
not intended to handle timings, which will be addressed later.
Copy the enables for WLAN into early GPIO Init so that they're
enabled before FSP-M runs and trains the PCIe busses.
Again, this patch is the minimum to let the FSP train the PCIe busses.
BUG=b:182202136
TEST=Boot guybrush from NVME.
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I5e3e9fe21f44b832e26b0942759ae2ec96ec6c82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
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Add dynamic fan table mechanism for Lindar and Lillipup.
Create different fan tables that provided from thermal team.
BUG=b:185308432
TEST=Build FW and boot to OS modify CBI test with DPTF tool.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I1b79dbe1ae6ee7aa41cef832b4ee305cc8f4b753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
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BUG=b:185939089
TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the
sleep state configuration from the mainboard.
Change-Id: I4b23b014ca45bd09c76b626b73b0332586dec056
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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Enable GL9755 SD card reader.
BUG=b:185397257
TEST=SD card is functional in the OS.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib3be54274ca796bedda76ce807a0bd630d1d8e4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Currently, it fails to dump the nvme data by test command.
It reports the following error:
cat: '/sys/bus/i2c/devices/i2c-PRP0001:01/eeprom': Connection timed out
So increase the value from 0x0400 to 0x2000 and double the address width from 0x08 to 0x10 to solve this problem.
BUG=b:177393430
TEST=1. cat /sys/bus/i2c/devices/i2c-PRP0001:01/eeprom > /tmp/ov8856_eeprom.bin
2. hexdump -C /tmp/ov8856_eeprom.bin > ov8856_eeprom_dump.log
3. cat ov8856_eeprom_dump.log
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Ia933927981f07e0f7954a4bc6d82f0bdd70181f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52048
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: ShawnX Tu <shawnx.tu@intel.com>
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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The next guybrush build uses 2 new LPDDR4X memory chips:
- Micro MT53E1G32D2NP-046 WT:B
- Hynix H9HCNNNBKMMLXR-NEE
The MT53E2G32D4NQ-046 WT:A chip has been added to the global LPDDR4X
list since the last time guybrush was updated, so that's brought into
the guybrush SPD directory as lp4x-spd-10.hex, but it's not used.
BUG=b:186027256
TEST=Build only
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ia5efd548f8b9442fb3703518387175aba8933a33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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Add cs42l42 codec support in fleex.
BUG=b:184103445
TEST=boot to check cs42l42 is functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1571003f8b272a573e6ab9fb525f17659bae8c4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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This patch includes changes to enable display and DSP audio UPD.
BUG=b:181219097,b:183482000
TEST=Audio sound card is detected and listed by the linux kernel.
Audio playback and capture is working on the Brya.
Change-Id: I3dab02bedb6df995b1efd27332d3aa26985e188e
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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This patch has changes to support multiple cameras modules, based on
the value set in the SSFC_CONFIG.
BUG=b:176065425
TEST=Tested the changes with magolor 5MP and 8MP camera.
Change-Id: I764abf70bacbe61452e7b0fd59c1b375227b5748
Signed-off-by: Shawn Tu <shawnx.tu@intel.com>
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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Change eSPI bus frequency to 33Mhz.
BUG=b:184356693, b:185514521
TEST=Boot guybrush, observe no eSPI bus errors
Change-Id: Ie2c1b256531f5c7354600e35e9e5191567197feb
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52402
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add PSP_DISABLE_POSTCODES and PSP_POSTCODES_ON_ESPI kconfig options for
cezanne. Select PSP_DISABLE_DISABLE_POSTCODES and unselect
PSP_POSTCODES_ON_ESPI for guybrush. Port80 codes from PSP can cause bus
errors on guybrush.
BUG=b:185514903, b:184356693
TEST=Boot guybrush, observe no port80 codes from PSP
Change-Id: I7241e47ec1b89782e699135370c796eb251afcaa
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52401
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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All related mainboards are setting DIMM_SPD_SIZE to 512. Therefore,
default to 512 in the SoC Kconfig and drop it from related mainboard
Kconfigs.
Change-Id: Idb6a0e42961eeb490afd76b4aa7d940961991733
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52513
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Update the DPTF parameters. Modify TDP, Critical Policy and Active Policy setting.
BUG=b:177777472
BRANCH=firmware-volteer-13672.B
TEST=build test firmware and verified by thermal team.
Change-Id: Ib57de5535f3d37765ac7051c17445c311c098927
Signed-off-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Replace CONFIG(CHROMEOS) with CONFIG(CHROMEOS_NVS) for cases where
the conditional and dependency are clearly about the presence of
an ACPI NVS table specified by vendorcode. For couple locations also
CONFIG(HAVE_ACPI_TABLES) changes to CONFIG(CHROMEOS_NVS).
This also helps find some of the CONFIG(CHROMEOS) cases that might
be more FMAP and VPD related and not about ChromeOS per-se, as
suggested by followup works.
Change-Id: Ife888ae43093949bb2d3e397565033037396f434
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50611
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on the measurement, adjust the delay time between the main power rail and reset signal to 7ms in order to match the spec. of touch controller, eKTH7918U.
BUG=b:184126265
BRANCH=firmware-volteer-13672.B
TEST=build test firmware and verified by EE team.
Change-Id: Iea84046c1b1f3fe6ab8bb89d86d00b1e89325f71
Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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Modify PENH device GPIO GPP_E17 for pen ejection event.
BUG=b:182867209
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot, check evtest if SW_PEN_INSERTED event
(value:1/0) when insert/eject pen, and eject pen to wake system from s0ix
Change-Id: I1b13d09ed6d065779de9441f2137dcf6559b8f27
Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52494
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul2 Huang <paul2_huang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add control charging current from TSR0 and correct charger_perf table value.
BUG=b:179067801
BRANCH=dedede
TEST=emerge-dedede coreboot
Change-Id: Ie0d969898defe76952e5c136fa93b7edffe51de3
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Edward Doan <edoan@google.com>
|
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Condition use of RO_VPD for LAN MAC address on CONFIG_VPD rather
than CONFIG_CHROMEOS.
Test: build/boot google/{beltino,jecht} with RO_VPD propagated from
stock firmware, verify MAC address set correctly.
Change-Id: I1606fe1936ccee6e03dee145901767c8e73bfe2d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52517
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
Metaknight has two daughter-board (DB_PORTS_1A_HDMI and
DB_PORTS_LTE_HDMI), LTE and USB Type A use the same usb port,so needs to
probe daughter-board to avoid USB device cannot recognize correctly.
BUG=b:184809456
TEST=build and verify USB device can recognize correctly
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ie42d12c7ce5c7341751c3cf92b5f37b6cd4d479f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52369
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raymond Wong <wongraymond@google.com>
Reviewed-by: Kaiyen Chang <kaiyen.chang@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 800193414148d5f39be42110fc2c76ad1ceb7d2f. EC
software sync needs to be enabled in payload once the EFS2 requirements
are met.
BUG=b:185277224
TEST=Build.
Cq-Depend: chromium:2829948
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ib22a89e221e1e057d82ef76b7008e5d3f14df5e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52451
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 1e36dc078e4012f884d67a32f1faac5f80406285. With EFS2
already enabled in EC, enabling early EC sync is not required. Also a
workaround has been added in payload to address any boot issues.
BUG=b:185277224
TEST=Build and boot to OS in Guybrush in both normal and recovery mode.
Cq-Depend: chromium:2832032
Change-Id: I921dc5c814e5187dce283eeff43075b59885723a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52418
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Ensure the ChromeOS FMAPs are used only when CONFIG_CHROMEOS
is selected, so non-ChromeOS targets use the default x86 FMAP.
Change-Id: Id5d3e7a44973f2fadba3ea15e0e544eee7fa53e6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Sync from guybrush.
BUG=b:182211161
TEST=builds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I02b375b6fc134e56b7f55e1421f694daa4aa994d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52407
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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EN_SPKR is routed to SD pin in the ALC1019 speaker amplifier. The
concerned pin has a voltage rating of 1.8V whereas the EN_SPKR GPIO has
a voltage rating of 3.3 V. The schematics has been updated to bridge the
gap. So enable the speaker amplifier by default and add a gpio override
table to disable the speakers before board version 2.
Also update the codec ACPI HID name for the kernel machine driver to
probe the codec successfully.
BUG=b:182960979
TEST=Build and boot to OS in guybrush. Ensure that the GPIO output state
is high.
Change-Id: I32b29bfae9bc94b5119b33a535d8bc825ef89445
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52355
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable AMD I2S machine driver and configure the devicetree with HID
information so that the machine driver ACPI objects can be passed to the
kernel.
BUG=b:182960979
TEST=Build and boot to OS in guybrush. Ensure that the ACPI objects for
machine driver is populated.
Change-Id: I8ed474d25273082d1e0742ba93746d97930deb19
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is
done") introduced a workaround in coreboot for `soc/intel/cannonlake`
platforms to save and restore GPIO configuration performed by
mainboard across call to FSP Silicon Init (FSP-S). This workaround was
required because FSP-S was configuring GPIOs differently than
mainboard resulting in boot and runtime issues because of
misconfigured GPIOs.
This issue has since been fixed in FSP (verified with FSP v1263 on
hatch). However, there were still 4 boards in coreboot using
`cnl_configure_pads()`. As part of RFC CB:50829, librem_cnl, clevo/cml-u
and system76/lemp9 were tested to ensure that this workaround is no
longer required.
This change drops the workaround using `cnl_configure_pads()` and
updates all mainboards to use `gpio_configure_pads()` instead.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Tested-by: Angel Pons <th3fanbus@gmail.com>
(Tested purism/librem_cnl)
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
(Tested clevo/cml-u which is similar to system76/lemp9)
Change-Id: I7a4facbf23fc81707cb111859600e641fde34fc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52248
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable CRFP in devicetree and configure GPIOs.
BUG=b:182201937
BRANCH=None
TEST=Boot into OS and confirm FPMCU is responding.
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add ACPI code to enable the backlight when we enter the OS.
BUG=b:184198808
TEST=Backlight enabled in the OS
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I3e0a6c06120ac5abf0a0d82494e03d9cf80c1f8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52113
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Both touchpads supported by zork use level-triggered wakeup signal.
BRANCH=zork
BUG=b:172846122,b:182911201
TEST=1. cros build-ap -b zork
2. both Synaptics and ELAN touchpads work fine on Vilboz
3. Wakeup source is correctly reported on Vilboz
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: Icc2b5ad3bd434c9759a0fdfc121aa3c94f46630e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52367
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on the datasheet provided by ELAN, the /INT pin is "low active"
and "indicates touchpad likes to send data to system(host) when low".
The signal is level-triggered.
BRANCH=zork
BUG=b:172846122
TEST=cros build-ap -b zork
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I1f2182aaf483932304591ab14592f35214ea6efd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52366
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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support audio AMP selection with fw_config.
BUG=b:185082705
BRANCH=dedede
TEST=build pass
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ieb169c69a6716082dd218d05479bca46bbc09a3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add AUDIO_AMP ports bit field in devicetree.
UNPROVISIONED 0
MAX98360 1
RT1015_I2C 2
RT1015P_AUTO 3
BUG=b:185082705
BRANCH=dedede
TEST=build pass
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I54f1e44036857dc00df074c38fde0fa82e589320
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52317
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Modify GPIO_D22/D23/E11 configuration for P-sensor
BUG=b:185214363
BRANCH=dedede
TEST=built storo firmware and verified P-sensor function
Change-Id: Ia2df1a227b04688a6b98384cd3a4e63023c0c1d9
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add uart controller to chipset.cb and leave it off by default.
Turn uart0 on for console for mainboards.
BUG=none
TEST=builds and boot into OS
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Iaeb7fea4b92bd89331c7ae7c1c000f8d9961fe9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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TCSS OC pins has not been correctly configured for brya.
This patch fills the value from devicetree to correct the OC pins
mapping
BUG=b:184653645
BRANCH=None
TEST=check if UPD value has been reflected correctly
Change-Id: Ia21cdbf5768ad7516ea52bff7e247291a7d2ebd1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Add log to show the codec has been disabled.
BUG=b:185193926
TEST=cbmem -c | grep disabled, can find the codec name
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8ce7e435ce73beb2a5cbf5883905554227b1989b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
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BUG=b:185397933
TEST=boot guybrush and no longer see tis_plat_irq_status warnings
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9b67cb59221d4e355df8e8a2205e03ead7dba51f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This is the same as zork.
BUG=b:184126844
TEST=Boot guybrush in developer mode and switch to normal mode.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib11c255ab7e937de334ecd18dc030006f7724275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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BUG=none
TEST=none
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I658372d082a8276f15c7165fe4104de4613fe7d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This include provides the GPIO_x definitions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I12a0d95f79658f3852132876e92c389b715f3001
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52358
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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platform_descriptors.h is unrelated to the contents of baseboard/gpio.h
where it was included, so move the includes to the files where it is
actually needed.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I94e59b5aac2df834d956106ac953eebfc5cf6921
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52357
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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amdblocks/gpio_defs.h provides the definitions of GEVENT_x.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I65d398667e6777de6f1fa4e027cf1c75a3e235c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52356
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I353f0d241391dd1122c85866a74984b95ed54770
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52305
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Change-Id: I428cf1a461ee63215f5683abbfed90202d1b2a88
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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The board's ec.h file defined EC_SCI_GPI as GEVENT_24, so use that
definition in all places in the mainboard code instead of a mix of the
board specific define and the SoC's GEVENT number define.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I46525ed24e9993acd3d850959dd63761a690d5df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Enable CRFP power control in gpio table. RST needs to drive low
before PWR enable. Since reset signal is asserted in bootblock,
it results in FPMCU not working after a S3 resume. This is a known issue.
BUG=b:181377402
BRANCH=None
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8a8fae80c3cc186e0a097ab2007abb656f382cbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52185
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add LTE modem to devicetree
Configure GPIO control for LTE modem
BUG=b:178092096
TEST=Built image and verified with command modem status
Change-Id: Id8f483e1132a08500fbe950711cc84197ce40b12
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=b:185084331
BRANCH=dedede
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Ie982741cb7b328623cf27f41c31f819e8cdb7bc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The new discovery from Google & AMD, the value currently used
STAPM Time Constant of 1640 is reducing real PPT TSP from the
target 4.8W to 4.68W.
Furthermore, when using the "default" STAPM Time Constant of 1400,
the actual real PPT TSP becomes 4.89W.
Operating at this default settings therefore uses a higher real PPT TSP,
which results in a significant performance improvement.
BUG=b:175364713,b:184902568
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test => pass
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I9cf4d51f42fe250340bcb642db07796c9a480c34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52312
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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