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This patch moves platform.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify _PIC method present inside
common platform.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Delete SoC local copy of ipu.asl and refer from common block ipu.asl
TEST=Dump and disassemble DSDT on tglrvp, verify IPU0 device
present there.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I6a0f8a919092f7bbcd64d4791746d30fdee33894
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Configure EMMC_RESET_L (GPIO68) to drive high by default. As per JEDEC
specification for eMMC, RST_n_FUNCTION defaults to temporarily disable
reset using RST_n signal (which is connected to EMMC_RESET_L on
zork). Chrome OS platforms do not configure RST_n_FUNCTION thus making
the reset signal unused. The spec also says that there are no internal
pulls on the card and hence the RST_n signal should be driven
appropriately to prevent the input circuits from flowing unnecessary
leakage current.
Thus, even though the line remains unused, since it is connected in
hardware, this change drives EMMC_RESET_L to high.
BUG=b:169222156
BRANCH=zork
TEST=emerge-zork coreboot
eMMC DUT reboot/suspend x100 iterations pass
Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This fix needs to go into ACPI in the long-term, but this
should suffice in the short-term.
BUG=b:158087989
TEST=Boot berknip, verify backlight is enabled. Test suspend
& resume sequence, backlight is still enabled.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6ecc3c9e397c9756a78e480d3f639c507879a0ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45854
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The SMU code was assuming that GPIO 85 was used for a fan, which caused
interesting backlight flickering. That has now been fixed, so remove
the code that reconfigured it to a GPIO on resume.
BUG=b:155667589
TEST=Verify the screen does not flicker on resume from S3
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6d4f9d98e9df52fefab9b20d0ab0f0b67512d356
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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This patch updates the SLP_Sx assertion widths and power cycle duration
for volteer.
Power cycle duration:
With default value,
S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0
With value set to 1,
S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0
BUG=b:159108661
TEST=Verified that the power cycle duration is 1~2s with a global reset
on volteer.
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Idf4e0c3a60b4ac59e31df1357f2ff28f195ff17f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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1. TSRO trip point from 75C change to 73C
2. Sample period time from 5s change to 60s
BUG=b:160385395
BRANCH=puff
TEST=build and verify by thermal team
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I0b000841845ce793be0e52fc28a07ac6a931ef7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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The default GPIO values for camera power were set as 1 so the LED was
turned on by default when the board is powered on.
This status is kept until the camera is probed then being turned off.
So the LED is turned on for a few seconds during the boot up.
By setting the default power to 0, the LED is lit only when camera
is turned on for probing and this should be just a blink.
BUG=b:167635396
BRANCH=none
TEST=Build and boot volteer board. Monitor camera privacy LED
and check it is not lit more than 0.5 seconds.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: Ic7df391aa512daafe6e1ce49e9222b90e17ad806
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45058
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure overridetree settings for audio function.
BUG=b:153680359, b:163382106
TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I107f6fc21b99d80d69931139dc50e7d5873a8e52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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cameras
There is a patch https://lkml.org/lkml/2020/9/3/235 which allows i2c
device can support driver probe without power up the device.
In order to support this, need add coreboot add
"i2c-allow-low-power-probe" property.
BUG=b:169058784
BRANCH=none
TEST=Build and boot volteer board. Monitor camera privacy LED
and check it blinks. It should not blink.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: I46f90ff8d412b18c7ee4bd7f22f9a7db771eb84f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Use the 96 character limit.
Change-Id: I865288051869e50602a579a6999b1b23ef68ec2f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Only do LTE power off for LTE sku in order to save extra 130ms delay
for non-LTE sku.
BUG=b:168075958
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If983185ff2f09fb1b2553c6ff1a1473d3254de4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
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They should be tuned per board to get the best signal and boot time.
This fixes the HS400 preset, so it's correctly set to A. It also changes
the SDR50 and DDR50 presets to B. We can't boot correctly when DDR50 is
set to A.
I chose 1 as the init kHz value since that's what depthcharge uses to
calculate the init clock.
BUG=b:159823235
TEST=Boot Ezkinil and dump SDHCI preset registers.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie2f3497b65d771820ab1a803fec73265547f8906
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Use Wifi SAR table for non-LTE sku only.
BUG=b:169115341
BRANCH=octopus
TEST=Check no SAR table can be loaded with sku id 4.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I086fa14a9f23e4a0fc0ef8085040219c932dbf17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45640
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable newly added PCIe Gen2 to SD 4.0 card reader controller GL9755
for Delbin and Volteer2.
BUG=b:166141961
TEST=Boot to kernel on Delbin, Volteer2 boards. Check PC10 in IDON.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I2589ab2334625ec0d20dbdd5f3a31d98235aad2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45708
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPP_S4 and GPP_S5 use as DMIC pins that need to be defined as NF2
BUG=b:168564129
Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: Ia1fca960ac85f253882f0aa68b370eed49ac67b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
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It needs to use probe statement in overridetree.cb to enable the cache
of fw_config field implemented by cb:44782 and cb:44783.
BUG=b:161963281
TEST= dmidecode -t 11 shows correct audio fw_config.
Handle 0x0009, DMI type 11, 5 bytes
OEM Strings
String 1: DB_USB-USB4_GEN2
String 2: AUDIO-MAX98373_ALC5682I_I2S_UP4
Signed-off-by: Kevin Cheng <kevin.cheng@intel.com>
Change-Id: I68c19b67d945aaca3e9ebec87eb27a4b07e1a49e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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update telemetry to improve the performance.
BUG=b:168581158
BRANCH=zork
TEST=1. emerge-zork coreboot
2. pass AMD SDLE test
Change-Id: Ib93905cd89132664b06f2476e94494e96980642c
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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add tcc, critical, passive policy, and pl values from thermal team
BUG=b:168353037
TEST=build and verify by thermal tool
Change-Id: I887d494ff097a881d519a456f24578a278323051
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45453
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. enable DRIVERS_INTEL_MIPI_CAMERA/SOC_INTEL_COMMON_BLOCK_IPU
2. add IPU/VCM/NVM/CAM0 in devicetree
BUG=b:166527568
TEST= build and verify function by cam ap on DUT
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: Ica6aa8ddc03a1dab5b548a759825dd3a4de3101f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45329
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Camera ACPI tables are generated at run-time for all variants of Dedede.
BUG=None
TEST=Build madoo variant.
Change-Id: Icb74c01a0a6dbc620466b64cd2b5652408ca41b9
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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In order to pass DB type-C USB2 eye diagram, DB USB2 PHY register needs
to be overridden.
port#1
PortUsb20Enable=1
Usb2PhyPetxiset=7
Usb2PhyTxiset=7
Usb2PhyPredeemp=3
Usb2PhyPehalfbit=0
BUG=b:169105751
Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: If076c644783fa2992ac062d6469f9c49e6d5ff24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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update the telemetry setting for second SDLE testing(for APU power adjusting).
Those values are used to power calibration the APU power and achieving
the best performance.
BUG=b:160698427
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4cf5b8f090befd6a3c4990f44f2f200bc66aa1f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44804
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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update telemetry to improve the performance.
BUG=b:168585079
BRANCH=zork
TEST=emerge-zork coreboot
Change-Id: I464b90550aaa1666ce3f2393856bf46fe7686d1d
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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BUG=b:168847046
TEST=emerge-dedede coreboot chromeos-bootimage
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I16ed22aa5e270ad2d5c964764cc134b72941d4e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add new ID for memory part H5ANAG6NDMR-XNC.
Command to generate files:
go build gen_part_id.go
local variant=vilboz
./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt
BUG=b:165611994
TEST=none
Change-Id: Iaf613d54bf23b637e38917937ce3e78702b26a28
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45682
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These parts have not been used in any vilboz devices. Removing
so IDs can be assigned more efficiently.
Command to generate files:
go build gen_part_id.go
local variant=vilboz
./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt
BUG=b:165611994
TEST=none
Change-Id: I99614acaf45db0556120c883577494d9f753ea12
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45679
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add memory part H5ANAG6NDMR-XNC. Attributes are derived from data
sheets.
BUG=b:165611994
TEST=Compared generated SPD with data sheets and checked in SPD
Change-Id: Ifdcc7536441e9f0b94543c6f06fe466596f752dc
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Morphius has SSD/eMMC SKU, we should turn off eMMC
if storage is NVMe SSD.
BUG=b:169211959
BRANCH=zork
TEST=1. emerge-zork coreboot
2. Check eMMC is enabled or disabled based on the eMMC bit in
FW_CONFIG.
Change-Id: I67d5d77ce3d827ae89b82529de59925f67eaf894
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Add AC connect and disconnect to S0ix lazy wake sources.
BUG=b:161466940
BRANCH=master
TEST=Connect and disconnect charger in S0ix; observe wake
Change-Id: I30046a379ff75c33b991e355cc8d142241ee8b2e
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45669
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the boldar variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
Add "memory/Makefile.inc" generated by gen_part_id.go
BUG=b:162202257
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_BOLDAR
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: I92b4b917448d8e5e9176cb983adf7b209956d2c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Modify I2C3 setting to follow I2C specification(lower than 400kHz).
Original setting:
.rise_time_ns = 125
.fall_time_ns = 37
Change to:
.rise_time_ns = 110
.fall_time_ns = 34
BUG=b:169207742
BRANCH=None
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I0f0b791c3e701ebf6b336a8cb259eeb74c46af5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Modify USB 2.0 PHY parameters for improve usb eye diagram.
1. USB 2.0 TypeC port0:
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
2. USB 2.0 TypeC port3:
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
BUG=b:169207729
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I764238485a1a81eb0d4740ac58c80a43f965f550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45641
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop lpit.asl from CNL and switch to the common one in the three boards
currently using it.
The only difference between the two is the usage on macros in common
code instead of plain integer values.
Change-Id: Iefbd18db7f4c560dce16c4119fde4f4cfbeafb84
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This change enables CnviBtAudioOffload. FSP is invoked to configure
BT over USB and BT I2S pins for cAVS connection.
BUG=b:169045123
TEST=Verifed CnviBtCore and CnviBtAudioOffload settings and FSP
configuration. Booted up to kernel on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I1780da0824d145a79743d5cffdea4821236d4f74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naveen M <naveen.m@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Based on EVT schematic and gpio table of voxel, update gpio settings for
voxel EVT.
BUG=b:156841729
TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Idf88d83ad6d873283eb1eb8a45459ae3e74df124
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45173
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that we're using fmaptool to parse the .fmd file, we can use some
short forms and omit unnecessary information.
BUG=b:157068645
TEST=None
BRANCH=zork
Change-Id: I81c121d4fce13a9d2aad4477955cb4770794d244
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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0x12 will be more stable according to validation result on SD card and
USB devices.
BUG=b:163382089
BRANCH=none
TEST=check if SD cards and USB devices work properly
Signed-off-by: Marx Wang <marx.wang@intel.com>
Change-Id: Ic98f27b6164daa3667009300439c61fed43a4a0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45573
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The name GENERIC_SPD_BIN doesn't reflect anymore what that config is
used for, so rename it to HAVE_SPD_BIN_IN_CBFS.
Change-Id: I4004c48da205949e05101039abd4cf32666787df
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45147
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop GENERIC_SPD_BIN from boards selecting it, despite having no
soldered memory.
Change-Id: Id05fe45007d5662ff9bee326f28470df1206fcff
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45146
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4151d1a6ce94763432f307fbc8bc4afe229856ea
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Enable processor thermal control using PCI dev path function instead of
Device4Enable parameter in devicetree. This change removes the dependency
on Device4Enable in devicetree. We can enable and disable this thermal
control using on and off support with PCI device entry in devicetree.
BRANCH=None
BUG=None
TEST=Built and tested on dedede board
Change-Id: I0463236996ad001af506c9966840b27fe44d60d2
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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After adjustment on madoo
Touch Pad CLK: 381.9 KHz
Touch Screen CLK: 389.4 KHz
Audio CLK: 380.9 KHz
BUG=b:168565823
BRANCH=master
TEST=USE=build madoo and measure by scope with madoo.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: If281f9a8614e3e0ef20893b456f46e68ecb0631d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Lets have the Kconfig depend more directly on CSE_LITE_SKU
than indirectly on the PUFF baseboard.
BUG=none
BRANCH=puff
TEST=builds
Change-Id: I8784b506629ceedc2770dc86d8caabbef5eb8a1d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45523
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All octopus board share the same power off sequence.
Move to smihandler.c instead variant.c.
BUG=b:168075958
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2be5a656fb42fff99c56d21aaa73ed9140caad37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45436
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add wifi sar for madoo.
Using tablet mode of fw config to decide to load custom wifi sar or not.
BUG=b:165105210
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ic6128b966c952cdc02a6359c14fa41f22265039a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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This sets the state of GSPI chip select to 1 (deasserted) as applied
by the FSP during the silicon init phase. GSPI 0 and 1 are set to CS
mode manual in the SerialIoGSpiCsMode section which means we need to
explicitly configure CS to deasserted in the SerialIoGSpiCsState
section. GSPI0 is the CR50 and GSPI1 is the fingerprint sensor. We
were running into problems where the normal expected CS toggle
sequence to wake up CR50 did not work because CS was already asserted
when it was expected to be deasserted, leading to TPM timeouts.
BUG=b:168090038
TEST=booted on volteer, no more "TPM flow control failure" messages;
verified fingerprint enrollment still works.
Change-Id: I47aa5db429d75e66095d58a1eb77963dcfc3b9f3
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45384
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add MAX98373_ALC5682I_I2S_UP4 firmware configuration option and configure GPIOs properly for UP4 design. The design is also for Halvor.
BUG=b:153680359, b:163382106
TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage, fw_config value in Halvor:
> AUDIO=MAX98373_ALC5682I_I2S_UP4
ectool cbi set 6 0x00000400 4 2
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ie25f278dfbdc2f41a36b70403699a2e3c2234600
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add newly defined fields for presence of keyboard backlight and
number pad to the firmware configuration table.
We don't have a need to use these in coreboot (yet) but this
keeps the bit definitions in sync.
BUG=b:166707536
TEST=abuild -t google/volteer
Change-Id: I066e445f7d0be056e45737d2c538be1850ae85aa
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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clamshell/tablet:
Slow_ppt_limit(W) 20
Fast_ppt_limit(W) 24
Slow_ppt_time_constant 5
Stapm_time_constant 200
Sustained_power_limit(W) 12
clamshell:
Temperature limit(C') 100
tablet:
Temperature limit(C') 70
BUG=b:157943445
BRANCH=zork
TEST=1. emerge-zork coreboot
2. change mode and check "thermctl_limit" will change
Change-Id: I1eda1411766e446b673046236f7cc4015696521f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45520
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable CSE PCI device Bus 0: Device 0x0f: Function 0x00 to let
Intel common cse block code can use this device.
Calling me_read_config32(offset) function from ramstage:
Without this CL :
HECI: Global Reset(Type:1) Command
BUG: me_read_config32 requests hidden 00:0f.0
PCI: dev is NULL!
With this CL :
HECI: Global Reset(Type:1) Command
HECI: Global Reset success!
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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This patch updates the display power enable GPIO which moved from 30 to
52 for Coachz. Veterans of this project know that there's no point
trying to ask *why* this change was necessary -- the pins move in
mysterious ways and all we can do is watch and wonder. Pin 30 is now
used for a new camera reset GPIO... surely, there must have been some
excellent reason why that pin couldn't just have become pin 52 instead.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I00ad6a6249df66006b4f2b953a0a2449bd478f6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
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GPIOs related to power sequence are
GPIO_67 - EN_PP3300
GPIO_117 - FULL_CARD_POWER_ON_OFF
GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
- keep GPIO_67 and GPIO_117 high and
- pull down GPIO_161 for 30ms then release it.
BUG=b:168075958
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9b56ef8ff346c1d4edd5aad04d4a7396c4702ffc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45193
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPP_A19 and GPP_A20 are already declared as NC in the baseboard.
Change-Id: I02f5751a70b51a197320b865d18da3a4ffeb87f7
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45485
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This change adds a user selectable option to enable all WiFi SAR
configs that apply to volteer
BUG=b:168169690
TEST=1. cros-workon-volteer start
coreboot-private-files-baseboard-volteer
2. USE="project_eldrid" emerge-volteer chromeos-config
coreboot-private-files-baseboard-volteer
3. check wifi_sar-eldrid.hex in
coreboot-private/3rdparty/blobs/baseboard-volteer
Change-Id: I6b74cd2b34ebb99cc59d456e28fd7ab2399d71d0
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45233
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This allows us to drop some casts to uintptr_t around the tree.
The MCHBAR32 macro still needs a cast to preserve reproducibility.
Only the native raminit path needs the cast, the MRC path does not.
Tested with BUILD_TIMELESS=1, these boards remain identical:
- Lenovo ThinkPad X230
- Dell OptiPlex 9010
- Roda RW11 (with MRC raminit)
Change-Id: I8ca1c35e2c1f1b4f0d83bd7bb080b8667dbe3cb3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45349
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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RCBA is located in the PCH. Replace all instances with the
already-defined `DEFAULT_RCBA` macro, which is equivalent.
Change-Id: I4b92737820b126d32da09b69e09675464aa22e31
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45348
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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platforms
BUG=b:145958015
TEST= Build Volteer coreboot and boot on Volteer Proto 2 and Delbin.
Cq-Depend:chrome-internal-review:3249528
Change-Id: I0ff896424ab23dba43075c44eb9b2c2c480ccbfb
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1) without internal pull-down which wrongly presents HPD interrupts.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.
BUG=b:165893624, b:168090618
Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I31b25be1c9248debf855435c7b688b358e2cd57e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45246
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add dptc interface in devicetree for morphius.
Set the STAPM parameters for tablet mode:
dptc_enable = 1
dptc_fast_ppt_limit = 24000
dptc_slow_ppt_limit = 20000
dptc_sustained_power_limit = 6000
BUG=b:157943445
BRANCH=zork
TEST=Build. check the setting changed.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4dac4b7e5157ad7ad407f42a6fc6b06eefbf3291
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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This change updates devicetree to enable SSDT generation for world
facing camera and user facing camera of Waddledoo. Also reverts DSDT
changes related to both the camera.
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Change-Id: Ib7e875d297c04f35d4e980ff33d9a3767d2910ac
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
|
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This enables the keyboard backlight feature in ACPI for madoo.
BUG=b:167943993
TEST=Verified 'kbd_backlight' shows up in the '/sys/class/leds '.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I11531699cb650b96becae5c1bec9f89c48b6bea0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
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The gpio90 EN_PWR_TOUCHSCREEN had been set to PAD_GPO(GPIO_90, LOW), but
addtional PAD_NC(GPIO_90) cause enable fail. remove it for issue fixed.
BRANCH=zork
BUG=b:168580357
TEST=Check Touchscreen function work
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: Id94dd63ba51759cebaf17779a5e659dbe0f1807f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45415
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: Ia76323c749a9ba71cc752a91c968aeacc11e0093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45212
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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add the magolor touch screen ctrl devices:
1)elan 6915
2)elan 5012
3)raydium RM32680
BUG=b:166711761
BRANCH=None
TEST=build firmware and verify the touch functions on DUT
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: Icd2963317e858f7d35c937e45cd6f3e556bbb953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45227
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fingerprint interrupt (FPMCU_INT_L) is level triggered and not edge
triggered. Also, we are using GEVENT for wake from fingerprint and
not the GPIO IRQ wake. Thus, the irq property exposed in ACPI tables
does not need to be set to indicate wake for the IRQ.
This change updates GPIO table to configure the pad as level triggered
and drops the wake attribute for irq_gpio in overridetree.
BUG=b:165612778
BRANCH=zork
TEST=Verified that fingerprint still works in S0 and to wake device
from S3.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I9007e5b0882ac1a6770db52d651218998f6d750d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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I plan on adding another eMMC parameter. This refactor keeps the config
contained in a single struct.
BUG=b:159823235
TEST=Build test
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4b57d651ab44d6c1cad661d620bffd4207dfebd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1) without internal pull-down which wrongly presents HPD interrupts.
DP_HPD had been removed for EVT design as those events are through eSPI.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.
BUG=b:162566436
TEST=Booted to kernel and verified no kernel HPD pins assertion message
on Delbin board.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ifdef8ee438276678258b75d2fb70c6dfc7ee0a33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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BUG=b:167297664
BRANCH=octopus
TEST=build fleex, and check touchscreen can work
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I910681c258ff5487830e795a8bd08c66be69b1d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44980
Reviewed-by: Justin TerAvest <teravest@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add configuration for ALC5682 headphone jack and ALC1015 speaker
amplifier. Also turn on the HDA PCI device.
BUG=b:161667665
TEST=Build the boten board and verified the audio functionality.
Change-Id: I835db854543e6282c102c86a7073b432fd89d0a5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44920
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPP_E12 should not be defined in the baseboard as its use is
determined by the variant. For legacy reasons, we still have GPP_E12
defined in early_gpio but should not. Malefor and volteer* have the
same GPP_E12 definition, but that is a misconfiguration. I think that
was a copy-paste that slipped through the reviews.
BUG=b:157597158
TEST=volteer2 boots to the OS
Change-Id: Ic3ef864827aa94b0b96e335565119f3d5d008837
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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1. Set tcc offset to 5 degree celsius
2. Apply the DPTF parameters received from the thermal team.
BUG=b:167523658
TEST=build and verify by thermal team
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I01a6fc5bd959798c8dd423df3907c69c883733e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Clean up the DPTF section of the baseboard devicetree; this makes
overrides simpler, as not necessarily all of the fields need to be
overridden.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iad46fd02f7602c9419d7c3674b0d2b6f5add9a93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Jasper Lake SoC supports PL2 (Power Limit2) as 20W. Increase PL2 value from 15W to 20W.
BRANCH=None
BUG=b:166656373
TEST=Built and tested on drawlat system
Change-Id: I82d6792907bb1c88cc9dd57d1eaeda8421c12fb2
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45162
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Coverity detects missing error handling after calling function
tlcl_lib_init. This change checks the function tlcl_lib_init return
value and handles error properly.
Found-by: Coverity CID 1432491
TEST=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ife38b1450451cb25e5479760d640375db153e499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Enable EC software sync for terrador and todor
BUG=None
TEST=emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I8c463eadd19d99dc04923f7400560cf7ba4b8101
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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That devicetree setting is about the Audio Co-Processor and not ACPI.
BRANCH=zork
Change-Id: I7f376371ee094392d4434340c77f0fc8d0d8e4e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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BUG=b:162409909
BUG=b:164196066
BRANCH=NONE
TEST=Verify build of strongbad target
Signed-off-by: Bob Moragues <moragues@chromium.org>
Change-Id: If83bd2c8f25fdd3c9625f40121e55c3c922a66fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45276
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The debug statement to print WiFi SAR file can potentially have a NULL
pointer. Also the debug statement does not add much value. Hence remove the
debug statement.
BUG=b:165613510
TEST=Build and boot the drawcia board to OS.
Change-Id: I710240f5e965f523fb8ac55a67880e1cbf9abd48
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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drawman/drawlat/drawcia share the same coreboot, and only drawcia is convertible.
Use tablet mode of fw config to decide to load custom wifi sar or not.
BUG=b:165613510
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.
Change-Id: Ibcd498021e63d0a172c71c3d94b60b3a25973467
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Enable FW_CONFIG and add tablet mode field in devicetree
BUG=b:165613510
TEST=emerge-dedede coreboot
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I55e4c0d0b4aa2337c01773006d0b485fdcd91654
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=b:165613510
TEST=emerge-dedede coreboot
Change-Id: Ic575889fd9b726a710abff78e1ecc8427b668d5d
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Woomax needs memory ID 0 to map to MT40A512M16TB-062E:J.
BUG=b:165611555
TEST=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Ibbcef6be382bd6649c93cfe92427f124dd137112
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45264
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPP_F14 should be configured to be routed via APIC and not SCI.
BUG=b:162528549
TEST=verified on a volteer2
Signed-off-by: Alex Levin <levinale@google.com>
Change-Id: I7f2c7af230dd75b3cb3806e2b186725d49da9e68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45279
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Apparently what I thought was lazor-rev2 is actually lazor-rev3 and
nobody is really sure what lazor-rev4 is going to be at this point or
how we proceed from there. What seems to be somewhat agreed upon is that
for now all Lazor revisions use the "old" GPIO mapping and it's not very
clear if that's ever going to change for Lazor, so let's take the
revision restriction out from Lazor for now.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4939ccfd8464da6e72b5e01a58489b8c80f5b4df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
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Move APCB generation out of the picasso makefile and into the mainboard
makefile. APCB generation tends to be mainboard specific and does not
belong in the soc makefile.
BUG=b:168099242
TEST=Build mandolin and check for APCB in coreboot binary
Build and boot ezkinil
Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:163789704
TEST=emerge-asurada coreboot
BRANCH=none
Change-Id: I1a5928fb81356aaf040534e1675933a504aa9f95
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45163
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add sc7180 display hardware pipeline programming support
and invoke the display initialization from soc_init.
Changes in V1:
- added display init required check.
- added edid read function using i2c communication.
- added sn65dsi86 bridge driver to init bridge.
- moved display initialization to mainboard file.
Changes in V2:
- moved diplay init sequence to mainboard file
- moved edid read function to bridge driver.
- calculated timing paramters using edid parameters.
- removed command mode config code.
- moved bridge driver to drivers/ti.
- seperated out bridge and soc code with mainboard file as interface.
Changes in V3:
- add GPIO selection at runtime based on boardid.
- add vbif register struct overlay.
Changes in V4:
- update gpio config for lazor board.
Change-Id: I7d5e3f1781c48759553243abeb3d694f76cd008e
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add sn65dsi86 bridge driver to enable the eDP bridge.
Datasheet used : https://www.ti.com/lit/ds/sllseh2b/sllseh2b.pdf
Changes in V1:
- fix the dp lanes using mask
- separate out the refclk and hpd config to init function
Change-Id: I36a68f3241f0ba316c261a73c2f6d30fe6c3ccdc
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Configure GPIO pins as I2S mode for audio speaker.
The audio speaker does not work on Trogdor revision 1, as the
layout was changed.
Developer/Reviewer reference, be aware of this issue:
https://partnerissuetracker.corp.google.com/issues/146533652
Change-Id: Ia4bbfea591a3231640b53e64f0e4e9d43c4437a3
Signed-off-by: vsujithk <vsujithk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add memory parts and generate DRAM IDs for trondo.
BUG=None
TEST=FW_NAME=trondo emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I2e89ecaf73a30595ed48ac9ce94ccbd4bb7ed3c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45164
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new memory.c to support DDR4 memory types.
Use the new meminit_ddr() and variant_memory_sku() for eldrid variant
code on memory.c
The initial settings override the baseboard from volteer and fine tune
gpio.c and overridetree.cb on eldrid's configuration.
BUG=b:161772961
TEST='emerge-volteer coreboot chromeos-bootimage' and verify that Eldrid
can boots. NOTE that tests the ddr4 side of the implementation.
Change-Id: I2c7b30093a8d85bac5aba5b83768af5eb36c4f70
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Allow comments prefixed with '#' in mem_parts_used csv file.
BUG=None
TEST=Run gen_part_id with mem_parts_used file containing comments
Change-Id: Ia9e274d45aa06dea7a3a5f8cd1c8ee2b23398876
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The three Intel Apollo Lake boards (apl_rvp, leafhill and minnow3) do
not define MAX_CPUS, which would then default to 1. Since this is most
likely an oversight, use the same value as other Apollo Lake boards.
To ensure this does not happen again, factor out MAX_CPUS to SoC scope.
Change-Id: I5ed98a6b592c8010b59eca7ff773ae1ccc4cd7b1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45144
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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APL does not support Hyper-Threading, and has at most four CPU cores.
Change-Id: Ib2ffadc0c31cdd96bec8eed5364c984acb2e1250
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45143
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Both Gemini Lake boards in the tree use the same value.
Change-Id: Ib6bd05206026736fd7e3d44b49e4d8ba217c2708
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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For consistency with other platforms, use `SOC_INTEL_GEMINILAKE`.
Change-Id: I06310e5a9bca6c9504f19a6c2fe9b26626f290d4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Update critical and passive policy for TSR0.
BUG=b:167477885
BRANCH=puff
TEST=build and verify by thermal team
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I244e1b5cacabf5b73c47b4039ae150cd17fcd0fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45169
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Sushi is not a real product, just a test of the new_variant program.
The effort to keep it up-to-date with the rest of Hatch is no longer
worth it. Remove the variant.
BUG=b:168030592
TEST=build bot is successful, hatch-cq builds successfully
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I2b0036f3cbdea4bfaed1274ab87a20d24c75de57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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CB:44774 introduced the non-existent SPD path. This is preventing the
device from booting up.
BUG=b:168053219
TEST=Build and boot drawcia board to OS.
Change-Id: I70ca5f4cf2c8e2e88ea5b1514b656caafb732743
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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