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2018-07-20mainboard/google/kahlee: Create Liara variantMartin Roth
This is based on the Grunt variant. BUG=b:111607004 TEST=Build Liara Change-Id: I8f23e972be0d1665c736d61621a0caaa4c4c5551 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-07-20mainboard/google/kahlee: Create Aleena variantMartin Roth
This is based on the Grunt variant. BUG=b:111606874 TEST=Build Aleena Change-Id: I6fd42db6f9f309c3c375b670cd22f818555e4195 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-07-18mb/google/octopus/variants/baseboard: Udpate CPU critical tempSumeet Pawnikar
Observed thermal shutdown initiated by DPTF due to CPU temperature reaching critical temperature trip value. During stress testing with busty workloads like Octane, Aquarium on open yorp board with heat sink, sometime CPU temperature spikes till 99 degree Celsius and DPTF initiates system shutdown. With reference to previous APL/reef/coral platforms, this updates 105 degree Celsius for the CPU critical temperature trip value to avoid shutdown. This patch also updates power limit1 value to avoid the abrupt thermal shutdown by DPTF. BUG=b:79779737 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: Icd786d3c9b5f7c733dac3fd3e22579e2434058a6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/27294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-18mainboard/google/Kahlee: Select low-power mode for WiFiSimon Glass
Put the PCIe clock pins in power-saving mode for the WiFi module to save power. Note: This currently does not appear to have any effect on grunt. BUG=b:110041917 BRANCH=none TEST=boot without this patch: $ iotools mem_read32 0xfed80e00 0x0046f3ff With this patch: $ iotools mem_read32 0xfed80e00 0x0046f3f1 Change-Id: I389815bc36b8610a30b0cbb9d73262ad392e0181 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-18mainboard/google/kahlee: Enable ASPM on PCI expressSimon Glass
We should use active-state power management where possible to reduce power consumption during normal operation. Enable these options. Linux does not seem to enable this for AMD, and the Intel code in coreboot does enable these options. PCIEXP_COMMON_CLOCK is enabled also, to follow how Intel does it. BUG=b:110041917 TEST=boot on grunt, see that WiFi and eMMC still run OK Change-Id: Ia7c711304ffe460a9fb0d4f654a51485958239ea Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27464 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-18mb/google/octopus: Create meep variantJustin TerAvest
This creates a meep variant for octopus. The devicetree overrides are copied from yorp, otherwise everything just defaults to baseboard settings. BUG=b:111543000 TEST=None Change-Id: I791f8d1589d7323fbe884dddf0f9d7362a41b9ac Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/27516 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17mb/google/atlas: Add MIPI camera ASL filesChen, Ping-chung
Atlas has one sensor, create a single endpoint to CIO2. Create power resource for enabling/disabling camera. BUG=b:111141128 Branch=None TEST=Testing on Atlas board Change-Id: Ide0e923bbc34f869dd0227c0a29977645bc5d58d Signed-off-by: Ping-Chung Chen <ping-chung.chen@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/27350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andy Yeh <andy.yeh@intel.com> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
2018-07-17mainboard/google/kahlee: Don't default backlight onMarc Jones
Keep the backlight off until it is needed. BUG=b:72694972 TEST=Backlight turns on at ChromeOS splash screen, not prior. Change-Id: Ia1aba787734e2976146ecd305dd821f0b326f0db Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-17mainboard/google/kahlee: Enable backlight on resumeMarc Jones
BUG=b:72694972 TEST=Backlight turns on ChromeOS resume Change-Id: I452e2ea94b508b137cf52301df5d2d1ad5c9ab70 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-17mainboard/google/kahlee: Enable backlight in SMI APMCMarc Jones
Enable the backlight in the OS callback to SMI for APMC. This keeps the backlight off until the OS is ready to display something. BUG=b:72694972 TEST=Backlight turns on at ChromeOS splash screen Change-Id: Idf32b1a3d45971883571a829a5c0c1f8563bb1f7 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-17mainboard/google/kahlee: Add mainboard resume functionMarc Jones
Add the mainboard resume function and __weak variant override. Change-Id: I808734208bd1ce81428771ea203709b53db56cd3 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-16google/grunt: fix thermal zone CPU temperature reportKevin Chiu
there are 3 thermal sensors and index is: 0: 1 Charger 1: 1 SOC 2: 0 CPU it needs to adjust sensor to index 2 to have correct CPU temperature. BUG=b:111284412 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I27afb6c5b64b0c39d6db15e6c61ea16a1fda1ca3 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-16mainboard/google/kahlee: Add support for Dediprog em100Simon Glass
This device claims to run at 75MHz with dual read, but it is not always reliable. Add an option to change the SPI flash speed to 16MHz, to avoid any problems. BUG=b:111363976 TEST=manually try to get my em100 running (it doesn't yet) Change-Id: I78d3d32c467aac82c72d31c773bfb0f69808aed4 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-16Kconfig: Make the EM100 config option commonSimon Glass
This applied to AMD devices as well as Intel, although the mechanism is different. Move the option to a common place. BUG=b:111363976 TEST=USE=em100-mode emerge-reef coreboot See that a message appears: * Enabling em100 mode (slow SPI flash) Change-Id: Iea437bdf42e7bc49b1d28c812bfc6128e3eb68bd Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-13mb/google/poppy/variants/nami: Use Pantheon VBTIvy Jian
Add new Pantheon sku-id for loading vbt-pantheon.bin BUG=b:78663963 BRANCH=firmware-nami-10775.B TEST=Boots to OS and display comes up. Check the board specific vbt binary loaded. Change-Id: I1ee156372754ac0e77caae5959a9ca9884de95f4 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27432 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-13mainboard/google/kahlee: Add more 3 SPD filesMartin Roth
BUG=b:111195311 TEST=Build grunt, verify SPDs are present Change-Id: Ief5ed5c3ca1d96b36926f1fc84c344a8d66dcda5 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/27437 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-12mainboard/google/nocturne: Update GPIO_FCAM_PWR_ENRicky Liang
The FCAM_PWR_EN gpio should be GPP_B4 according to the latest board schematics. Change-Id: Id926bd224b3392d8a61b6d8ae0509053afaa5b9e Signed-off-by: Ricky Liang <jcliang@chromium.org> Reviewed-on: https://review.coreboot.org/27433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tomasz Figa <tfiga@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-07-12soc/intel/braswell/acpi/dptf/thermal.asl: Make Thermal event optionalFrans Hendriks
Currently thermal event support can not be disabled at board level. Define and dependent code are placed in same file. Move define of HAVE_THERM_EVENT_HANDLER to mainboard file. Change-Id: Icb532e5bc7fd171ee2921f9a4b9b2150ba9f05c5 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/27415 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-12mb/google/octopus/variants/yorp: Enable TBMC deviceFurquan Shaikh
This change enables tablet mode ACPI device for yorp. BUG=b:111264961 CQ-DEPEND=CL:1132686 Change-Id: I81140b84a1adb5b21f1656fd89d953331e538f01 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-12mb/google/octopus: Enable TBMC device only for phaserFurquan Shaikh
Enabling of TBMC device on AP side requires corresponding support on the EC side as well. Since not all octopus variants have tablet mode support enabled, this change enables TBMC device only for phaser. BUG=b:111264961 Change-Id: I1ce181baa8ebaff0a9d767e97ddc256eef9789e8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-12mb/google/octopus/variants/bip: Enable EC SW syncFurquan Shaikh
This change enables EC SW sync for bip by removing GBB flag selection for disabling SW sync. BUG=b:110523189 TEST=Verified that EC SW sync works fine on bip. Change-Id: Iff8ee67fd682530a4fa82643cd1d00a645b347a3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-11skylake: Remove "IshEnable"li feng
Remove "IshEnable" from soc_intel_skylake_config since it's not used anymore. Enable/disable ISH by checking if ISH device is turned on or not. Refer to https://review.coreboot.org/#/c/coreboot/+/26485/. BUG=b:79244403 BRANCH=none TEST=Built. Change-Id: I4d2889af118659852431c87cb516fd19b577efc5 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/26521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-11mainboard/google/poppy/variants/atlas: config ISH in mainboard sideli feng
To enable ISH device on atlas board, change "device pci 13.0 off end" to "device pci 13.0 on end" in file mainboard/google/poppy/variants/atlas/devicetree.cb. "IshEnable" is not needed. Config atlas board specific ISH setting in devicetree.cb. Dynamically load gpio setting for ISH enabled/disabled cases. BUG=b:79244403 BRANCH=none TEST=Verified on Atlas board with ISH rework. ISH log showed on console. Change-Id: I8269a85cd2ab7917bfc0e7d63d988e0e678d0bf2 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/26486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-11google/kukui: Update MMU table in romstage and ramstageTristan Shieh
In order to get better performance, map dram as cached after dram ready in romstage. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Need a futher check after dram calibration code ready. Change-Id: Ie541fe08ee1d5b260abbabc0a5c18fb04e602b9c Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27304 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11mediatek: Share MMU operation code among similar SOCsTristan Shieh
Refactor MMU operation code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Id8173da0a02e57e863263fcd89c91a9c089e8a0f Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-11mainboard/google/kahlee: Update existing SPD filesMartin Roth
Add an extra space after 8th value on each line to make it easier to count the values. Update the empty spd to remove two random 0x80 values. BUG=None TEST=None Change-Id: If330dbf0c133f65aedddc58ecb351a80b0e45a05 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/27423 Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11mainboard/google/kahlee: Add additional SPDs for variantsMartin Roth
BUG=b:111079089, b:80375243 TEST=Build grunt, verify that SPDs are included. Change-Id: Idb03a3fa0842f7f89bb8c66dedbb8a0b293569be Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/27422 Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-06google/grunt: Update Raydium TS device ACPI nodesKevin Chiu
change I2C irq to EDGE trigger BUG=b:110962003 BRANCH=master TEST=emerge-grunt coreboot Raydium TS is working. Change-Id: Iff3acf4199d23b29dff209ec1c03a731679c6cbe Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27327 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-06mb/google/octopus: Enable tablet modeJustin TerAvest
This change configures ACPI to properly route notifications from the EC for tablet mode events to userspace. Relevant EC config changes are at: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1125261 BUG=b:111078678 TEST=With EC change, tablet mode detected by evtest and powerd Change-Id: Ifbc318186b195534f647f062544de4968aa87401 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/27346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-06mb/google/poppy/variants/nocturne: fix FPMCU IRQ sensitivityVincent Palatin
the FPMCU_INT_L on GPP_C11 is active low but the kernel irq handler is defined as IRQF_TRIGGER_LOW, so do not invert it twice. BRANCH=poppy BUG=b:78613978 TEST=On Nocturne, the 'cros_ec' IRQ count in /proc/interrupts does not increment wildly. Change-Id: I56c13c797b133dd22669a2299bcd16ef14eed335 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/27221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-06google: Use proper ACPI ID for Semtech chips: STHGwendal Grignou
Change-Id: I85cd567a923cccd2504f351aae276b5f0d9db4de Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/27347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt Delco <delco@google.com> Reviewed-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-03mb/google/*: Remove selection of DRIVERS_PS2_KEYBOARDFurquan Shaikh
Until now, chromeec was doing keyboard initialization for the boards that have DRIVERS_PS2_KEYBOARD selected. However, coreboot does not leave the keyboard controller in a default reset state. This could result in payloads or OS failing to probe the controller as there could be stale data buffered in the controller during the handoff. Since the boards using chromeec already perform keyboard initialization in payload, there is no need to initialize the keyboard in coreboot too. This change gets rid of DRIVERS_PS2_KEYBOARD selection from all google mainboards using chromeec. BUG=b:110024487 TEST=Keyboard works fine after booting to OS even if user hits keys during BIOS to OS handoff. Change-Id: I1f49b060eb005c0f2b86f9d68d6758954eeb3cf0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27291 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02mainboard/google/nocturne: Enable IPU3Lijian Zhao
Enable Image Processing Unit and CIO2 device that constitute IPU3. BUG=None TEST=Build and boot up into Nocturne platform and check with lspci. Change-Id: Ic2edf5ec7bde5c55ce1b13cf7b680094a9fffc6a Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Tomasz Figa <tfiga@chromium.org> Reviewed-on: https://review.coreboot.org/27124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-02mainboard/google/nocturne: Set camera power sequenceLijian Zhao
To make image sensor working, the intended power sequence need to applied. BUG=NONE TEST=NONE Change-Id: I4833c0e303174b297c1d193495e08e55d294a717 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com> Signed-off-by: Tomasz Figa <tfiga@chromium.org> Reviewed-on: https://review.coreboot.org/27094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-02mainboard/google/nocturne: Enable camera sensorsLijian Zhao
Sensors and CSI2 receiver configuration for Nocturne platform. IMX355 module has VCM, NVM and is on the second port of receiver. IMX319 module has NVM and is on the first port of receiver. Change-Id: I37c877df8062d5c79e25ed27775ab58e977555db Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com> Signed-off-by: Tomasz Figa <tfiga@chromium.org> Reviewed-on: https://review.coreboot.org/26283 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02nocturne: Do not set 4 LSB of SX9310 CRTL0Gwendal Grignou
These bits start the acquisition process. They should only be set by the driver. BUG=b:74363445 TEST=compile Change-Id: I9e10f5570ac82124f7f4b5cc7aaad27da0c578be Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/27265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-02nocturne: Fix casing for register definitionGwendal Grignou
Use lower case for hex values. BUG=b:74363445 TEST=compile Change-Id: I24afea58b1a791fac3c87ad397a696f7f6e0d127 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/27264 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02mb/google/poppy/variants/nami: Perform PL2 setting for sonaJohn Su
According to sona thermal table, PL2 need to check cpu id. And then set PL2 value. BUG=b:110867809 TEST=The thermal team verify OK Change-Id: I5759fb3c685e3d4eef1be054541f950843d19874 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-06-29mb/google/poppy: Fix bytes 145-146 in nayna_dimm_NT6CL256T32CM SPDT.H. Lin
nayna/NT6CL256T32CM-H1 file change byte 145/146 to be"20" for JEDEC spec BUG=b:79443146,b:109708239 BRANCH=nami TEST=emerge-nami coreboot chromeos-bootimage Test on R69.10825 with mosys Change-Id: Iadc820111f0aed34e5b46d7e23dff44cb5bb811d Signed-off-by: T.H. Lin <t.h_lin@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27275 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28nocturne: Fix uid and desc for sx9310Enrico Granata
This commit changes the uid and desc fields for the sx9310 entries in the devicetree to be unique, and correctly identify the position of the respective sensors. Change-Id: I501df7d3349fdebc9673c9815f5b1b2458abac6e Signed-off-by: Enrico Granata <egranata@chromium.org> Reviewed-on: https://review.coreboot.org/27248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
2018-06-28mb/*/*/cmos.layout: Fix coding styleElyes HAOUAS
Change-Id: I4f82482595b0e6c6159c6e1c66158bc18b061f04 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-28mb/google/poppy/variants/nautilus: Use GPP_B20 to determine SKUSeunghwan Kim
We would use GPP_B20 instead of board id to determine nautilus SKU. BUG=b:80052672 BRANCH=poppy TEST=Verified the new coreboot could determine SKU correctly Change-Id: I1978b544eef7a184a3da191306ee32d862fa8c36 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27220 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28mb/google/octopus: Create bobba variantJustin TerAvest
This creates a bobba variant for octopus. The devicetree overrides are copied from fleex, otherwise everything just defaults to baseboard settings. BUG=b:110781720 TEST=None Change-Id: Ic30c6b0d955ce26f4a9f40cd7fef1c429ab950fc Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/27223 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28mb/google/poppy/variants/nocturne: Update TSR sensor infoSumeet Pawnikar
This patch updates TSR sensor info with appropriate names. Also, updates Charger effect with correct TSR sensor mapping. BUG=None BRANCH=None TEST=Build coreboot for Nocturne board. Change-Id: Ia3bbc78f8d823e88a91265e0d55c5ac2a4ea31a9 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/27210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-06-27mb/google/*: Add a few VBT filesMatt DeVillier
These files are directly extracted from the vendor firmware Change-Id: I1f05c913872c5d2d8c8279d89eac52fd4bf4e35e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-26cheza: Fix Kconfig TPM itemsT Michael Turney
TPM config items added upstream before ready SPI/TPM is not functional on Cheza yet Change-Id: I302e00014dc31279fe2574765763ecdbf326b449 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/27213 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-26mb/google/octopus: Enable logging of EC wake sources in S0ixFurquan Shaikh
This change adds GSMI callback elog_gsmi_cb_mainboard_log_wake_source to enable logging of EC wake events in S0ix. BUG=b:79449585 TEST=Verified that S0ix entry/exit events are added to eventlog: =========== Lid open ================ 62 | 2018-06-25 14:02:36 | S0ix Enter 63 | 2018-06-25 14:02:56 | S0ix Exit 64 | 2018-06-25 14:03:26 | Wake Source | GPE # | 15 65 | 2018-06-25 14:03:32 | Wake Source | GPE # | 65 66 | 2018-06-25 14:03:37 | EC Event | Lid Open Change-Id: Icc8cd3624966ff66d2cf189871e452cf650cec40 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27235 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25mb/google/kahlee/variants/grunt: Select low-power mode for BayHub720Simon Glass
Put the PCIe clock pins in power-saving mode for the BayHub eMMC bridge to save power. This requires use of an additional register (Misc control register 2) and another bit in the existing 'protect' register. The naming of bit 0 of that register is incorrect, based on the latest datasheet (14 June 2018) so fix that too. BUG=b:73726008 BRANCH=none TEST=boot without this patch: iotools mem_read32 0xfed80e00 0x0046ffff With this patch: $ iotools mem_read32 0xfed80e00 0x00463fff Also see that the PCIe clock stops when eMMC is idle and can be started by starting disk activity. Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/26515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-25mb/google/octopus: Use the newly added override devicetree featureFurquan Shaikh
Now that sconfig is able to support variant-specific override trees, this change updates octopus boards to use this feature. Following devices are moved from baseboard devicetree to variant specific devicetree: 1. Touchscreen 2. Trackpad 3. Digitizer 4. Audio codec BUG=b:80081934 TEST=Verified that the right devices show up in static.c for each variant. Change-Id: I8df0cdf4dbcd7613aa4ef4042c272eca2915da9e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27219 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25mb/google/poppy/variants/nami: Prevent leakage with touchscreen on PantheonCrystal Lin
We found GPP_C3 keeps high when system in S0ix mode. It caused 1.8V leakage. To fix this problem, add GPP_C3 into config for Pantheon Synaptics touchscreen. BUG=b:78436458 BRANCH=None TEST=Let DUT in S0ix mode and check GPP_C3 is normal. Change-Id: Idb2dab93178af1dae54265e49522b473b69a35af Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27177 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25mb/google/octopus/variants/baseboard: Update DPTF parametersSumeet Pawnikar
This patch updates DPTF parameters for Octopus baseboard. BUG=b:79779737 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I1456b7b9ee9e02491c66b0709c710e1a7ec08cc5 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/27027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-25mb/google/nami: Enable xDCIShelley Chen
This change enables xDCI controller on nami. BUG=b:110443736 BRANCH=None TEST=None Change-Id: Ieb63e0d65ac1a142c151a3f93afe306b80a5d99a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/27181 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-23mb/google/poppy/variants/atlas: Add two new Samsung memory optionsCaveh Jalali
- add K4E6E304EC-EGCF and K4EBE304EC-EGCF to memory strapping table BUG=b:110498646 BRANCH=none TEST=none Change-Id: Iddacdf1e1d0e2bae0c6168c86e54f5f602cd9d19 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/27184 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-23mb/google/poppy/variants/atlas: add GPIO for bluetooth enableCaveh Jalali
This configures a GPIO pin for enabling/disabling bluetooth on the next version of the atlas board. The default is for bluetooth to be enabled at this point. BUG=b:110614620,b:110613353 BRANCH=none TEST=none Change-Id: I4ba940e89b1dc03548b7ab44b8f84dc9a3097acb Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/27185 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-22mb/google/poppy/variants/nami: Fix non-working thermal sensor QT2 PSVJohn Su
Modify DPTF TRT parameters to solve thermal sensor QT2 PSV problem. BUG=b:109941652 TEST=The thermal team verify OK Change-Id: Id9d39d8282712a0341fea10f74c0e40bb1ac9d7c Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-22mb/google/octopus: Update GBB_FLAG_DISABLE_EC_SOFTWARE_SYNCFurquan Shaikh
Move GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC under each variant config and select it for bip and fleex only. Functional change in this CL is that EC SW sync will be enabled for phaser. BUG=b:110523400 Change-Id: If6f37c6b2ee71130b9ed5b10ce92fb23fa1c39fc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-22mb/google/poppy/variants/nocturne: Hook up the SX9310 proximity sensor.Enrico Granata
Change-Id: I7358ee34df873098a86d692cc8a909b0ec5023a8 Signed-off-by: Enrico Granata <egranata@chromium.org> Reviewed-on: https://review.coreboot.org/27172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"Arthur Heymans
In the end it does not look like RCBA register offsets are fully compatible over southbridges. This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4. Is squashed with revert of "sb/intel/common: Fix conflicting OIC register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f. Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-21google/lars,lili: Add SPD mapping for Hynix 8GB configren kuo
Upstreaming Chromium commit 0bc6c43: Lili: Update Memory IDs TEST=Build and boot up on lili board Original-Change-Id: I6da1e97820b1bf2e751102384eed07236143fe2b Original-Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/956782 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: Icf6588582da3b4a7861bced539d51a914b011dc4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27135 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21mb/google/poppy/variants/nocturne: add two new memory optionsNick Vaccaro
- add K4E6E304EC-EGCF and K4EBE304EC-EGCF to memory strapping table - add SPD files for K4E6E304EC-EGCF and K4EBE304EC-EGCF BUG=b:110277021 BRANCH=none TEST=none Change-Id: If1322311bd91842d6d32725822d91fd6d9e8077c Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21mb/google/poppy/variants/nocturne: Update Slave Addresses of Max98373 Amp'sSathyanarayana Nujella
When played Left Only Audio and Right Only Audio, we observed that Audio got swapped. Left Data played on Right Speaker and Viceversa. This patch fixes the above issue. BUG=b:73635449 TEST=Play Left only & Right only Audio and cross check Audio. Change-Id: Ie9c417ad0634a76fc8a4126ee75886603f1b3da0 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/27167 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21mb/google/poppy/variants/nocturne: disable p-statesNick Vaccaro
Set register speed_shift_enable=0 in devicetree to disable p-states in coreboot as a temporary workaround for an SoC hang. BUG=b:79666828 BRANCH=none TEST="emerge-nocturne depthcharge coreboot chromeos-bootimage", flash spi image onto nocturne, boot to kernel and verify device stays alive and responsive for several minutes without locking up. Change-Id: I71ed4c80c109b28ffa85d48338ce3a62396d272e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21mb/google/poppy/variants/atlas: enable camera power and release resetCaveh Jalali
This is a temporary hack to test camera presence before we have full camera support implemented. Basically, we can now probe the camera over i2c to verify that it's connected and the camera LED turns on. BUG=b:80106316 BRANCH=none TEST=camera LED comes on and camera can be probed over i2c. Change-Id: Ibaabf6c6f6a1dabaddd2fc47c820e090ca5984a5 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/27128 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21mb/google/poppy/variants/atlas: enable touchscreenCaveh Jalali
This adds the necessary config to enable touchscreen sensor in linux. BUG=b:110286344,b:110286345 BRANCH=none TEST=verified touch functionality using eval board Change-Id: I21efafda3f2ae1dcea19e44f8d66f6dfaac1bb12 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/27127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21mb/google/poppy/variants/atlas: support i2c-hid trackpadCaveh Jalali
We plan to use i2c-hid compatible trackpads on atlas, so this switches the trackpad config to i2c-hid. BUG=b:80662079 BRANCH=none TEST=used trackpad to verify motion tracking Change-Id: I2702e61a6aa96250c0c09ea4bd15d0c671eedadc Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/27126 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21mb/google/poppy/variants/nautilus: Add SAR sensor device into devicetree.cbSeunghwan Kim
This change defines SAR sensor device into devicetree.cb. Since only LTE sku has SAR sensor, we will use GPP_B20 as a device_present_gpio. BUG=None BRANCH=poppy TEST=Verified SAR sensor device is loaded by driver in Chrome OS Change-Id: Ib4969e4b82d18b1b1a599de8226c2d7d4bda7915 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27149 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21mb/google/poppy/variants/nautilus: Clear GPP_D0 when entering S5Seunghwan Kim
Nautilus 2nd SKU has a leakage voltage at GPP_D0 in S5 state. We need to set this to LOW when entering S5 for clear the leakage. BUG=None BRANCH=poppy TEST=Verified the leakage is gone after update coreboot Change-Id: I054e707b2bc2e63d6f99cd2fd8a57be20615f111 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21mb/google/poppy/variants/nautilus: Configure for 2nd nautilus SKUSeunghwan Kim
For supporting new SKU, we need to override GPIO table and device configuration. The board ID of 2nd SKU of nautilus is started from 9, so we would determine SKU with it. BUG=b:80052672 BRANCH=poppy TEST=emerge-nautilus coreboot Change-Id: I7242f23f47010664cc29ea86a126e63c9dd62ccd Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27147 Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-20mb/google/octopus: Configure EC_IN_RW correctlyFurquan Shaikh
This change fixes the following issues with EC_IN_RW signal: 1. EC_IN_RW is an input signal to the SoC. Configure it accordingly in GPIO table for baseboard and bip. 2. GPIO_EC_IN_RW is passed in coreboot tables so that payload can re-sample the GPIO at runtime. BUG=b:110084012 TEST=Verified that EC_IN_RW signal is read correctly in depthcharge. Change-Id: I1c5f5b4b914ced98e89a571dc398df5ba1fe8460 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-06-20mb/google/octopus: Enable Synaptics touchpad devicewuxy
This change adds Synaptics device to phaser project. BUG=b:110236590 TEST=emerge-octopus coreboot chromeos-bootimage reflash the coreboot to DUT,make sure the Synaptics Touchpad can work. Change-Id: Icc1e8c35a9de54ed04187fcf219a72a592d3bd81 Signed-off-by: Xingyu <wuxy@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27159 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-18mb/google/poppy/variants/nautilus: Correct USB OC pin configurationSeunghwan Kim
Due to schematic, we need to correct USB OC pin configuration. - OC0 for Type-C Port 1 - OC1 for Type-C Port 0 - OC2 for Type-A Port - OC3 to NC BUG=NONE BRANCH=poppy TEST=emerge-nautilus coreboot Change-Id: Ic71baef646926cc6aadcc5dda7cb14f00e8d3687 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-18mb/google/octopus: Enable Synaptics touchscreen deviceFurquan Shaikh
This change adds ACPI properties for SYTS7817 device. BUG=b:110013532 Change-Id: Ifdec4efce169c066f212a393df21089d43d8e4d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-18mb/google/octopus: Create fleex variantJustin TerAvest
This creates a fleex variant for octopus. Nothing is set in the variant files here; everything is picked up from baseboard. BUG=b:110085182 TEST=None Change-Id: Ia8b8bb757f67bea997b7f43489c38cac62f7682d Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/27105 Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15mainboard/google/Kahlee: All variants identify as Grunt in SMBIOSMartin Roth
All Grunt variants should identify as grunt in SMBIOS so that they're recognized correctly as a unibuild Grunt variant. BUG=b:110244268 TEST=Careena identifies as grunt Change-Id: Iaf254149fbec9551d9220018d6d6a0a1be741538 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27117 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15soc/intel/{glk,apl} and mainboards: Configure LPC_CLKRUN# pin as GPIO for S0ixHannah Williams
This pin does not have a native function for eSPI. Nonetheless if we use eSPI, it should be configured as a GPIO and kept unconnected to allow S0ix entry. Also removed initialization of LPC pins in mainboard code as they are already initialized in chipset code. The settings fpr LPC pins in chipset code were updated to those that were previously in mainboard code and have been validated on LPC flavor of Geminilake RVP. BUG=b:79251613 BRANCH=none TEST=From kernel prompt in bip, type powerd_dbus_suspend. Check on EC console that SOC enters S0ix. Change-Id: Ie0c1013fee638a3b7a91469736efc0c25a1597fa Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/23742 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15mb/google/poppy/variants/nami: Update DPTF table from version 1.5John Su
Update dptf.asl and TCC parameters from tuning of the thermal team. BUG=b:72974136 TEST=Match the result from DPTF UI Change-Id: Ic0ffc169ad3939cacb46824ed23999c61a23d2c4 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27086 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15mainboard/google/kahlee: Enable keyboard backlight for careena specific SKUKevin Chiu
Enable keyboard backlight by Careena SKUID Set to 10% as the same as google/snappy project BUG=b:110065836 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I7d302c4f50528b0e6b7ef4d990f342a69cff34f5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-14cpu/intel/haswell: Use the common intel romstage_main functionArthur Heymans
Tested on Google peppy (Acer C720). Change-Id: I6453c40bf4ebe4695684c1bd3a403d6def82814f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-14mb/google/poppy/variants/nocturne: config GPP_E2 for BT_DISABLE_LNick Vaccaro
GPP_E2 will be used as a BT reset line, so configure GPP_E2 as an output and initialize it high (high = out of reset). BUG=b:80089559 BRANCH=none TEST=none Change-Id: If45ef3a592c389a0b80298c59eea849d07d9671e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-14mb/google/poppy/variants/nocturne: config GPP_B4 for FCAM_PWR_ENNick Vaccaro
FCAM_PWR_EN signal is changing to connect to GPP_B4 instead of GPP_D8 as it needs a 3.3v gpio to provide enough power to also directly power the camera LED. BUG=b:79667559,b:78122599 BRANCH=none TEST=none Change-Id: Ie875ced45dfa2aa7069851004edde8f77329df34 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-06-11google/kukui: Add MediaTek MT8183 reference boardTristan Shieh
BUG=b:80501386 BRANCH=none TEST=timer and uart work fine Change-Id: I08644892d34925574f791b000b0035d5afad7022 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26722 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11mb/*/*/acpi_tables.c: Remove unneeded includesElyes HAOUAS
Change-Id: If1f032d097224a1102ba29d8d45dce46aad3a91a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-11{src,util}: Use NULL instead of 0 for pointerElyes HAOUAS
Change-Id: I75fa4577055f25dde0a8b1044c005bba72cabd92 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-11google/fizz: fix LAN driver chip_info attachmentMatt DeVillier
As a result of commit: [711fb81] soc/intel/skylake: Swap PCI devfn resides in same PCI device fizz's chip_info for the LAN driver is being overwritten/nulled, as the LAN device is on function 2 (PCIe port 3), but the driver info was set for the post-swapped PCIe port (1). Move the driver chip_info to function 2/port 3, so that it follows the PCI device function when swapped after FSP-s, and is correctly passed to the LAN driver. Test: boot google/fizz (teemo variant), check cbmem console and verify ethernet MAC address and LED config correctly set. Change-Id: I08810c0c89d99af5799f42c7c4e51814f09aafec Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-11mainboard/google/kahlee: Remove unused baseboard codeMartin Roth
This code is no longer needed. BUG=b:107537694 TEST=Build & boot on grunt Change-Id: I71ad01f0d4c69a618d564e514ed99550b72a6b44 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-11mainboard/google/kahlee: Remove Kahlee variantMartin Roth
This code is no longer needed. Removing Kahlee options allows some Kconfig options to be optimized. BUG=b:77693343 TEST=Build Grunt, verify that nothing's changed. Change-Id: I4eeeee7f35381bba8760c8a530251c475d0ee29b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-11mainboard/google/eve: add vendor to subsystem idMatt Delco
The initial subsystem ID had a device ID but not a vendor ID. This change adds the Google vendor ID to the subsystem ID. Change-Id: I14897da115fd6f2ddd492b6c565bd23227197232 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/26987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: HARSHAPRIYA N <harshapriya.n@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-11mb/google/poppy/variants/nami: Add EC_ENABLE_TBMC_DEVICEShelley Chen
Add tablet motion control config to nami devices. BUG=None BRANCH=None TEST=run evtest make sure tablet switch value is 1 in tablet mode and 0 when not in tablet mode Change-Id: Ie1480934dc003d9b467883e001ed89f9a3694d10 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/26970 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11mb/google/poppy/variants/nocturne: enable nvmeNick Vaccaro
- configure GPP_B7 (PCIE_NVME_CLKREQ_ODL) for NF1 - enable root port 9 - add nvme register settings to devicetree BUG=b:78122599 BRANCH=chromeos-2016.05 TEST='emerge-nocturne depthcharge coreboot chromeos-bootimage', boot to kernel, and verify /dev/nvme* entries exist. CQ-DEPEND=CL:1090070 Change-Id: I0070d33b1ed09bd1f51a680d92ddb7e2bcb1ebc2 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/26933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-06-11Fizz: Remove BJ adapter configurationDaisuke Nojiri
This patch removes BJ adapter configuration, which has been moved to the EC. BUG=b:109762580 CQ-DEPEND=CL:1089328 BRANCH=none TEST=Verify BJ adapter is set expectedly on Teemo. Change-Id: I3041b984e7f02624b94ba2713b084d001fa155f9 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1089370 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/26965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-09mainboard: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Use pci_devfn_t or pnp_devfn_t instead of device_t in romstage. Change-Id: Ie0ae3972eacc97ae154dad4fafd171aa1f38683a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26984 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-08mainboard/google/kahlee: Turn on backlight for all SKUsMartin Roth
Careena uses a different keyboard backlight method, so let the EC handle the different SKUs and backlight methods. BUG=b:80106042 TEST=None Change-Id: I47f7a9ac13538f0216fbb0f64fdd22f66097820c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-06-08src/mainboard/kahlee: Use common mainboard and romstage filesMartin Roth
Until these need to be separated out, use a common file for mainboard and romstage to make upkeep easier. BUG=b:80106042 TEST=Build Grunt and Careena Change-Id: I65188bee1958d442bfe64637c3b93dc05583a686 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-06-08mainboard/google/kahlee: Use 66MHz SPI clock for fast readMartin Roth
Looking at the 100MHz signal, we were violating the timing requirements. 66MHz still isn't great, but it's a good tradeoff between improving the signal and losing boot speed time. This slows down the boot time by about 20mS. BUG=b:109583457 TEST=Boot grunt, look at signal on scope Change-Id: I7ce70c992822dd17c5877226e74c1890660768c6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-06-08mb/google/kahlee: Configure EC_PCH_WAKE_L as an SCI sourceDaniel Kurtz
Configuring EC_PCH_WAKE_L as an SCI enabled GPIO allows the EC to wake the AP from S3 on keyboard presses. BUG=b:109759838 TEST=(1) powerd_dbus_suspend (2) press a key on the internal keyboard => system resumes from S3 Change-Id: I30f72460fd588706f91f4fc3ea4ff007c96e9ebe Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26931 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07mb/google/octopus: Fix GPIO to GPE mappings in devicetreeFurquan Shaikh
Change b41ae2 (mb/google/octopus: Enable wake-over-wifi for octopus variants) changed the GPE mappings to accomodate for WiFi wake pin. However, this resulted in TPM interrupt pin being removed from the GPIO to GPE mapping. Since we do not support true interrupts in coreboot, GPE_STS registers are used to identify if an interrupt has triggered. Change in GPE mapping resulted in this information to be lost when talking to TPM thus resulting in "Timeout wait for tpm irq". This change fixes the above issue by assigning GPIO block for TPM interrupt back to DW1 and moving GPIO block for wake-over-wifi pin to DW3. DW3 was mapped to NW_31_0 which only has debug header pins and CNVI pins (none of them are used for reading GPE_STS or as wake sources). BUG=b:109824918 TEST=Verified that there are no "Timeout wait for tpm irq" messages when talking to TPM. Change-Id: I30768177a838a684948f7485d760c8b83c3190f7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com>
2018-06-07mb/google/poppy: Select right TPM interfaceNaresh G Solanki
TPM over SPI/I2C config selection got changed in https://review.coreboot.org/c/coreboot/+/24903 so this CL is fixing the same. BUG=None BRANCH=None TEST=Build for Soraka & make sure that TPM is probed over I2C interface rather than SPI. Change-Id: I077e4dc03520e26eb9f6404a7eb1edd99925de77 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26890 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07mb/google/poppy/variants/nami: Disable rear camera/DMIC for SonaAmanda Huang
Since there are two cameras on Nami and only one camera on Sona. We need to disable rear camera/DMIC on all Sona sku. BUG=b:109710674 BRANCH=master TEST=Verify if only front camera/DMIC shown on Sona Change-Id: Id84ee22c9ffc15db78be3bbad148af5cd7dc866e Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-07mb/google/poppy/variants/nami: Disable rear camera/DMIC for PantheonAmanda Huang
Since there are two cameras on Nami and only one camera on Pantheon. We need to disable rear camera/DMIC on all Pantheon sku. BUG=b:109720689 BRANCH=master TEST=Verify if only front camera/DMIC shown on Pantheon Change-Id: Ibe48a945dc57f2c05344479253040ad1945d92fd Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-07mainboard/google/kahlee: Remove colon from filenamesMartin Roth
Change-Id: I3e0ca62ad88aea5c99f9f0902ad8553656469a1c Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 20:17:42 +0000