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2020-07-18mb/google/dedede: Convert static DPTF ASL into devicetree entriesTim Wawrzynczak
Since there is now a mechanism to generate DPTF ACPI tables and methods at runtime, dedede should switch to using that instead of raw ASL files. This patch converts the existing .asl files into devicetree entries. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6bb6e6e15f50a1e510080e16bbca09dfc5f16b1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43422 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-18mb/google/volteer: Update DPTF with temp sensor 3Tim Wawrzynczak
While the DPTF refactor was in progress, TSR3 was added to volteer's dptf.asl file, and I forgot to update the devicetree with TSR3 as well. Also missed a swap in the passive policies of TSR0 and TSR1. This patch fixes those. BUG=b:149722146 TEST=boot volteer, dump SSDT & DSDT, verify TSR3._STA returns 0xF Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I71bc798492ec45bb1e2f8d779e6829db52ef4499 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-17mb/google/zork/var/vilboz: Use AMDI1015 HID for I2S machine deviceFurquan Shaikh
Vilboz requires a different HID than rest of the zork variants. Hence, this change sets the HID to AMDI1015 for I2S machine device in vilboz overridetree.cb. BUG=b:157708581 Change-Id: Ibae343f21cf8f0c782dc8a461f69172bf0da7eba Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43545 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/google/zork: Switch to using newly added i2s_machine_dev driverFurquan Shaikh
This change switches zork devices to use the newly added i2s_machine_dev driver in devicetree rather than passing dmic_select_gpio in SoC config. BUG=b:157708581 Change-Id: I76c633694cbfb454c081ab2a4af4765bfbbae16b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-17mb/google/zork: Drop mainboard.aslFurquan Shaikh
This change drops mainboard.asl from zork because none of the objects defined in it are used. BUG=b:153879530 Change-Id: If5440bcbce39b4461b44acaec69561663b1ea329 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43519 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17soc/amd/picasso: Move PMOD global variable to globalnvs.aslFurquan Shaikh
Global variable `PMOD` that stores the interrupt mode used by OS is required by all mainboards. This change moves the variable definition to globalnvs.asl under picasso. Additionally, ACPI spec says that BIOS should assume interrupt mode as PIC until _PIC() method is called by OS. Thus, this change also updates the default value of PMOD as 0 i.e. PIC mode. BUG=b:153879530 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I731c03d965882281a7a23f55894451210ba72274 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43514 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/google/zork: correct wake gpe value for gpio 9Aaron Durbin
GPIO_9 is associated with gevent 22. Correct all the misconfigurations and use macros for clarity as to what bit offset is being used instead of open coding things. BUG=b:161205804 Change-Id: Ic4cfd62763d72d12a55f89585f24e07df6af0f4f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43516 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/google/zork: Enable ACP_PME_EN and ACP_I2S_WAKE_ENFurquan Shaikh
This change enables ACP_PME_EN and ACP_I2S_WAKE_EN for dalboz and trembyle boards using devicetree settings. BUG=b:161328042,b:146317284 Change-Id: Ie367a9ba878a1892177df874bbcb8005efeb0880 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43496 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16soc/amd/picasso: remove unused fadt_pm_profile devicetree settingFelix Held
commit 56da63c3dc3f50cfac541c779b608e1bae9e635c removed overriding that field in the FADT. Change-Id: I0c8ff9ab125129dc856949c47a3a0c14e4109c73 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43417 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16soc/amd/picasso/acpi,mb/{zork,mandolin}: Stop clearing PciExpWakeStatusRaul E Rangel
The kernel already clears this: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/third_party/kernel/v5.4/drivers/acpi/acpica/hwregs.c;l=390 No reason to have the firmware do it as well. BUG=b:153001807, b:154756391 TEST=Build Trembyle, boot, suspend, and resume and didn't see any ACPI errors. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia5c79fb95dc885eaef8abc4257b6ba18c1ef1b66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16soc/amd/picasso,mb/{zork,mandolin}: Remove invalid UPWS variableRaul E Rangel
PMx0EE is not defined in the Picasso PPR. BUG=b:153001807, b:154756391 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I98caf0cd2d0bdcf19de2b945dcf74f5cf7354769 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16mb/google/zork: Move variant_pcie_gpio_configure() to bootblockFurquan Shaikh
On zork, bootblock is part of RW firmware in non-recovery mode, so PCIe GPIOs can be configured early on in bootblock rather than waiting until romstage. This change moves the call to variant_pcie_gpio_configure() to happen in bootblock and drops romstage.c file. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ic515304f35fe5623d58d6000efcb11fb9039e137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43476 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/google/zork: Drop variant_romstage_gpio_table()Furquan Shaikh
gpio_set_stage_rom table is now configuring only PCIe related GPIOs in romstage. This change moves the configuration of PCIe related GPIOs to variant_pcie_gpio_configure() to keep all the configuration for WiFi and non-WiFi PCIe pads in one place. It also drops the function variant_romstage_gpio_table() as it is unused. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib1c41ba141dce6b52b6e0a250a3aa07c296068aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/43475 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/google/zork: Drop redundant romstage GPIO tableFurquan Shaikh
Now that the power and reset GPIO configuration for non-PCIe devices is dropped from romstage GPIO table, the tables for pre-v3 and v3 version of schematics are exactly same. So, this change drops the duplicate table and also removes the check for v3 schematics when configuring the pads in romstage. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I67ca9f587c3f47912393ebaf38badcc9d76cc393 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-16mb/google/zork: Drop power and reset control in romstage for dalbozFurquan Shaikh
This change drops power and reset control for non PCIe devices in romstage for dalboz reference as this is not required. +---------------------------------------------------------------------------------------+ | GPIO| Net name | External| Internal| Domain| State at reset | State on S3 resume | | # | | Pull | Pull | | | | +---------------------------------------------------------------------------------------+ | 5 | PEN_POWER_EN | 100K PD | PD | S5 | Powered off | Powered on | | | | | | | (because of | (since power is not| | | | | | | internal PD) | disabled when | | | | | | | | entering S3) | +---------------------------------------------------------------------------------------+ | 6 |EN_PWR_TOUCHPAD| 499K PD | PU | S5 | Powered on | Powered on | | | | | | | (because of | (since trackpad | | | | | | | internal PU) | is wake source) | +---------------------------------------------------------------------------------------+ | 68 | EMMC_RESET_L | 100K PU | PD | S0 | Asserted | Asserted | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ | 76 | EN_PWR_CAMERA | 499K PD | PD | S0 | Powered off | Powered off | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ | 140 | USI_RESET | 10K PD | PD | S0 | Deasserted | Deasserted | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ | 141 | USB_HUB_RST_L | 10K PU | PD | S0 | Asserted | Asserted | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------+ | 67 |EN_PWR_TOUCHPAD| 10K PU | PD | S0 | Powered off | Powered off | | |_PS2 (pre-V3) | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ GPIO_140 starts deasserted out of reset and S3 resume, but gets asserted in ramstage since it is eventually deasserted by OS using ACPI methods. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ie792a5a9d6420763ff10d1e475c094b6ee514888 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-16mb/google/zork: Drop power and reset control in romstage for trembyleFurquan Shaikh
This change drops power and reset control for non PCIe devices in romstage as this is not required. +---------------------+--------------------------------------------+--------------------+ | GPIO| Net name | External| Internal| Domain| State at reset | State on S3 resume | | # | | Pull | Pull | | | | +---------------------------------------------------------------------------------------+ | 5 | PEN_POWER_EN | 100K PD | PD | S5 | Powered off | Powered on | | | | | | | (because of | (since power is not| | | | | | | internal PD) | disabled when | | | | | | | | entering S3) | +---------------------------------------------------------------------------------------+ | 13 |EN_PWR_TOUCHPAD| 499K PD | PU | S5 | Powered on | Powered on | | |_PS2 | | | | (because of | (since trackpad | | | | | | | internal PU) | is wake source) | +---------------------------------------------------------------------------------------+ | 68 | EMMC_RESET_L | 100K PU | PD | S0 | Asserted | Asserted | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ | 76 | EN_PWR_CAMERA | 499K PD | PD | S0 | Powered off | Powered off | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ | 140 | USI_RESET | 10K PD | PD | S0 | Deasserted | Deasserted | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------+ | 67 |EN_PWR_TOUCHPAD| 10K PU | PD | S0 | Powered off | Powered off | | |_PS2 (pre-V3) | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | | | | | | | | | +-----+---------------+---------+---------+-------+----------------+--------------------+ GPIO_140 starts deasserted out of reset and S3 resume, but gets asserted in ramstage since it is eventually deasserted by OS using ACPI methods. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ieadc62f1a13857209cf0a62f204efb9278e0e97d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-16mb/google/zork: Keep USI_RST asserted in ramstageFurquan Shaikh
This change keeps USI_RST(GPIO_140) asserted in ramstage since it gets deasserted by OS using ACPI methods. BUG=b:160854397 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I8feced788e471a0efb2358d42b2146df04fb7a0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/43461 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/google/zork: Keep pen power enabled in sleep stateFurquan Shaikh
This change keeps pen power enabled in sleep state to allow it to charge in S3. BUG=b:155422911 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I6190496653878327f34a01f6a743db474d32e929 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43452 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/google/kukui: Add new config 'willow'Sheng-Liang Pan
New board introduced to Kukui family. BUG=b:159194582 TEST=None BRANCH=kukui Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Icc6bcbd006008a05303693e481a54636f0645887 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43318 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16google/trogdor: Remove GPIO_AP_SUSPEND_LJulius Werner
This pin has been removed from recent revisions (or at least moved to a pin that's not controlled like a normal GPIO). It has also never been used on older ones (I think?). The same GPIO is now used as a SKU ID pin, so make sure we're not incorrectly configuring it as an output (although sku_id() overrides that later anyway, but it's still incorrect). BUG=b:160754995 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I6e0d56e230d0bef172d7b78cc48263e9b6f059de Reviewed-on: https://review.coreboot.org/c/coreboot/+/43471 Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Philip Chen <philipchen@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/google/zork: Remove redundant PCI info from overridetreesRob Barnes
This information is redundant since it's already specified in baseboard/devicetree_trembyle.cb or baseboard/devicetree_dalboz.cb domain 0 is still required because sconfig uses it as an identity anchor to match devicetree and overridetree. BUG=b:157580724 TEST=Boot zork, usb functional Change-Id: I3c3c1c2410166b99599d7343fae3ee756f4da321 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43437 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15mb/google/dedede: Enable SIS touchscreen for WaddledeeKarthikeyan Ramasubramanian
Add SiS9813 USI touchscreen support. BUG=b:160129126 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Change-Id: I42fdc5e8243d2c70c953b2f516c10f84a041c035 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43304 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15mb/google/volteer: Enable SATA Port Dito ConfigShaunak Saha
Enable SataPortsEnableDitoConfig for port 1. BUG=b:151163106 BRANCH=None TEST=Build and boot volteer. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: I552faaa0e7172e77208025cf4251bb848cc90709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42415 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15mb/google/zork/.../sleep.asl: Remove unnecessary variableRaul E Rangel
There is no reason to create a named variable. We can just return the package. BUG=b:153001807, b:154756391 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4f8f0362adf5ea5f026d0ba5ac6ac917fa160142 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-15mainboard: Drop optional and empty ACPI \_BFS methodsAngel Pons
The ACPI specification, version 2.0 says: _BFS is an optional control method. So, remove them. They have been copy-pasted around quite a bit, and do not do anything useful. Plus, it's deprecated in later ACPI versions. Change-Id: I9ef21f231dd6051d410ac3a0fe554908409c2fa7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43443 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15mb/google/zork: Change SPI fast speed to 66mhzRob Barnes
Morphius cannot support 100Mhz fast SPI causing it to not boot. Downgrade all zork boards to fast=66mhz and normal=33mhz to be safe. BUG=b:161233767 TEST=Boot morphius Change-Id: I7744dd0cb8dede985fbdc28a64385e0bc4048402 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43459 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Eric Peers <epeers@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15mb/google/oak: Add new DRAM modules for oakwuxy
Add DRAM support for oak: Samsung K4E6E304ED-4GB # 1001 Nanya NT6CL512T32AM-H0-4GB # 1010 BUG=b:157702981 BRANCH=oak TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge, update FW to DUTs,these DUTs can pass 'memtester' test over 48 hours. Signed-off-by: Xingyu Wu <wuxy@bitland.corp-partner.google.com> Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-14mb/hatch: Fix Puff baseboard missing mainboard symbolsEdward O'Callaghan
Fix a missing CONFIG_ prefix in Makefile. BUG=b:161154280 BRANCH=puff TEST=builds Change-Id: I177fcd830a8a03a8db1910bfbfd784a60dc08e11 Spotted-by: Ryan Lin. Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43438 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14src: Remove unused 'include <stdint.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<' Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14src: Remove unused 'include <types.h>'Elyes HAOUAS
Files found using: diff <(git grep -l '#include <types.h>' -- src/) <(git grep -l 'BIT(\|size_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\|MAYBE_STATIC_NONZERO\|zeroptr\|int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|bool\|true\|false\|cb_err\|CB_SUCCESS\|CB_ERR\|CB_ERR_ARG\|CB_CMOS_\|CB_KBD_\|CB_I2C_\|cb_err_t\|DIV_ROUND_CLOSEST\|container_of\|__unused\|alloca(\|ARRAY_SIZE\|ALIGN\|ALIGN_UP\|ALIGN_DOWN\|IS_ALIGNED\|__CMP_UNSAFE\|MIN_UNSAFE\|MAX_UNSAFE\|__CMP_SAFE\|__CMP\|MIN(\|MAX(\|ABS(\|IS_POWER_OF_2\|POWER_OF_2\|DIV_ROUND_UP\|SWAP(\|KiB\|MiB\|GiB\|KHz\|MHz\|GHz\|offsetof(\|check_member\|member_size' -- src/)|grep -v vendor |grep '<' Change-Id: I5d99d844cc58d80acb505d98da9d3ec76319b2eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41677 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14mb/google/zork: Add USB to baseboard devicetreeRob Barnes
Add USB ports, USB user-facing camera and USB bluetooth to devicetree. USB ports 4 and 5 are duplicated for picasso and dali. BUG=b:158096224 TEST=Boot Trembyle and Dalboz, Dump acpi tables Change-Id: Icf8628d91e27a3afdc5fd67a53b44089c809da87 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-14mb/google/zork: Split devicetree between baseboardsRob Barnes
Split zork baseboard devicetree between dalboz and trembyle. The devicetree is simply duplicated, no other changes in this commit. BUG=b:158096224 TEST=Build coreboot for zork Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I5b26770790092c69db9567fa4337edd21a6ed809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-14mb/google/hatch: Set SA slow slew rate to 1/2 for jinlon/dratiniWisley Chen
Screen flickered on VT2 on some devices after idle a period of time. Remove SSR (1/8) setting for SA to default SSR (1/2), screen flicking issue disappeared, and didn't affect acoustic noise much. Because CB:38212 (commit eae254e) caused this issue. BUG=b:160754994 TEST=build dratini, observe that screen flick issue disapppered Change-Id: I9e81c2f15dd6babfa360eee213fc4ab6310c7455 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43284 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14mainboard/volteer: Enable SaGv for volteer2, delbin & voxelShreesh Chhabbi
SaGv needs to be enabled for only QS. On ES2, we are seeing system instability. BUG=b:159198381 TEST=Tested for boot. Power and performance tests were run with volteer2 with qs setup. System showed stability. Tested for boot stability on on delbin. Change-Id: I1bce3b9f837fb19ba5a20ae31750a73474a86788 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-14mb/google/kukui: Add new configs 'Cerise' and 'Stern'xuxinxiong
New boards introduced to Kukui family. BUG=b:160854400 TEST=make # select Cerise and Stern BRANCH=kukui Change-Id: I5841d57c0891d5191dd96097b90da889855b56c8 Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43320 Reviewed-by: Zhaoyou Hong <hongzhaoyou@huaqin.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14mb/google/volteer: config QS silicon devices for CSE LITENick Vaccaro
Configure volteer2 and delbin, the two variants currently using preQS or QS silicon, to use CSE Lite. BUG=b:158140797 TEST=cd to volteer's asset_generation folder, execute "./gen_all_variant_images.sh" and verify that all variant images are produced. Change-Id: I5e444529b090d82094b9da0df2648ea4cdb2888e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-13mb/google/zork: Fix check for variant_uses_v3_schematics()Furquan Shaikh
CB:43224 ("mb/google/zork: Add helpers for v3 schematics and wifi power enable") added helper functions for determining if a board uses v3 schematics. However, it introduced a regression by adding a wrong check for variant_uses_v3_schematics() in variant_audio_update(). This change fixes the check to ensure that dmic_gpio is updated when variant is not using v3 schematics. BUG=b:161141258,b:161128964 TEST=Verified on trembyle that trackpad works again (it was broken because of the regression). Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I0e6ad844f68cface7b545f1547bd94470c30dde4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43415 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-13mb/google/zork: Create Woomax variantKane Chen
Create the woomax variant of the zork reference board by copying the template(coreboot-zork/util/mainboard/google/trembyle) files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). BUG=b:158343602 BRANCH=None TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I0bb8ce1851f4064d24e48fd8957e2f9fe1e80b53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-12mb/google/beltino/bootblock.c: Drop unused includeAngel Pons
Change-Id: I2994b8bf5521b539a9f3585a3221452b1807837a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-12mb/google/zork: Update SPI mode to 100MHz, 1-2-2Martin Roth
Change SPI speed from 66MHz, mode 1-1-2 to 100MHz mode 1-2-2. “1-2-2" means command, address and data are transmitted through 1 wire, 2 wire and 2 wire, respectively. BUG=b:160603142 TEST=Boot on trembyle, verify register settings. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I14f96e3c085126c70e64ef3a3f5b7b54ce6cbffe Reviewed-on: https://review.coreboot.org/c/coreboot/+/43306 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12soc/intel/baytrail: Add dedicated devices for MMC and MMC 4.5 controllerMate Kukri
- Correctly detect device 17h as the MMC 4.5 controller - Support detection of the "old" MMC controller at device 10h Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Change-Id: I9f0007b1cf01df09f775c088397c3b9c846908c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-12mb/google/volteer: Convert static ASL files to new DPTF implementationTim Wawrzynczak
This patch converts the current DPTF policies from static ASL files into the new SSDT-based DPTF implementation. All settings are intended to be copied exactly. Change-Id: I964c53afbd503d47a07b982672425f0e7a986a3f Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41895 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12mb/google/dedede: Add ability to provide override GPIO tableKarthikeyan Ramasubramanian
For variants with slightly different GPIO configuration, add support to pass an override GPIO configuration table. BUG=None TEST=Build and boot the waddledee mainboard. Change-Id: I2f1c6dc2ea5499bff96a471c4461339ef01ee19a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-12mb/google/dedede/var/drawcia: support internal usb cameraWisley Chen
BUG=b:160741778 TEST=build drawcia, and check camera can be regconized Change-Id: I67bee9773b53451653abd76088d1d4062fe3da8f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42929 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12mb/google/dedede/var/drawcia:Add audio support (ALC5682 codec, MX98360A spk amp)Wisley Chen
Select the drivers for ALC5682 codec and MX98360A spk amp BUG=b:158202026 TEST=FW_NAME=drawcia emerge-dedede coreboot chromeos-bootimage Change-Id: If271f11f10a85ade6f61ff8c25bfafeb67a69af6 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-12haswell: Move some MRC settings to devicetreeAngel Pons
There's no generic way to tell whether a mainboard has an EC or not. Making Kconfig symbols for these options seems overkill, too. So, just put them on the devicetree. Also, drop unnecessary assignments when the board's current value is zero, as the struct defaults to zero already. Change-Id: If2ebac5fcab278c97dfaf8adc9d1e125888acafe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43129 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12haswell: Add function to retrieve SPD addressesAngel Pons
And use it instead of directly writing to the MRC struct. Change-Id: I7f04db29a08512c1a8b2b2300dba71cb3b84a5c5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12haswell: Automatically determine system typeAngel Pons
Check the PCH's LPC device ID to know the system type instead of relying on hardcoded numbers. The `get_pch_platform_type` function is MRC-safe. Change-Id: Icfe7c2dccb7c7a178892ad3a2e34ca93b33b2bb9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43124 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12haswell: Introduce ENABLE_DDR_2X_REFRESH Kconfig optionAngel Pons
This Kconfig symbol allows doubling the memory's refresh rate, assuming that the MRC actually cares about it. It is disabled by default except on the mainboards which explicitly enabled this setting in `pei_data`. Change-Id: I6318dad0350d1c506c67f9d117d0ae8dad871281 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12haswell boards: Drop unused romstage.c includesAngel Pons
Several of these includes are no longer necessary. Get rid of them. Since "raminit.h" already includes "pei_data.h", we can omit including the latter for brevity's sake. Change-Id: Ia7e9dadf87114ca9ea4761b89909ea035cdfc38a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43121 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12haswell: Factor out `max_ddr3_freq`Angel Pons
All mainboards choose the maximum speed of DDR3-1600. Change-Id: I8863f9d1df950b924f596689ebf1bfda5d317e06 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43120 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12haswell: Compute disabled channel masks at runtimeAngel Pons
All mainboards have a non-zero SPD address to implemented DIMM slots. Knowing this, it is possible to compute the MRC slot population masks automatically instead of hardcoding the values on each mainboard. Change-Id: Ia8f369dd1228d53d64471e48700e870e01e77837 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43119 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12mb/google/slippy: Factor out common MRC settingsAngel Pons
There's no need to redefine common settings. Change-Id: I4c6b65bce42b875bb55e8d04da44afe9c18fb6e5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12mb/google/beltino: Factor out common MRC settingsAngel Pons
There's no need to redefine common settings. Change-Id: I62f5014cf1fea093aee17023b48fd4d404279410 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12haswell: Relocate `mainboard_romstage_entry` to northbridgeAngel Pons
This is what sandybridge does, and if done properly allows factoring out common settings. Said refactoring will be handled in subsequent commits. Change-Id: I075eba1324a9e7cbd47e776b097eb940102ef4fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12haswell boards: Fix writes to 16-bit DxxIR registersAngel Pons
The DxxIR (Device xx Interrupt Route) registers in RCBA are 16-bit wide, so do not use 32-bit operations to program them. Note that the DxxIP (Device xx Interrupt Pin) registers are 32-bit, so using 32-bit operations on them is correct. Change-Id: I9699b98d5fcd26b2c710bf018f16acc65dcb634e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12haswell: Drop `struct romstage_params` typeAngel Pons
It only contains a pointer to another struct. Flatten it. Change-Id: Iab427592c332646e032a768719fc380c5794086b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12haswell: Make `copy_spd` a weak functionAngel Pons
Instead of using function pointers, we can use weak functions. So, drop the pointer from `romstage_params`, leaving `pei_data` as the only remaining member. This will be cleaned up in a follow-up commit. Change-Id: I3b17d21ea7a650734119a5cab4892fcb158b589d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-11mb/google/beltino: Move Super I/O init to bootblockAngel Pons
Also remove an unneeded `pch_enable_lpc` function call. Change-Id: I83158a655670d4e6cd91f6bf3332d1b6f9f655d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-07-10mb/google/zork: Rename get_gpe_table to variant_gpe_tableRaul E Rangel
This matches the other methods. BUG=b:154756391 TEST=Build trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6ba1fc5756c17da4dc1727425af17c4582c01a18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-10mb/google/volteer: remove ripto variantNick Vaccaro
BUG=b:160711124 TEST="FW_NAME=ripto emerge-volteer coreboot chromeos-bootimage" and verify that the build does not fail. Change-Id: Ic132256a192b8cb77662963bea844f193eb912d9 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-10mb/google/zork: enable i2c devices in verstageMartin Roth
Zork devices shut down the i2c controllers in S3 to save power. On resume, they need to be enabled in verstage before being accessed or the system hangs. BUG=b:160834101 TEST=Resume works with psp_verstage. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I7b8c7e12847876dab4ca74d67d3c41e63d7727cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/43334 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10AMD mainboards: Drop commented-out includeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I6f71419ea23b973b0bedb426e20cb3dc460ef68d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43271 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09ACPI: Drop commented-out DSDT DefinitionBlock instancesAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I9b5589d4596eead83a5897b083ccb85ef05a03d5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43270 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09haswell: Drop GPIO indirection layersAngel Pons
This simplifies things and makes type checking possible. Change-Id: Iefc9baabae286aac2f2c46853adf1f6edf01586f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-09mb/google/slippy: Put GPIOs in a C fileAngel Pons
This will allow dropping the pointer inside romstage_params. Change-Id: Iec6dac1a271b22d6c09b4064a9e8a310e57026a6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-09mb/google/beltino: Put GPIOs in a C fileAngel Pons
This will allow dropping the pointer inside romstage_params. Change-Id: I536225351a0353298381c16cff25f39098c19bba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-09haswell: Turn RCBA configuration into a functionAngel Pons
Instead of passing around a pointer to an array, just write the relevant registers directly. Note that intel/baskingridge used spaces to indent line continuations and had to be replaced with tabs to quell Jenkins. Change-Id: Ifa06a2ab24da9b8c6aac6480542fa32d04f6d6fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-09soc/intel/baytrail: Rename "pmc.h" to "pm.h"Angel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I3d4c1285bdc4b061383b7bb6262f69671166b9c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-07-08mb/google/zork: Do not select VARIANT_SUPPORTS_PRE_V3_SCHEMATICS for VilbozFurquan Shaikh
This change drops the selection of VARIANT_SUPPORTS_PRE_V3_SCHEMATICS for Vilboz since it did not have any build with pre-v3 schematics. Change-Id: I3919ad43e1dae95a4fa71073e83865e92f30dfec Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43225 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/google/zork: Add helpers for v3 schematics and wifi power enableFurquan Shaikh
This change adds following two helper functions: 1. variant_uses_v3_schematics() - Check whether the variant is using v3 version of schematics. 2. variant_has_active_low_wifi_power() - Check whether the variant is using active low power enable for WiFi. In addition to this, Kconfig options are reorganized to add two new configs - VARIANT_SUPPORTS_PRE_V3_SCHEMATICS and VARIANT_SUPPORTS_WIFI_POWER_ACTIVE_HIGH. This allows the helper functions to return `true` early without checking for board version. Eventually, when a variant decides to drop support for pre-v3 schematics, it can be dropped from selecting VARIANT_SUPPORTS_PRE_V3_SCHEMATICS. Similarly, when the variant decides to drop support for active high power enable for WiFi, it can be dropped from selecting VARIANT_SUPPORTS_WIFI_POWER_ACTIVE_HIGH. Change-Id: I62851299e8dd7929a8e1e9a287389abd71c7706c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43224 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/google/zork: Move GPIO_137 configuration to ramstageFurquan Shaikh
This change moves the configuration of GPIO_137 to happen in ramstage since there is nothing in coreboot that requires the state of write protect GPIO for zork. Change-Id: Ibaf8e7d9dd5d13a9b39b10ac0174de345b8380f5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43223 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/google/zork: Do not share "write protect" information with depthchargeFurquan Shaikh
This change removes "write protect" entry from the list of GPIOs shared with depthcharge as done for other Chrome OS boards in CB:39318. Change-Id: Ibd39e8d6835e465b2ab5eebcc245e45db5d84deb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43222 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08sb/intel/lynxpoint: Factor out RCBA Function DisableAngel Pons
Comments stating that this was mainboard-specific were very wrong. Change-Id: I7026ca9c7dabd01b4a0c0549b697e006d5f75eb8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-08mb/google/slippy: Factor out common romstage settingsAngel Pons
There's no need to repeat the same values over four variants. Change-Id: Ifc4a9961fe9c87f15a6039e6e478682fab5b0bb7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-08mb/google/zork: Enable psp_verstageMartin Roth
Finally enable psp_verstage for zork. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: If6a12c2074d7c84c0cb766393c66f5eff29a58d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08mb/google/waddledee: Enable AudioMaulik V Vaghela
1. Enable HDA Pci device in devicetree 2. Enable I2C4 in devicetree and fill ACPI information 3. Pass correct IRQ GPIO for headset jack BUG=None BRANCH=None TEST=Audio playback and recording works on Waddledee. Change-Id: I77aaa27bb29460ef834c3dd090ced868f2e99616 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Yong Zhi <yong.zhi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41765 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/google/dedede/var/drawcia: add elan touchscreenWisley Chen
BUG=b:155002684 TEST=build drawcia, and check touchscreen can work Change-Id: Ib6a190d2f6fc5132af0e58c6df9919381e88f699 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-08mb/google/dedede/var/drawcia: Support Elan touchpadWisley Chen
BUG=b:155002811 TEST=build drawcia, and check touchpad can work. Change-Id: I674236aa6937a0444a85e6b8e2fb9a7925b56f5c Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42922 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07google/trogdor: Add new variant PompomJulius Werner
This patch adds a new variant called Pompom that is identical to Lazor for now. Also reorder variants alphabetically while we're here. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I5a0f297413765bce8353d5a781f0f67446de4e7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/43147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-07-07mb/google/vilboz: Drop gpio.c from variants/vilbozPeichao Wang
Update GPIOs since Vilboz hardware design follow schematic V3.2, so gpio.c is unnecessary. BUG=b:157744136 BRANCH=NONE TEST=flash the bios to vilboz DUT and test touchpad function Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I575f8b233b56185f3281ad7127bc274bda5ea801 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42986 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/google/vilboz: Fix variant ID for v3+ schematics for vilbozPeichao Wang
At this moment, Vilboz board version is 1 and it according to v3+ schematics, however WiFi power enable is active high. This change sets VARIANT_MIN_BOARD_ID_V3_SCHEMATICS for Vilboz as 1 and VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW as 2. BUG=b:160547115 BRANCH=None TEST=flash the bios to vilboz DUT and test WIFI module Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I9699bb839a801ab7d14c38b971ec28e3a322a997 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-07mb/google/volteer: Change ov2740 HID of Chrome driver to match withDaniel Kang
Windows definition There was a review comment for Chromium Linux ov2740 driver that Windows driver already set the HID as INT3474 and suggested to have the same value for Chrome. The upstreamed Linux driver code has INT3474 as HID and this patch is to set the same HID in ACPI configuration. https://patchwork.kernel.org/patch/11540753/ BUG=b:160334865 BRANCH=none TEST=User-facing camera should work with the driver which set the HID as INT3474 Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I10e98d32899f31d91c1cc7ddfa099af73d8aef37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43006 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/google/volteer: Fix world-facing camera LED is always on issueDaniel Kang
Volteer world-facing camera has a privacy LED and it is supposed to be turned on only when the camera is being used. But the LED is always on and this is to fix the issue. RCAM_SNR_PWR_EN (RearCAMera_SeNsoR_PoWeR_ENable) GPIO, which controls the world-facing camera LED, was not in the power-up and power-down sequence definitions and this caused the issue. BUG=b:160341981 BRANCH=none TEST=Build and boot volteer proto 2 board. Start a camera app and check the world-facing camera LED is only turned on only when the camera is working. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I564690baffddfdd0f998525992643aaf16ba4b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42985 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/google/zork: update telemetry settings for dalbozChris Wang
update telemetry value for SDLE test result. BUG=b:152922299,b:152369472 TEST=emerge-zork coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I14d218243931271ba15ec4113e9bc46c670fb2ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/42999 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/google/volteer/var/terrador: Update gpio settings and overridetree.cbDavid Wu
Based on schematic and gpio table of terrador, generate gpio settings and overridetree.cb for terrador. BUG=b:156435028,b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Verify that the image-terrador.bin is generated successfully. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42302 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/google/volteer/var/terrador: Add memory parts and generate DRAM IDsDavid Wu
This change adds memory parts used by variant terrador to mem_list_variant.txt and generates DRAM IDs allocated to these parts. Added memory 1. MT53E512M64D4NW-046 WT:E 2. MT53E1G64D8NW-046 WT:E BUG=b:159195585,b:152936481,b:156435028 TEST="emerge-volteer coreboot chromeos-bootimage", flash terrador and verify terrador boots to kernel. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia14f76e9cb0df64961d46f4b61b39439e56f6a8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41995 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06trogdor: Add board variant checks in KconfigRavi Kumar Bokka
Diffentiate Lazor and trogdor build configuration Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I3ad413ea6e658e939796bebdff8c1e0dd76417cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/42730 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/google/volteer: Enable HotPlug on PCIe root port for the SD expressnick_xr_chen
Enable HotPlug for the PCIe root port that the SD express is on so the OS can re-train the link without needing a reboot if it goes down unexpectedly at runtime. BUG=b:156879564 BRANCH=master TEST=enable HotPlug on Volteer Root Port 7 (SD express) and check in linux that it is identified as a HotPlug capable root port Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: Ie9d427dd297567f06123119a670b5ed2e1f73701 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42897 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/google/volteer: Rename remaining pmc_mux/con to connPatrick Georgi
CB:43090 renamed con to conn to avoid issues when building on Windows. CB:42905 introduced more uses of the old name. Adapt the latter to comply with the former. Change-Id: I723141add5452fc541f67cb8591793f2d64cc231 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43141 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/google/volteer/var/voxel: Update gpio settings and overridetree.cbDavid Wu
Based on schematic and gpio table of voxel, generate gpio settings and overridetree.cb for voxel. BUG=b:157879197,b:155062762 TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage Verify that the image-voxel.bin is generated successfully. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I49c1923e63d87f11de362fd893905ac2f1137bba Reviewed-on: https://review.coreboot.org/c/coreboot/+/42731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-06mb/google/zork: Apply cereme telemetry settings for dalbozChris Wang
Currently, the telemetry settings are not for the pollock platform and might causethe power and performance issue. so applied the Pollock reference board settings to Dalboz to improve the performance, and the values need to be updated after the SDLE test finished. BUG=b:157961590,b:152922299 TEST=Build. Change-Id: I0da5b81afaa5814c13ec0257dc0eb3471be94c29 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2228257 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42998 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/google/zork: Apply USB2 default phy tune parameter for Zork familyChris Wang
Apply the default USB2 phy tuning parameter for Zork family BUG=b:155132211 TEST=Build, verified the default value been applied on trembyle and the USB2 device works well. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I1f00b04173796d70147e232bafa405487b0761e1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2260216 Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42997 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/google/volteer: Add support for passive USB-C daughterboardCaveh Jalali
The USB-C SBU and HSL orientation configuration depends on the USB daughterboard used on the system. This patch adds an additional configuration for supporting passive USB daughterboards using "probe" directives to select the appropriate configuration at runtime. BUG=b:158673460 TEST=verified active USB DBs enumerate at USB3 speeds in linux Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: Ia4bd97de8f974531f97469a5e47ecf4d948beca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-06mb/google/dedede: Create Boten Legacy variantKarthikeyan Ramasubramanian
Upcoming builds of boten will use 16 MiB SPI ROM. So create a legacy Boten variant to support the builds that use 32 MiB SPI ROM. BUG=None TEST=Build the boten and boten_legacy variant. Cq-Depend: TBD Change-Id: Idf7732768aa7fbf2281a4cbf47b7b5b4f8ef51da Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-07-06mb/google/dedede: Create Drawcia Legacy variantKarthikeyan Ramasubramanian
Upcoming builds of drawcia will use 16 MiB SPI ROM. So create a legacy Drawcia variant to support the builds that use 32 MiB SPI ROM. BUG=None TEST=Build the drawcia and drawcia_legacy variant. Cq-Depend: TBD Change-Id: Ifb5a4778abe38a396e35963a3270b0d3cc9809e0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-07-05mb/google/zork: Drop check for ENV_RAMSTAGE in mainboard_ec_initFurquan Shaikh
This change drops the check for ENV_RAMSTAGE in mainboard_ec_init() since it is included only in ramstage. Also, the content of ramstage_ec_init() is moved into mainboard_ec_init(). Change-Id: I282fb07a80f4de6064a544f6dd58e8f973a597b9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43118 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/google/zork: Drop mainboard_ec_init() from romstageFurquan Shaikh
mainboard_ec_init() does nothing in any stage other than ramstage. So, this change drops the call to mainboard_ec_init() from romstage.c. Additionally, it also drops ec.c from romstage and verstage. Change-Id: Iae0be4d678b0780cf532000a6c0fff1bce333c0e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43117 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/google/zork: Drop unused function variant_romstage_entry()Furquan Shaikh
This change drops the function `variant_romstage_entry()` which is unused on zork. Change-Id: I140ab3e837971c4c7dbef5d27616043b5fc6c2c9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43116 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/google/zork: Use SSDT generator for Chrome EC audio codec deviceFurquan Shaikh
This change drops the inclusion of codec.asl in DSDT for `GOOG0013` device and instead uses the newly added Chrome EC audio codec driver for filling in the device node in SSDT. TEST=Verified that following node gets generated: Scope (\_SB.PCI0.LPCB.EC0.CREC) { Device (ECA0) { Name (_HID, "GOOG0013") // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (_DDN, "Cros EC audio codec") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } } Change-Id: I3e626ce01a3735ac2c966c0e95310be4c828b241 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43042 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 13:22:07 +0000