| Age | Commit message (Collapse) | Author |
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when S0ix returns S0, PERST needs to delay until
Main 3V3 is stable and then pull up
BUG=b:313976507
TEST=emerge-rex coreboot,measurement waveform verify pass
Change-Id: I33a86e52fab3c5c8cba6ebed0cbdd1b88b6538b0
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79320
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For EVT SCH:
1. Use GPP_D15 to control AVDD and AFVDD simultaneously for MIPI Camera.
2. Delay reset for 5ms when device power on.
BUG=b:312663347
TEST=1. Google Camera app working
2. Passed EA verified
Change-Id: I880fb309fcef006090e2849fa6c3a0d472851851
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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With 1ms delay, reset is de-asserted too soon, before power is fully
up, causing a glitch to the reset signal. The issue is resolved with
4ms delay.
TEST=tested on google/jinlon device and observed the issue is resolved.
BUG=b:260253945
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I4efe916824cc193a7c2db7599b37f0d4de40bfce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79474
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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BUG=b:312099281
TEST=Build and boot to Karis. Verify the config from serial logs.
w/o this CL -
```
[SPEW ] ------------------ CNVi Config ------------------
[SPEW ] CNVi Mode = 1
[SPEW ] Wi-Fi Core = 1
[SPEW ] BT Core = 1
[SPEW ] BT Audio Offload = 0
[SPEW ] BT Interface = 1
```
w/ this CL -
```
[SPEW ] ------------------ CNVi Config ------------------
[SPEW ] CNVi Mode = 1
[SPEW ] Wi-Fi Core = 1
[SPEW ] BT Core = 1
[SPEW ] BT Audio Offload = 1
[SPEW ] BT Interface = 1
```
Change-Id: Icd2c42261fdcfa5aac17be28fde3804348ddf9b4
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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1. Anraggar doesn't support SDCard, so disable SDCard contorller.
2. Not disabling it will cause can't enter S0ix on first suspend.
BUG=b:313585586
TEST=1. check lspci
2. can enter S0ix on first suspend
Change-Id: Ie4747d9c5d6ae93d29ef78b629855e0dd320c4db
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This file is identical to the copy currently found in the blobs
repository; it is simply being relocated for consistency and since it
does not need to be in an external repo.
BUG=none
TEST=build/boot skyrim
Change-Id: I352f58e0d3965356f3282a2653c6c11b44853857
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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This file is identical to the copy currently found in the blobs
repository; it is simply being relocated for consistency and since it
does not need to be in an external repo.
BUG=none
TEST=build/boot guybrush
Change-Id: Ice4cbaccca13e9c4ae246fdcde5c89aa2086f1e1
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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This file is identical to the copy currently found in the amd_blobs
repository; it is simply being relocated since it is mainboard specific
and does not need to be in an external repo.
BUG=none
TEST=build/boot morphius
Change-Id: Ia78fcd065fbf4d5ba6ec4edc3f8f937badf66ecc
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79591
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For initial debugging, we want to disable SW syncing. Will re-enable
in the future.
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
run gbb_utility --get --flags <image>
make sure that it returns 0xa39
Change-Id: I865e9585ab37d1328a0ff54c6343cdad2c02220c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79569
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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The default EPP is set at 50%, which is deemed insufficiently
aggressive for meeting the MTL performance expectations in
balance_performance mode.
# cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference
balance_performance
# iotools rdmsr 0 0x774
0x0000000080003f06
EPP=45% is giving the required performance in MTL.
# iotools rdmsr 0 0x774
0x0000000073003d06
NOTE: Kernel changes are necessary to ensure that the EPP (Energy Performance Preference) configured in the BIOS is not overwritten: https://patchwork.kernel.org/patch/13461932
BUG=b:314275133
TEST=Build and boot.
Change-Id: I1953994cdb4e9363fdd4b4728e3e5236276c06c8
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79386
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Non-touchscreen sku will set related GPIOs to NC. If touchscreen enabled
in overridetree for non-touchscreen sku, the boot time will be 6-7s. Set
touchscreen probed to TOUCHSCREEN_UNKNOWN for reduce boot time from 6-7s
to under 1s.
BUG=b:316434359
BRANCH=firmware-nissa-15217.B
TEST=Boot time (cbmem -t) from 6,460,972 to 922,844
Change-Id: I016ce762f726b7624bd060284f74f0992cb129b6
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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FSP default value for LpDdrDqDqsReTraining is 1. For boards
that didn't set LpDdrDqDqsReTraining to any value, 0 was being
assigned and it caused black screen issue.
BUG=b:302465393
TEST=Boot to OS with debug FSP, check LpDdrDqDqsReTraining = 1
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I301a6e43f2944ffbc63431393378ab8b23450032
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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The original DA7219 is designed to use a 500ohm mic detection
threshold. Some headset mics (e.g. Logitech H111) have a lower DC impedance that is lower than the threshold and thus cannot be
detected. Lower the threshold to 200ohm to match the new default
value provided by Renasas as in https://patchwork.kernel.org/project/alsa-devel/patch/20231201042933.26392-1-David.Rau.opensource@dm.renesas.com/ to support such headsets.
BUG=b:314062160,b:308207450
Change-Id: I6415e84a4622e0c61bc74b94536fe734048a043f
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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FSP default value for LpDdrDqDqsReTraining is 1. For boards
that didn't set LpDdrDqDqsReTraining to any value, 0 was being
assigned and it caused black screen issue.
BUG=b:302465393,b:315739133
TEST=Boot to OS with debug FSP, check LpDdrDqDqsReTraining = 1
Change-Id: I5d61301fddac6630bb1c48e992dd76e5cf02a272
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79533
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Change GPP_B14 from UP_20K to NONE for compatible
with DVT1 and DVT2 board
BUG=b:272447747
TEST=enable usb OC2 function to ensure USBA work normal
Change-Id: Ib7720980335660f423b3a74199ceedc113ec70df
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79431
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update DTT settings based on the suggestion of the thermal.
BUG=b:313833488
TEST=emerge-nissa coreboot
Change-Id: I2296990062cadc05202e3d1ab90af04234bda885
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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1. Ref to SCH, LTE use USB3 Port3, enable it.
2. Explicitly define the use of USB3 Port1 & USB3 Port2.
BUG=b:315061146
TEST=can pass PCIe Hardware Compliance Test
Change-Id: I03d6925020012fa740bbd0168a2f5b02ea6763b4
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change code style to be compatible with Nissa's format:
register "option" = "{
[0] = value /* comment */
...
}"
to
register "option[0]" = "value" /* comment */
BUG=none
TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar
Change-Id: I60659bd44813173f9b984216473a0919c5f331b8
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add the MICRON MT62F1G32D2DS-023 WT:B RAM part for brox:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
MT62F1G32D2DS-023 WT:B 2 (0010)
BUG=b:311450057,b:315913909
BRANCH=None
TEST=Run part_id_gen tool without any errors
Change-Id: Id120a5eb311d8299a8e59d2c1658fe0742e93934
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Adjust PL1 max value from 15W to 25W
BUG=b:314263021
TEST=emerge-rex coreboot
Change-Id: I4122a13d7e33c736299c1a759ec51f7a3b29340f
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79377
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update proximity sensor tuning value from dedede/kracko tuning.
Remove GPIO override to use the configuration from nissa baseboard:
- GPP_B5 ==> SOC_I2C_SUB_SDA
- GPP_B6 ==> SOC_I2C_SUB_SCL
BUG=b:310050220
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I7c687677a797415d80be4c420484d3346a8455f6
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79247
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Updated Linux FW works with PCI gen3 speed and PSPP.
This reverts
commit 05c9a850fd21 ("mb/google/nipperkin: Fix WLAN to GEN2 speed")
https://review.coreboot.org/c/coreboot/+/63593
and
commit 76fddd963925 ("mb/google/nipperkin: Disable PSPP for WLAN")
https://review.coreboot.org/c/coreboot/+/63722
The changes are overlapped and are reverted together.
BUG=b:240426142 & b:228830362
The system is able to ran over 2500 cycles on Nipperkin with command
suspend_stress_test -c 10000 --wake_min 10 --suspend_min 10 \
--nofw_errors_fatal
The whole variant_update_dxio_descriptors is empty and is pushed back
to weak function.
Change-Id: Id207076542edc8ea0cabc6e02e29856c2b6803c7
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
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Enable BT offload when I2S option is selected for screebo.
BUG=b:275538390
TEST=Verified audio playback using BT speaker/headset in I2S mode on google/screebo.
Fixes: https://review.coreboot.org/c/coreboot/+/77755
Change-Id: I7ebe8e28d35428ce2fb8129dc145fec9ac60f9da
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79378
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Due to TCPC0 & TCPC1 exchanged compare to Neried design,
but related USB2 Ports not exchanged, keep mainboard C port to conn0.
BUG=b:312998945
TEST=can boot from external Type-c USB disk
Change-Id: Ib8df4a256bd9cd1b2ca229b09d68f97babc8092e
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Update brox devicetree based on the latest schematics.
- Configure typeC to EC mux ports settings.
- Configure USB2/USB3 ports settings.
- Configure TCSS ports settings.
BUG=b:311450057
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: Iac5a2e8be6cea64f107d267d4cf71529f08bb63d
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79391
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the support LP5 RAM parts for brox:
1. HYNIX LPDDR5 6400 2GB H9JCNNNBK3MLYR-N6E
2. MICRON LPDDR5 6400 4GB MT62F1G32D4DR-031 WT:B
DRAM Part Name ID to assign
H9JCNNNBK3MLYR-N6E 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
BUG=b:311450057
BRANCH=None
TEST=Run part_id_gen tool without any errors
Change-Id: Ib17f26a310435e37088191594863a645aa751440
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79392
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=b:305793886
TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku
Change-Id: I41a64252f08304ffc66fd782e54720252064ca49
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Fix up the memory config for brox based on the schematics. Also,
since memory training needs to happen in romstage, initializing the
MEM_STRAP & MEM_CH_SEL gpios for use in romstage. Also consolidating
the GPIOs needing to be initialized in romstage into the baseboard
gpio.c file.
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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This patch allows variants to override the default baseboard PLx
limits.
Additionally, rearrange the include header files alphabetically.
BUG=b:313667378
TEST=Able to boot google/screebo with modified power limits.
Before:
[DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/rex/
ramstage.c/variant_devtree_update called
[INFO ] Overriding power limits PL1 (mW) (10000, 15000)
PL2 (mW) (40000, 40000) PL4 (W) (84)
After:
[INFO ] Overriding power limits PL1 (mW) (10000, 15000)
PL2 (mW) (40000, 40000) PL4 (W) (84)
Change-Id: Ic66872c530963238a0bf5eebbd5b5a76a7985e5c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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+-------------+----------------+------------+
| USB 2.0 | Connector Type | OC Mapping |
+-------------+----------------+------------+
| 1 | Type-C | OC_0 |
+-------------+----------------+------------+
| 2 | Type-C | OC_0 |
+-------------+----------------+------------+
| 3 | Type-C | OC-0 |
+-------------+----------------+------------+
| 4 | Type-A | OC_3 |
+-------------+----------------+------------+
| 5 | Type-C | OC_0 |
+-------------+----------------+------------+
| 6 | Type-A | OC_3 |
+-------------+----------------+------------+
| 7 | Type-A | OC_3 |
+-------------+----------------+------------+
| 8 | Type-A | OC_3 |
+-------------+----------------+------------+
| 9 | Type-A | OC_3 |
+-------------+----------------+------------+
| 10 | BT | NA |
+-------------+----------------+------------+
+---------------------+-------------------+------------+
| USB 3.2 Gen 2x1 | Connector Details | OC Mapping |
+---------------------+-------------------+------------+
| 1 | Type-A | OC_3 |
+---------------------+-------------------+------------+
| 2 | Type-A | OC_3 |
+---------------------+-------------------+------------+
+------+-------------------+------------+
| TCPx | Connector Details | OC Mapping |
+------+-------------------+------------+
| 1 | Type C port 0 | OC_0 |
+------+-------------------+------------+
| 2 | Type C port 1 | OC_0 |
+------+-------------------+------------+
| 3 | Type C port 2 | OC_0 |
+------+-------------------+------------+
| 4 | Type C port 3 | OC_0 |
+------+-------------------+------------+
BUG=b:305793886
TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I90d3d984af6d40efb4553cf5675617700161d2d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add default Intel DPTF.
BUG=b:305793886
TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Id681754fc8e7b418de35f66df097cadd4aad7448
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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google/deku is a Chromebox featuring two LAN ports.
Add overridetree.cb entry to configure the LAN0 LAN1 devices.
BUG=b:305793886
TEST=Built FW image correctly.
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I8980dabc7f9fc731a2b60c599e1e48c9b11dabb4
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79292
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch adds the power limit configuration for MCH ID index 3 aka
0x7d14 DID which is identical to MCH ID 0x7d01 (index 1).
TEST=Able to perform power limit configuration for google/ovis.
[DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/ovis/
ramstage.c/variant_devtree_update called
[INFO ] Overriding power limits PL1 (mW) (19000, 28000)
PL2 (mW) (64000, 64000) PL4 (W) (120)
Change-Id: Iff71adb4e26d18970b5947927c258419f751de32
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79332
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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This patch removes the deprecated PL_PERFORMANCE and PL_BASELINE
configurations, relying instead on the refactored power limit flow.
This flow allows for seamless overrides by the baseboard and/or by
the variant board, if necessary.
Specifically, this patch:
- Removes PL_PERFORMANCE and PL_BASELINE configuration options from
mainboard.c in the google/rex directory.
- Relies on the baseboard_devtree_update() function, which is
implemented by the respective baseboard, to handle power limit
configuration.
- Leverages the variant_devtree_update() function, which is a
__weak implementation, to allow overrides by the variant directory.
This simplification improves code readability and maintainability while
maintaining the flexibility to handle power limit configurations as
needed.
Change-Id: I872e5cb59d7b2789ef517d4a090189785db46b85
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79331
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch expands the power limit override capability to include
variants directories, enabling them to modify power limit settings
configured by the baseboard.
Previously, only the baseboard could override power limit settings.
For instance, while the google/rex baseboard sets the PL1 max power
limit to 15W, the google/screebo variant couldn't override this value.
This enhancement empowers variants directories to override baseboard-
configured power limit settings, allowing for greater flexibility and
control over power limits.
BUG=b:313667378
TEST=Able to call into _weak implementation of `variant_devtree_update`
unless there is one override.
[DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/rex/
ramstage.c/variant_devtree_update called
[INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW)
(40000, 40000) PL4 (W) (84)
Change-Id: Ib07691625e075b0fbab42271512322ffc60ba13b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Trim all GPIO comments like "origin ==> current".
BUG=b:304920262
TEST=pass building
Change-Id: I05daa4df16b6da3d3f971b75c7c467032e3f854d
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79321
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix GPP_D6 configuration for LTE power enable.
BUG=b:304920262
TEST=mmcli -m any
Change-Id: I2996fd35c2897269997bc0290e0ce93bbbaa1bf8
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79166
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
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Due to TCPC0 & TCPC1 exchanged compare to Neried design,
but related USB2 Ports not exchanged.
BUG=b:304920262
TEST=Tpye-C & DP functions workable
Change-Id: I9dacf06b1e672575a684856acdb10b6c88360b18
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79165
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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For proto PCB:
GPP_C0 for enable power supply which also for sensor subsystem.
GPP_C0 must allways turn power on, so GPP_C6 is not only used
for enable function but also for stop report.
BUG=b:304920262
TEST=1. touchscreen function workable
2. INT pin no active during suspend
Change-Id: I7dabf205dba616f57ef9717f950eba96282d8e3d
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
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Update overridetree to correct AUX pin to USB-C port 3
BUG=b:299570339
TEST=emerge-brya coreboot chromeos-bootimage
Change-Id: I3a5a89c6008fbf28c927f83060e6e508d60845ba
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79343
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Brox has SSD and UFS storage per different SKU.
1. Set SSD on CPU PCIe port (PCIEX4_A) and configure related gpio
settings according to the schematic.
2. Enable UFS, also enable ISH since it is PCI function 0, required
for UFS function 7 to be enabled.
3. Set unused SRCCLKREQ signals to NC.
4. Remove unused gpio settings in variant gpio table to prevent
unexpected overrides.
BUG=b:311450057
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I88922bcfa13652006aa10078c3c444624fd4575e
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79295
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on Platform Mapping Document for Deku (go/cros-deku-mapping)
from Nov 8, 2023 (Rev 0.4)
BUG=b:305793886
TEST=WIP, not tested yet
Change-Id: Ib37a7ebf0aca788d14fafea0f97e364beafb4c4d
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78960
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Use fw_config to differentiate audio amps instead of the
kconfig option.
BRANCH=corsola
BUG=b:305828247
TEST=Verify devbeep in depthcharge console
Change-Id: I5f887f5e0d16dc14039fb12b636257d01339b2de
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79309
Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Quandiso does not use DB_1C, replace the fw_config with LTE only
daughterboard.
BUG=b:312094048
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Id7129e52d3733f62405f9d766f08563f05016c69
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79297
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Shawn Ku <shawnku@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since lars has two touchscreen options, we need to determine which (if
any) are present on a given device at runtime so that there are not
multiple ACPI touchscreen devices (as it makes Windows unhappy).
Implement power sequencing and runtime detection for both touchscreen
options.
TEST=build/boot Win11/Linux on google/lars, verify touchscreen detected
and functional under both OSes.
Change-Id: I49ccb29ec4589315a4abe3c0ea8fa76f97080bcd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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LARS has a Melfas touchscreen option, so add an entry for it. Adapted
from Chromium branch firmware-glados-7820.315.B, commit a26fe552569f
("Chell: Update DPTF parameters for CPU").
TEST=build/boot Linux on google/lars with Melfas touchscreen, verify
functional.
Change-Id: Idecd572335d7d5d52e4f89e85ebf7f0c90f23751
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79310
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable MIPI camera for anraggar project.
Sensor: OV13B10-GA5A
Driver: DW9714V
EEPROM: GT24P64E
Ref to SCH, use MIPI 4-lane serial output interface.
BUG=b:309518095
TEST=Google Camera app working
Checking log with:
coreboot log:
\_SB.PCI0.I2C2.CAM0: Intel MIPI Camera Device I2C address 036h
\_SB.PCI0.I2C2.VCM0: Intel MIPI Camera Device I2C address 0ch
\_SB.PCI0.I2C2.NVM0: Intel MIPI Camera Device I2C address 050h
kernel log:
kernel: [ 6.140429] intel-ipu6-isys intel-ipu6-isys0: bind ov13b10 11-0036 nlanes is 4 port is 1
cros_camera_service[4755]: Read camera eeprom from /sys/bus/i2c/devices/i2c-PRP0001:02/eeprom
cros_camera_service[4755]: Probing media device '/dev/media0'
cros_camera_service[4755]: Probing sensor 'ov13b10 11-0036' (v4l-subdev17)
cros_camera_service[4755]: Found V4L2 sensor subdev on /sys/devices/pci0000:00/0000:00:15.2/i2c_designware.2/i2c-11/i2c-OVTIDB10:00/video4linux/v4l-subdev17
Change-Id: I6a82557c94203f24449588a6005abc53cc29ca76
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79163
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arec Kao <arec.kao@intel.corp-partner.google.com>
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Intel CNVi WLAN's BT uses USB2 Port 10 inside the SOC,
and the relevant configuration needs to be modified in overridtre.cb.
BUG=b:304920262
TEST=lsusb
ID 8087:0033 Intel Corp.
rfkill list
hci0:Bluetooth
Change-Id: Ibcae800836c17307bc133de5a91658f6dda5985c
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79055
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Anraggar cannot boot into OS and kernel loading failure.
Update eMMC DLL values to improve initialization reliability
- Sending different speed TX/RX command/data signal to eMMC and check
the response is success or not.
- Collecting every eMMC that use for the project
- Based on above result to provide a fine tune DLL values
BUG=b:308366637
TEST=Cold reboot stress test over 2500 cycles
Change-Id: I9ec3cc23000301aa72aed96e74b63114623c4fc2
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78851
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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As customer demand, it is necessary to set MSR Package Power Limit-1 to 17W for the DTT setting to optimize performance.
The PL1 value (17W) suggested by the thermal team which is different from the reference code(PL1=15W).
BUG=b:312321601
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Built and booted into OS, and confirm MSR PL1=17W correctly.
Change-Id: If7874d26038118c5605cf0721c30e681b45123fe
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79335
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch moves the SOC_INTEL_STORE_ISH_FW_VERSION config from the
Nissa baseboard to BOARD_GOOGLE_BRYA_COMMON. This allows all baseboards
to retrieve the ISH version and store it into memory.
Ensure SOC_INTEL_STORE_ISH_FW_VERSION is enabled only for platforms
with ISH support (DRIVERS_INTEL_ISH).
Additionally, the dedicated SOC_INTEL_STORE_ISH_FW_VERSION config
selection for the Nissa baseboard is no longer needed.
BUG=b:280722061
TEST=Able to build and boot google/marasov.
Change-Id: I99dab43ae4e13869b7f8797a9c4014f60e38a595
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79338
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
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Change GPP_B14 from NC to NF
BUG=b:272447747
TEST=enable usb OC2 function to ensure USBA work normal
Change-Id: Ie0f112bcf183870869d0c1b9a223d4231600a300
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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On Brox, TPM is using i2c4 and GPP_E2, so modifying the Kconfig to
reflect this. Also, fixing up the TPM entry in the device tree.
Making sure that the GPIO for GSC_PCH_INT_ODL is set correctly.
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79102
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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Add taeko new supported memory parts in mem_parts_used.txt, generate
spd-3.hex for these parts.
1. Samsung K4UBE3D4AB-MGCL
2. Micron MT53E1G32D2NP-046 WT:B
BUG=b:312363368
TEST=Use part_id_gen to generate related settings
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I221ad3f490f24b43fe1ccd211014787eab5d1038
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
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Enable BT audio offload of ALC1019_ALC5682I_I2S based on fw_config.
BUG=b:299510759
TEST=Build and boot to Screebo. Verify the config from serial logs.
w/o this CL -
```
[SPEW ] ------------------ CNVi Config ------------------
[SPEW ] CNVi Mode = 1
[SPEW ] Wi-Fi Core = 1
[SPEW ] BT Core = 1
[SPEW ] BT Audio Offload = 0
[SPEW ] BT Interface = 1
```
w/ this CL -
```
[SPEW ] ------------------ CNVi Config ------------------
[SPEW ] CNVi Mode = 1
[SPEW ] Wi-Fi Core = 1
[SPEW ] BT Core = 1
[SPEW ] BT Audio Offload = 1
[SPEW ] BT Interface = 1
```
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I6c713752f3f0bf58b5ebd78b904e773fdbf16e06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77755
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
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Add PIXA touchpad for variants of craask.
BUG=b:310489697
TEST=build craask firmware and test with PIXA touchpad
Change-Id: I7e68a44eb3d639eaadb5b7b9cb5a6955fd059eeb
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
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In nissa platform, we configured GPP_F17 as SCI+APIC to wake the system
and also generate IRQ to the IOAPIC. Currently, we set GPP_F17 to level
triggered and it causes AP (Application Processor) to keep sending
GET_NEXT_EVENT to EC during resume from suspend by connecting AC.
So we change GPP_F17 to edge triggered to avoid this condition.
BUG=b:308716748
TEST=Original failure rate was 7 out of 10 times and it reduced to
0 out of 60 times on six joxer systems.
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I3ceb1dfce46376a6a9a8c6cb6d691d818a0a42ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79244
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
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Probe usb ports by FW_CONFIG setting to disable C1 port on quandiso new daughterboard without C1 port.
BUG=b:312094048
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I6f702f60c772176e80b3452bf957d10625564102
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79173
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The DPTF parameters were defined by the thermal team.
Based on thermal table in 290705146#comment17.
BUG=b:290705146
BRUNCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I02b4187000eec9990bf10a57875b23007f7bdd12
Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79183
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables the FSP (Firmware Splash Screen) rendering feature
for all Rex variants, including chromeboxes like Ovis. This will allow
users to see the FSP logo during the boot process.
BUG=b:284799726
TEST=Verify that the FSP logo is displayed during the boot process on
an google/ovis chromebox.
Change-Id: I73d82e16f70ffdc8cb168506c86d9c4e9a92c38d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Set pen detect pin to NC base on fw_config.
BUG=b:304680060
TEST=emerge-rex coreboot pass
Change-Id: Icf9171fca49cfed1a05a67ae7fc8d62b7e9630c9
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79213
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch tries to standardize and simplify the Kconfig option layout
for Google boards with MediaTek SoCs and align them to the scheme used
with other Arm-based Google boards.
Change-Id: I40880e7609ba703d0053ad01da742871e54d4e7a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79063
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
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This patch unifies and simplifies the Kconfig selection model for the
Gru, Herobrine, Trogdor and Veyron boards according to the model
discussed in CB:78972.
Also add missing license headers to two Kconfig files while I'm here.
Change-Id: If679a05afd10869afba9c2a33b54862e102b5f40
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79022
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` config
option for select mainboards, as not all board variants may want to
enable this config due to underlying SoC dependencies.
Mainboards that attempt to enable early caching have exhibited soft
hangs while switching between pre-RAM and post-RAM phases. This patch
allows mainboards to choose to enable this option without enabling
it by default (which could cause boot hangs).
Furthermore, it reorganizes the configuration options under
BOARD_GOOGLE_BASEBOARD_REX in alphabetical order for better readability.
BUG=b:306677879
TEST=Enable SOC_INTEL_COMMON_BASECODE_RAMTOP for google/rex and
intel/mtlrvp.
Change-Id: If380c2ecbee4f6437c3d58bfb55be076a4902997
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Follow thermal validation, add ldo output select for speaker.
BUG=b:297298847
TEST=emerge-nissa and deploy to DUT to verify audio functionality.
Change-Id: Ie68f2b35f024b4dd066d831ae8fd5a662d407753
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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This partially reverts commit f493857c9bc1 ("mb/google/brya/var/*: Set
dGPU/LAN/WLAN device type to generic"). Setting the LAN device type to
generic broke programming the LAN MAC address, so set it back to pci.
TEST=build/boot google/brya (osiris), verify LAN MAC address programmed
correctly.
Change-Id: I4fb43b7212e67b5c38724baad572860bc45b558e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79150
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This mostly reverts commit 6c705e766f7f ("mb/google/puff/var/*: Set
LAN/WLAN device type to generic"). Setting the LAN device type to
generic broke programming the LAN MAC address, so set it back to pci.
TEST=build/boot google/puff (wyvern), verify LAN MAC address programmed
correctly.
Change-Id: I558ae6dc1366d5a8a22e0383d7d597d15159df03
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Check FW_CONFIG and disable gpios for HPS if HPS_ABSENT for skolas
and brya0 variants.
BUG=b:311740746
BRANCH=firmware-brya-14505.B
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas
to kernel and verify via "cbmem -c | grep HPS".
Change-Id: I8cbe4f40c41f1d06e8f511c3e88c05984566d441
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Check FW_CONFIG and disable gpios for LTE if LTE_ABSENT for skolas
and brya0 variants.
BUG=b:311459627
BRANCH=firmware-brya-14505.B
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas
to kernel and verify LTE gpios are disabled via "cbmem -c | grep LTE".
Change-Id: I3f3bc2b536babf71cc484cce02f96f47707f729c
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79122
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Skolas uses brya0 schematic, so override tree should be almost the same
for brya0 and skolas. This change sync's the skolas overridetree.cb
with brya0's overridetree.cb.
BUG=b:311722825
BRANCH=firmware-brya-14505.B
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to
kernel.
Change-Id: I14a2ed803a8ffb8614018af587c66034fb724b38
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
According to eDP panel datasheet[1], the eDP panel needs 0 <= x <=200ms
delay after VDD powering on. The MIPI panel[2] does not need this delay.
Move this delay to eDP path.
[1] NE135FBM-N41 V8.0 Product Spec_P2 20191025.pdf
[2] B5 TV110C9M-LL0 Product Specification Rev.P0
BRANCH=none
BUG=none
TEST=check FW screen
TEST=check timestamp
Before:
60:device initialization 696,422 (1)
15:starting LZMA decompress (ignore for x86) 696,587 (165)
16:finished LZMA decompress (ignore for x86) 696,675 (88)
17:starting LZ4 decompress (ignore for x86) 1,340,226 (643,551)
After:
60:device initialization 724,259 (1)
15:starting LZMA decompress (ignore for x86) 724,425 (166)
16:finished LZMA decompress (ignore for x86) 724,512 (87)
17:starting LZ4 decompress (ignore for x86) 1,168,176 (443,664)
Change-Id: I92bca5ec8269f4bad4dfab4ee193cdb5665de233
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79109
Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
Brox is using Ti50, so make sure that we set the right config for that.
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: If4a16448eebc028b2989c1de150b9e0f9067ee92
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Assigning the macros in gpio.h to the correct GPIOs. Also, fixing GPE
configurations so that they are mapped to the proper wake sources
(GPP_B, D, E groups).
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I6320cd98e560e514e63c52e173cb7923cfd1cdee
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I25b7adccf60abe515d129f8d00383165eccf6431
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79028
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I30a15277527a1e423691ff55ff11cc2136cefc90
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Building coreboot for the Qualcomm SoCs SC7180 and SC7280 requires to
include the Qualcomm blobs, which requires to accept their license.
However, for various reasons it makes sense to build without blobs, e.g.
static analysis or just build-testing.
So in order to do that, run the steps integrating the Qualcomm blobs
into the coreboot binary only if USE_QC_BLOBS is enabled and also remove
guards which prevent building related mainboards when USE_QC_BLOBS is
not enabled.
Change-Id: I249ac477b8f10e7fa0848e967c23a3b3b9bbd27d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79026
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Configure I2S1 and I2C5 for ALC5650 to support beep sound in
depthcharge.
BRANCH=corsola
BUG=b:305828247
TEST=Verify devbeep in depthcharge console
Change-Id: Ibd098adb8d5568ad338bbfece0edfd0c38cbf854
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79064
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Morphius boards using pre-v3.6 schematics don't have a dedicated GPIO
for touchscreen power/enable, and so fail with runtime detection
enabled. Since it only has one touchscreen option, and no SKUs lack a
touchscreen, we can safely assume it is present in all cases.
TEST=build/boot morphius w/4k screen, verify touchscreen enabled in
cbmem and functional in Linux and Windows.
Change-Id: I13e07e14b5a18fa1dd3b18950cf46e9d7821eedc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Appears to not be used under Windows, Linux, or ChromeOS, and causes
high CPU usage at idle under Windows.
BUG=none
TEST=build/boot Win11, Linux on google/frostflow, verify camera shutter
function unchanged, CPU usage under Windows idles where expected.
Change-Id: I8a6ea3b886766bdb055b40949c75bec0264eecc5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
According to proto schematics, the SD card is removed.
BUG=b:308968270
TEST=emerge-geralt coreboot
BRANCH=None
Change-Id: Id4e021e7896d093560f39c40573ac616d76438c2
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
These backlight related functions can be reused in other variants, move
them out to the panel.c. Also the panel_geralt.c should be used for
Geralt, enable it on Geralt board only.
BUG=b:308968270
TEST=emerge-geralt coreboot
BRANCH=None
Change-Id: I5d4035d5f480551c428c450826e23bf77f2fe08a
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78955
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
|
|
Create the variant Ciri and enable MAX98390 AMP for it. The panel
related support will be added in the follow up CLs.
BUG=b:308968270
TEST=emerge-geralt coreboot
BRANCH=None
Change-Id: I7bbe9ed5e722a70bab1c799a61ce38d2ad58ab25
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78954
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Update power limit values based on the suggestion of the thermal
team for RPL CPU.
The PL1 value (28W) suggested by the thermal team which is different from the reference document 686872 (PL1=15W).
BUG=b:310834985
TEST=built and booted into OS.
Change-Id: Ia2540ecd1fc453701b9160c97d82ba50b88ee848
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79059
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add support for the new memory CXMT CXDB4CBAM-ML-A.
BUG=b:304932936
BRANCH=firmware-dedede-13606.B
TEST=Run command "go run \
./util/spd_tools/src/part_id_gen/part_id_gen.go \
JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \
src/mainboard/google/dedede/variants/pirika/memory/\
mem_parts_used.txt"
And confirm the mainboard boot normally with CXMT
CXDB4CBAM-ML-A memory.
Change-Id: Iff2ed16bcbc9b0755e60a284246aa928625fa26a
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78892
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
All of these signals have net names, but are actually unstuffed, so we
have to set them to NC.
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I27d8b7cd02aefb49a2dc031a30eb0d1e8aa9faa9
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.
Change-Id: I866250602701e7e83a695d346f4b404b1bbae6d5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.
Change-Id: I4f2c4f4a576ea2fd2ccb7a7e6b52cf258bac5f84
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79043
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree.
Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping.
Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
The symbol VBT_DATA_SIZE_KB was removed in commit 8bde652241 -
"drivers/intel/gma/opregion: Use CBFS cache to load VBT" CB:77886,
however that patch only removed the Kconfig option from the Intel
chipsets, leaving it unused in the mainboards.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia29d8d6ec17b172e662ff591849f1668d65f1ff9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78967
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Add variant of LTE and WFC support on gothrax board.
We base decisions on the values within the firmware configuration
CBI field.
In fw_config settings, if the board move LTE and WFC modules,
the hardware GPP_A8/GPP_E13/GPP_F12/GPP_H19/GPP_H23/GPP_R6/GPP_R7
pins need to be deasserted.
BUG=b:303526071
TEST=emerge-nissa coreboot & \
Check against schematic.
Whether it works as expected under different SKUs.
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: Ia8041bdc599509911bde95d6294314036e75b227
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78916
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
There is no enumerate_buses() today and also no trace of it in our
repository. Also, in current terms, mainboard_enable() is called
as the very first thing in our enumeration so the comment seems
misleading.
Change-Id: Iae620f83c8166c1cfc8b9fb9ef4a7025987bf1be
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
Update DFP port setting for retimer power GPIO
BUG=b:302428013
BRANCH=none
TEST=Retimer enumaration in NDA works.
Change-Id: Idc1a728ec4cbb66e776c2700025db41d85801c60
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
That select is duplicate to the ones in the Kconfig file, and it
shouldn't be there anyway. Remove it.
Change-Id: I1a940f034a69f72280d15ab9a0c9d83f8111910e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78973
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Later GSCs don't need a EC_IN_RW GPIO anymore, so removing the use of
this for get_ec_is_trusted().
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I29f94969e9f2c1f239d9f9655f39b8410296f695
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Having a separate romstage is only desirable:
- with advanced setups like vboot or normal/fallback
- boot medium is slow at startup (some ARM SOCs)
- bootblock is limited in size (Intel APL 32K)
When this is not the case there is no need for the extra complexity
that romstage brings. Including the romstage sources inside the
bootblock substantially reduces the total code footprint. Often the
resulting code is 10-20k smaller.
This is controlled via a Kconfig option.
TESTED: works on qemu x86, arm and aarch64 with and without VBOOT.
Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55068
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Add FW_CONFIG probe to separate WFC settings.
WFC_PRESENT/WFC_ABSENT
Add FW_CONFIG probe for new DB_USB sku.
DB_C_A_LTE/DB_A
BUG=b:303526071
TEST=emerge-nissa coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I93e0bce4b8be37e259efe0d7b0185035b3e88785
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78963
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable DDI on ports 1 to 4 for Type-C DisplayPort.
BUG=b:305793886
TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I3acaff4a9306f2d058ce9542e8956ee0acba94cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78498
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
As TOUCHSCREEN_I2C_SPI will be used for two different configurations,
splitting it to TOUCHSCREEN_GSPI and TOUCHSCREEN_THC, and re-order
the FW_CONFIG bits by moving VPU to different bit position.
BUG=b:307774932
TEST=build and boot rex
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: Ied4d732ef7993e95edbb7eb281842b9392e72820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Some GPIOs (like WP and GSC) need to be configured in bootblock.
Making sure that they get configured earlier for this.
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I8dd4853bc05b954f47d858d87ea2aed48e4b8074
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78943
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are some inaccuracies in arbitrage. This is the first pass at
correcting the incorrectly generated configs. I also tried to update
the "No heuristic was found useful" comment generated by arbitrage
into something more useful (ie: the appropriate NFs).
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I836565e09a3e0b25746b3e2f9ed6610eaacf7e97
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78942
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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