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2022-11-16mb/google/brya/var/agah: Add Power Limits for RPL SKUTarun Tuli
Add power limits for the RPL SKUs of Agah. BUG=b:258432915 TEST=build and boot ADL based Agah. RPL based testing when hardware becomes available. Change-Id: Ie97a9d14f1ee6f65225b7d26e25ff3d902fddc7f Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69419 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-11-16mb/google/brya/variants/volmar: Update ELAN touchscreen timingRen Kuo
ELAN updated the datasheet, the HID/I2C protocol's T3 delay time is 150ms now. Modify the volmar's delay time to follow the requiremnet. BUG=b:257073343 TEST=Build firmware and measure the T3 timing of resume and boot up on volmar DUT. Run Suspend/Resume with UI test and got pass. Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I40a30ed567cd676d0a9373527d93fe51f89d39e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69559 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-16mb/google/skyrim/var/winterhold: Update DPTC setting for SMTEricKY Cheng
Follow Dynamic Thermal Table Switching proposal to initialize thermal table config E as default table for SMT. Since the dynamic thermal table switching mechanism is still under cooking, after discussing with thermal team, suggest adopting config E(limit Soc not reach to max power) as default thermal config to avoid any thermal-related issue during phase build. Once the dynamic thermal table switching mechanism is finished, will change the default value to config A. BUG=b:232946420, b:258572474 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I4aa90304e1e7bda7d580de2582129191e9eb0e76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-11-16mb/google/skyrim: Create crystaldrift variantChao Gui
Create the crystaldrift variant of the skyrim reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:240970782 BRANCH=None TEST=util/abuild/abuild -p none -t google/skyrim -x -a make sure the build includes GOOGLE_CRYSTALDRIFT Signed-off-by: Chao Gui <chaogui@google.com> Change-Id: Ibb3ebaa7e4af1a03173b93b8c4fbd342f7cd7100 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-16mb/google/zork: Use detect vs probed flag for touchscreensMatt DeVillier
Now that coreboot performs the necessary power sequencing, switch from using the 'probed' flag to 'detect' for all I2C touchscreens. This alleviates ChromeOS from having to probe to see which touchscreen model is actually present, prevents breaking ACPI spec by generating device entries with status 'enabled and present' which aren't actually present, and improves compatibility with upstream Linux and Windows. BUG=b:121309055 TEST=build/boot ChromeOS and Linux on zork, ensure touchscreen is functional, and ACPI device entry generated for correct touchscreen model. This mirrors the changes made for skyrim in commit 22683fab (mb/google/skyrim: Use detect vs probed flag for touchscreens) Change-Id: Idfe899bd535507c56f0825c6538246441b3b0827 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69457 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16mb/google/zork: Implement touchscreen power sequencingMatt DeVillier
As all variants have a touchscreen option, in baseboard tables set the enable GPIO high and hold in reset during romstage, then release reset in ramstage. This will allow the touchscreen to make use of the runtime I2C detect feature (enabled in a subsequent commit) so that an ACPI device entry is created only for the touchscreen actually present. This mirrors the change to skyrim in commit f90ff456 (mb/google/skyrim: Implement touchscreen power sequencing) Change-Id: Ifdd75cd96e7b6880085a3f47214b92948a56aa2e Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69456 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16mb/google/nissa/var/craask: Correct G2 touchscreen HIDTyler Wang
Correct G2 touchscreen HID to GT75CH02. BUG=b:235919755 Test=Dump the SSDT on craask and check the HID had been modified. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Iad32e8cbd534dc43fca24d881092f3477ca1a4e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69600 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16mg/google/zork: Add functionality to set GPIOs in romstageMatt DeVillier
Add (empty) baseboard GPIO tables, getter functions, and call to gpio_configure_pads() in romstage, in preparation for adding touchscreen GPIO configuration/power sequencing. Change-Id: If0f626dbc7e601c2f49759e49a0baf027bf25f96 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69482 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-16mb/google/kahlee: Implement touchscreen power sequencingMatt DeVillier
As all variants have a touchscreen option, in baseboard table set the enable GPIO high and hold in reset during romstage, then release reset in ramstage. This will allow the touchscreen to make use of the runtime I2C detect feature (enabled in a subsequent commit) so that an ACPI device entry is created only for the touchscreen actually present. This mirrors similar changes made for skyrim, guybrush, and zork. TEST=tested with rest of patch train Change-Id: Id235815904dfc093549a1ed529e19974010977c7 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69547 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16mb/google/kahlee: Use detect vs probed flag for touchscreensMatt DeVillier
Now that coreboot performs the necessary power sequencing, switch from using the 'probed' flag to 'detect' for all I2C touchscreens. This alleviates ChromeOS from having to probe to see which touchscreen model is actually present, prevents breaking ACPI spec by generating device entries with status 'enabled and present' which aren't actually present, and improves compatibility with upstream Linux and Windows. BUG=b:121309055 TEST=build/boot ChromeOS and Linux on barla/liara, ensure touchscreen is functional, and ACPI device entry generated for correct touchscreen model. Change-Id: I142a6cdb6e8cef51fd925d34362a19a8736982a5 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69548 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16mb/google/kahlee: rename baseboard GPIO table getter for clarityMatt DeVillier
Rename variant_romstage_gpio_table() to baseboard_romstage_gpio_table() since the GPIO table comes from the baseboard (and is not overridden by any variant). Drop the __weak qualifier as this function is not overridden. This mirrors similar changes made for skyrim, guybrush, and zork. Change-Id: I772bd2d74fd6778ffaa1e0809cc53f8d43b153f3 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69546 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16mb/google/kahlee: Disable touchscreen GPIO export in CRSMatt DeVillier
Disable GPIO export in ACPI _CRS for touchscreens which set the register "have_power_resource." This eliminates the error: [ERROR] I2C: <bus:addr>: Exposing GPIOs in Power Resource and _CRS TEST=build/boot barla/liara, verify touchscreen functional, no error in cbmem log. Change-Id: Ifa8248755f346df37faf7a3182651bf190b0c33d Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69549 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16mb/google/brya/var/agah: Set GPP_H13 to reset on PLTRSTTarun Tuli
GPP_H13 should be reset when going to S5. Update it to do so on PLTRST BUG=b:240617195 TEST=Measured on Agah that PP3300_SD_X goes off in S5. Change-Id: I959f92f2c486e0ca5cb4269b271c163b4c4925d4 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69340 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16mb/google/brya/var/gaelin: Configure DRIVER_TPM_I2C_BUSRaymond Chung
Add TPM I2C bus for gaelin in Kconfig. BUG=b:249000573 BRANCH=firmware-brya-14505.B TEST=Build "emerge-brask coreboot" and can boot to OS. Change-Id: Idaac11111a9ba7df0929267567e4730b2811f5f0 Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68886 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2022-11-15mb/google/nissa: Add SD_BOOT fw_configReka Norman
Some nissa devices want to disable boot from SD card. Since nissa has a single shared depthcharge target, add a program-wide fw_config to allow disabling it. BUG=b:253003881 TEST=With depthcharge change, set SD_BOOT_DISABLE on nivviks and check SD card is not initialised in depthcharge. Change-Id: I1a3a533e4e74e48d9ce4a9678b812cb62ce2066b Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69541 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15mb/google/nissa: Remove SI_ME subregionsReka Norman
The SI_ME subregions were added to support using the CSE stitching tools (cse_serger). Use of the stitching tools has been reverted and probably won't be re-enabled soon, so the subregions are not currently used by anything. They also don't match the actual region sizes chosen by the FIT tool, so remove them to avoid confusion. The other option would be to manually keep them in sync with the sizes chosen by the FIT tool, but this would be extra manual effort without much benefit. BUG=None TEST=Build and boot on nivviks Change-Id: I993e07a060445ab8de1b0e40a023e8248867c53c Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69540 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-11-15soc/amd: commonize generation of the PIC/APIC mapping tablesFelix Held
Now that we have a common init_tables in all mainboards using AMD SoCs, both the population of the fch_pic_routing and fch_apic_routing arrays and the definition of those arrays can be moved to the common AMD SoC code to not have the code duplicated in all mainboards. BUG=b:182782749 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I8c65eca258272f0ef7dec3ece6236f5d00954c66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68853 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15mb/google/geralt: Enable RTC for eventlog timestampsLiju-Clr Chen
Without RTC, the timestamps in the eventlog are currently all '2000-00-00 00:00:00'. Enable RTC to get the correct timestamps. localhost ~ # head /var/log/eventlog.txt 0 | 2022-10-15 22:59:38 | Log area cleared | 4088 1 | 2022-10-15 22:59:38 | Memory Cache Update | Normal | Success 2 | 2022-10-15 22:59:45 | System boot | 0 3 | 2022-10-15 22:59:46 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown localhost ~ # localhost ~ # date Sun Oct 16 01:42:59 PDT 2022 localhost ~ # BUG=b:233720142 TEST=check the timestamp field in /var/log/eventlog.txt Change-Id: Iddad102dc8d60de01a691d330deb8247e99c616a Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69432 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15mb/google/brya/var/marasov: Add memory config for marasovFrank Chu
Configure the rcomp, dqs and dq tables based on the schematic. BUG=b:254365935 BRANCH=None TEST=Built successfully Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I8c9541006828deae83e2ae4a860f40d7433662d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69149 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-15mb/google/kahlee/mainboard: rewrite IRQ mapping handlingFelix Held
Rewrite the Kahlee IRQ mapping handling to be in line with the newer AMD SoCs to allow making the largest part of the corresponding code common for all AMD SoCs in the coreboot tree. The PIC-mode IRQ numbers for both PIRQ_ASF and PIRQ_SDIO were 0 in the data tables which is the PIT IRQ which looks very wrong to me, so it was changed to PIRQ_NC. Since the ASF and likely also the SDIO controller are unused, this shouldn't change runtime behavior. The data tables also had non 0 and non 0x1f entries in the following locations the internal BKDG #55072 revision 3.04 describes as unused: 0x31, 0x33, 0x35-0x37, 0x40, 0x50-0x53. The entry at 0x32 is also non 0 and non 0x1f and the description in the BKDG says that it controls the IRQ mapping of another internal PCI device, but that PCI device doesn't exist in the SoC. TEST=No obvious IRQ-related breakage on google/liara Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Change-Id: I9b3bfca33d88ef3989b63f4fe6c301e0e485b7e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68851 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15mb/google/brya/var/marasov: use i2c1 for TPM for marasovFrank Chu
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the marasov variant. BUG=b:254365935 TEST=FW_NAME=marasov emerge-brya coreboot Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I4d155fb35424d1ec12e825ca0aab233bd3cd607e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69376 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-15mb/google: Fix log messagesElyes Haouas
Change 'printk(BIOS_DEBUG, "ERROR:' to printk(BIOS_ERR, "'. Change-Id: Id31c25f5b8686f951ab4f331682b82ff327d5e78 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-15mb/google/nissa/var/craask: Remove RFIM settings for CraaskTyler Wang
Request by RF team, remove RFIM related settings to disable it. BUG=b:239657092 Test=RF team test on DUT and check it's disable Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I1eb4d93c2821cb067628dc1228c6c522d292c739 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-14mb/google/nissa/var/pujjo: Modify touch screen hid to ELAN901CLeo Chou
Modify touch screen hid for Pujjo board. BUG=b:258586760 TEST=Use the value to boot on Pujjo successfully. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ia3b374de8cba2125c478814a1890a4b6831715b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-13mb/google/zork: rename baseboard GPIO table getter for clarityMatt DeVillier
Rename variant_pcie_gpio_table() to baseboard_pcie_gpio_table(), since the GPIO table comes from the baseboard (and is not overridden by any variant). Drop the __weak qualifier as this function is not overridden. This is similar to the change made for skyrim in CB:67809 Change-Id: Idd8ea3446ab7940b21265a3ed8080ba4029c4ff7 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69453 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12mb/google/brya/var/agah: Add RPL Support to AgahTarun Tuli
Enable RPL support for Agah. BUG=b:258432915 TEST=build and boot ADL based Agah. RPL based testing when hardware becomes available. Change-Id: I5437dbf9e7812367a280d1ed659f286fb9b62a68 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69398 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12mb/google/rex: Add Write Protect GPIO to cros_gpiosIvy Jian
This will enable crossystem to access WP GPIO BUG=b:258048687 TEST= wpsw_cur in crossystem reads the correct gpio Change-Id: I67f4a57025064dbf8c691255b0abae9d3fa0dbd3 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69468 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12mb/google/brya/variants/volmar: Disable the unused FP padsRen Kuo
Disable the unused fingerprinter(FP) gpio for zavala by fw_config FPMCU_MASK field. BUG=b:250807253 TEST=build firmware and veriify the FP function on volmar DUT Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I0af1b7c3e4829ecab98525ead4f078c3eb6485d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69465 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12mb/google/brya/var/marasov: Enable ISH driver and firmware nameSubrata Banik
BUG=b:234776154 TEST=Build and boot Marasov UFS, copy ISH firmware to host file system /lib/firmware/intel/adl_ish_lite.bin check "dmesg |grep ish", it should show: ish-loader: ISH firmware intel/adl_ish_lite.bin loaded Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic53a3cbdf83825adc27f37877a14f4f405d4a5ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/69377 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-11-12mb/google/brya/var/marasov: Select ISH driverSubrata Banik
This patch ensures that Marasov selects the ISH driver for devices with UFS enabled. BUG=b:256566011 TEST=Able to build Marasov. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I97a0aa3bc6976be32ddbf1fc6b37c16bb62a62e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69379 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-11-12ec/google/chromeec: Deprecate dev_index from google_chromeec_rebootCaveh Jalali
This removes the dev_index argument from the google_chromeec_reboot API. It's always set to 0, so don't bother passing it. BUG=b:258126464 BRANCH=none TEST=none Change-Id: Iadc3d7c6c1e048e4b1ab8f8cec3cb8eb8db38e6a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69373 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetreeArthur Heymans
Change-Id: I77a333827552741453d8b575f2a8009b3e1bf8f1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12mb/google/brya/var/gladios: Add GL9750 SD card reader supportKevin Chiu
BUG=b:239513596 TEST=emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I7411e10348c36786000c6918b9b154b7329f3cd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-12mb/google/brya/var/gladios: Include GL9763E driver for eMMC supportKevin Chiu
Support GL9763E as a eMMC boot disk. BUG=b:239513596 TEST=emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I2b29309615df381f1e24f29fc048c6f9bf216b7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69425 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11mb/google/brya/var/gladios: use i2c1 for TPM supportKevin Chiu
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the gladios variant. BUG=b:239513596 TEST=emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Id6f2bf2a79df883bcb70171051cec4c577ca3bc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69424 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-10mb/google/skyrim: Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSPJan Dabros
Skyrim platforms have I2C3 controller which is shared between PSP and X86. In order to enable cooperation, PSP acts as an arbitrator. Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP, so that proper driver is binded on the OS side. BUG=b:241878652 BRANCH=none TEST=Build kernel and firmware. Run on skyrim and verify TPM functionality. Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I2a3de8cb2b9241e2d81e02df49f317ac0408d5bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/67675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-11-10mb/google/herobrine: Update comment of modem status infoVenkat Thogaru
Updated comment as per guidelines. BUG=b:232302324 TEST=none Signed-off-by: Venkat Thogaru <quic_thogaru@quicinc.com> Change-Id: I6a925477a926e7e9d54e42d662768536318ec8e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-11-10mb/google/brya/var/marasov: use RPL FSP headersFrank Chu
To support an RPL SKU on marasov, marasov must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for marasov so that it will use the RPL FSP headers for marasov. BUG=b:254365935 BRANCH=None TEST=FW_NAME=marasov emerge-brya intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I7874420c0fb51b9cc616cd979ffc9349c381602e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69367 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-10mb/google/brya/var/marasov: Generate SPD ID for supported memory partsFrank Chu
Add supported memory parts in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 1 (0001) MT62F1G32D4DR-031 WT:B 4 (0100) H9JCNNNCP3MLYR-N6E 5 (0101) BUG=b:254365935 BRANCH=None TEST=run part_id_gen to generate SPD id Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ifa0637b47d0017cdb9e26ed32328f4405c0df3f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69311 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-10mb/google/brya/var/marasov: Update devicetree setting for marasovFrank Chu
update devicetree setting per the schematic BUG=b:254365935 BRANCH=None TEST=Built successfully Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ifa4cb18b8e1a7b162f505ff12612ef808fb7061a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69364 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10mb/google/nissa/var/craask: Disable stylus GPIO pins based on fw_configTyler Wang
BUG=b:257879909 Test:Boot to OS on craask and check stylus GPIO pins Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I7e3a2583187c8a8e2616a5272b5a7a61debe982b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69138 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10mb/google/nissa/var/craask: Modify DPTF related settingsTyler Wang
Request by thermal team, make below changes: 1) tdp_pl2_override: 12 --> 25 2) pl1.min_power: 3000 --> 5500 3) pl1.time_window_max: 32 * MSECS_PER_SEC --> 28 * MSECS_PER_SEC 4) pl2.min_power: 12000 --> 25000 5) pl2.max_power: 12000 --> 25000 6) pl2.time_window_min: 28 * MSECS_PER_SEC --> 1 7) pl2.time_window_max: 32 * MSECS_PER_SEC --> 1 BUG=b:239495499 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I88c8c4e6798ec5bc2930dd713e8c8b2c543cfaf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68523 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
2022-11-10mb/google/nissa/var/pujjo: Update register parameters for SX9324 tunningVictor Ding
Update SX9324 related settings based on tunned values from the ODM. This patch supports both legacy and upstream Linux's SX9324 driver. BUG=b:242662878 TEST=i2cdump -y -f 13 0x28 (Verified register values on Pujjo) Signed-off-by: Victor Ding <victording@google.com> Change-Id: I34d8073ffe93e6939f8da0cd7efb8667c0e9ac37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69366 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09soc/amd/picasso/acpi: include pci_int_defs.asl from soc.aslFelix Held
Instead of including pci_int_defs.asl in each board's DSDT, include it in the common soc.asl. This moves the PRQM OperationRegion and the PRQI IndexField defined in pci_int_defs.asl into the \_SB scope, but those are defined inside the \_SB scope both in the Picasso reference code and for the AMD SoCs from Cezanne on. TEST=Both Linux and Windows still boot and don't show ACPI errors on Mandolin after moving this inside the \_SB scope Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2022-11-09soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.aslFelix Held
This aligns Picasso more with the newer AMD SoCs and also makes it a bit clearer what this file does. Also remove the unneeded tabs at the beginning of each line. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie6e5ee815e4346004bc864a6111a255dc689eae8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2022-11-09nb/intel/haswell: Hook up PCI domain and CPU cluster ops to devicetreeArthur Heymans
Change-Id: I955274bc6bda587201f130762c0735c36f5501d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69289 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09mb/google/nissa/var/craask: Add wifi sar tableTyler Wang
Add wifi sar table for craask/craaskbowl. Use fw_config to separate different project settings. BUG=b:247652032,b:251287099,b:251287101 Test=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I5c92f0ab53ece12a97068f09241e5298909116aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/68660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-09soc/amd/common/block/spi: Mainboard to override SPI Read ModeKarthikeyan Ramasubramanian
On certain mainboards due to hardware design limitations, certain SPI Read Modes eg. (Dual I/O 1-2-2) cannot be supported. Add ability to override SPI read modes in boards which do not have hardware limitations. Currently there is an API to override SPI fast speeds. Update this API for mainboards to override SPI read mode as well. BUG=b:225213679 TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of ~25 ms with 100 MHz SPI speeds. Before: 11:start of bootblock 688,046 14:finished loading romstage 30,865 16:FSP-M finished LZMA decompress (ignore for x86) 91,049 Total Time: 1,972,625 After: 11:start of bootblock 667,642 14:finished loading romstage 29,798 16:FSP-M finished LZMA decompress (ignore for x86) 87,743 Total Time: 1,943,924 Change-Id: I160b56f6201a798ce59e977ca40301e23ab63805 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-11-09mb/google/nissa/var/xivu: Add Hynix new memory supportIan Feng
Add new ram_id:0 (0000) for memory part H9JCNNNCP3MLYR-N6E. DRAM Part Name ID to assign H9JCNNNCP3MLYR-N6E 0 (0000) BUG=b:257867226 TEST=Use part_id_gen to generate related settings and emerge-nissa coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: If663afbcd2e0457636f4a1c7475f1e3e40f0dd96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-09drivers/i2c/sx9324: Add support for Linux's SX9324 driverVictor Ding
SX9324 driver is updated per Linux's documentation found at https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml Supporting logic for the deprecated SX932x driver is hence guarded by DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER This patch by itself does not introduce functional changes to any board. The legacy SX932x Linux driver never reached upstream Linux and is only available in ChromeOS kernel fork of 4.4 and 5.4. Linux later accepted a different implementation named SX9324 and has been available since 5.4. Ideally all variants should adopt the new driver; however, during the transition phase, coreboot must support both drivers. It is better to have a single firmware build that can work with both Linux kernel drivers by specifying both sets of properties. Legacy driver support should be deleted once all variants finish migration. BUG=b:242662878 TEST=Dump ACPI SSDT then verify _DSD entries related to the legacy SX932x driver are identical w/ and w/o this patch (Tested on Craask and Nivviks) Change-Id: I42cd6841c3a270c242ed2e739db245e858eadb3b Signed-off-by: Victor Ding <victording@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69192 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-09mb/google/rex: Add fingerprint SPIEran Mitrani
Add Fingerprint SPI, and power-off FPMCU during romstage. For reference see CL:66915 for a similar change to Brya's power sequence SHA: 2b523ce6316e5c5ec86fe812d739fe48ca81d83d ("Invoke power cycle of FPMCU on startup") TEST=Tested on Rex - setup and logged in using fingerprint Change-Id: I4e6be24e72a8232ae2c958a01cf8ea9a272d7365 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66992 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-08vboot: Add VBOOT_CBFS_INTEGRATION supportJakub Czapiga
This patch introduces support signing and verification of firmware slots using CBFS metadata hash verification method for faster initial verification. To have complete verification, CBFS_VERIFICATION should also be enabled, as metadata hash covers only files metadata, not their contents. This patch also adapts mainboards and SoCs to new vboot reset requirements. TEST=Google Volteer/Voxel boots with VBOOT_CBFS_INTEGRATION enabled Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I40ae01c477c4e4f7a1c90e4026a8a868ae64b5ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/66909 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-08mb/google/brask: Disable PCH USB2 phy power gating for braskRicky Chang
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for moli board. Please refer Intel doc#723158 for more information. BUG=b:257415959 TEST=Verify the build for brask board Change-Id: I518e90e9032e8f2186300b6b907cc9d84a1682e4 Signed-off-by: Ricky Chang <rickytlchang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-08mb/google/nissa/var/craask: Add ambient thermal sensor settingsTyler Wang
BUG=b:239495499 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I026a8b3e1a27bedc3e0082e15e80a74a2f8adfda Reviewed-on: https://review.coreboot.org/c/coreboot/+/69197 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
2022-11-08mb/google/brya/var/kano: Add mipi hi556 camera supportDavid Wu
This patch supports multiple camera modules based on FW_CONFIG. BUG=b:251235140 TEST=Test the changes with ov2740/hi556 camera. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I34dbf67634ecd364c40c6e934217af3d8efe1689 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jim Lai <jim.lai@intel.com> Reviewed-by: Ricardo Ribalda <ribalda@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-11-08mb/google/brya/var/kinox: Disable PCH USB2 phy power gatingDtrain Hsu
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for kinox board. Please refer Intel doc#723158 for more information. BUG=b:257373738 TEST=Verify the build for kinox board Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ifcf4f89ea4c61ec4f9a31edba069d2111ca06010 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-08mb/google/brya/var/lisbon: Disable thunderbolt portsKevin Chiu
Lisbon doesn't support thunderbolt. BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Iac44315d000c3c0c572efb00e877d039e0308455 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68916 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-07soc/qualcomm/sc7280: Move AOP load and reset handle to RomstageSudheer Kumar Amrabadi
As AOP takes 500 msec delay to get up, moving aop load and reset to romstage improves the performance. BUG=b:218406702 TEST=reboot from AP console (on CRD3) prior to fix (from cbmem dump): 1000:depthcharge start 1,139,809 (152,679) after fix (from cbmem dump): 1000:depthcharge start 1,041,109 (46,353) Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org> Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-11-07mb/google/guybrush: Use detect vs probed flag for touchscreensMatt DeVillier
Now that coreboot performs the necessary power sequencing, switch from using the 'probed' flag to 'detect' for all I2C touchscreens. This alleviates ChromeOS from having to probe to see which touchscreen model is actually present, prevents breaking ACPI spec by generating device entries with status 'enabled and present' which aren't actually present, and improves compatibility with upstream Linux and Windows. BUG=b:121309055 TEST=build/boot ChromeOS and Linux on guybrush, ensure touchscreen is functional, and ACPI device entry generated for correct touchscreen model. This mirrors the changes made for skyrim in CB:67779. Change-Id: Ib6a76b969d3a245eccde5352231eb7e36736f2e0 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-07mb/google/guybrush: Implement touchscreen power sequencingMatt DeVillier
As all variants have a touchscreen option, in baseboard table set the enable GPIO high and hold in reset during romstage, then release reset in ramstage. This will allow the touchscreen to make use of the runtime I2C detect feature (enabled in a subsequent commit) so that an ACPI device entry is created only for the touchscreen actually present. Variants/SKUs which do not have a touchscreen (if any) can use the romstage/ramstage GPIO override tables to set the associated enable/ reset GPIOs to NC. This mirrors the change to skyrim in CB:67778. BUG=b:121309055 TEST=build/boot guybrush with rest of patch series Change-Id: I9b3356b8b3a0e68a307838a4b18775d25b32e548 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-07mb/google/brya : Set EPP value for Vell boardSridhar Siricilla
The patch sets the EPP to 50% (0x80) for Vell. With EPP at 50%, the Vell system demonstrated better power improvement without sacrificing the performance. PLT Results(Perf) with EPP@40% and EPP@50%: EPP@40%: Device1-656 mins, Device2-664 mins. EPP@50%: Device1-678 mins, Device2-677 mins. In short, with EPP@50%, PLT KPI ran for more than 13 to 22mins compared to EPP@40%. Branch=firmware-brya-14505.B BUG=b:215526166 TEST=Verified code build for Vell board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I41b15b84025d25cf59dac2d85826a3de9d725bae Reviewed-on: https://review.coreboot.org/c/coreboot/+/68900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-07mb/google: Probe p-sensor only for selected variantsVictor Ding
Only a subset of variants has proximity sensors. This patch by itself does not introduce functional changes to any board. It is mainly to ease migrating SX9324 from the legacy driver to the linux one - allowing gradual migration variant by variant. BUG=b:242662878 TEST=Dump ACPI SSDT then verify they are identical w/ and w/o this patch Change-Id: Ic00e0d9eafcef2c9eaf32571fecf6190777cec36 Signed-off-by: Victor Ding <victording@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69191 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07mb/google/brya: Create marasov variantFrank Chu
Create the marasov variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:254365935 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_MARASOV Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ibe2dc442480f6a73877b40625e228cdb2038aa4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69052 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Kyle Lin <kylelinck@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-07mb/google/brya/variants/volmar: Add firmware config field for FPMCURen Kuo
The fingerprint(FP) feature is only for volmar,and it's not for zavala. Add FPMCU_MASK field in fw_config to disable the FP function for zavala, and reserve FP function for shipped volmar. Define the value as following: field FPMCU_MASK 10 option FPMCU_ENABLED 0 option FPMCU_DISABLED 1 end BUG=b:250807253 TEST=build firmware and verify the fp function in volmar DUT. write `disable=1` and 'enable=0' in FPCMU_MASK field. check the fp function and run `ectool --name cros_fp version` It works as expected. Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I867771904811459697056662d5e29c545a1a9474 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68917 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-05mb/google/guybrush: Rename pcie_gpio_table to romstage_gpio_tableMatt DeVillier
Rename so table more indicative of when GPIOs are set, and so it can be used for more than just setting PCIe GPIOs. Will be used to set touchscreen GPIOs as part of power sequencing in a subsequent commit. Rename all variant tables and getter functions to match. This mirrors the changes made for skyrim in CB:67810 Change-Id: I72e7febfb532262be7e4c14bf136e0d69c91301e Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-05mb/google/guybrush: rename baseboard GPIO table getter for clarityMatt DeVillier
Rename variant_pcie_gpio_table() to baseboard_pcie_gpio_table(), since the GPIO table comes from the baseboard and is overridden by a separate table from the variant. Drop the __weak qualifier as this function is not overridden. This is similar to the change made for skyrim in CB:67809 Change-Id: I14c79fad04f18d874ce6ff7e572bb237445db8b1 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-05mb/google/brask: Disable PCH USB2 phy power gating for moliCasper Chang
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for moli board. Please refer Intel doc#723158 for more information. BUG=b:257373742 TEST=Verify the build for moli board Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I457d410501be996f0f29ec622e1829f1581c4970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69193 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
2022-11-04mb/google/reef: Fix guarding of reading SKU from VPDMatt DeVillier
VPD read depends on CONFIG(VPD), not CONFIG(CHROMEOS). TEST=build/boot snappy, verify SKU set properly in SMBIOS Change-Id: I8aa57f793bd04dbe31f3b49bbff23e05c96592a6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04mb/google/rex: Enable RFIM for CNVizhaojohn
This patch enables the radio frequency interference mitigation for Rex. BUG=b:248391777 TEST=Booted to OS on Rex board. Verified RFIM DSM is presented to kernel through ACPI SSDT. Change-Id: I22f9861452c2c222dd7a33bfeb02c63b026bf2f7 Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-04mb/google/brask/var/kuldax: Update PsysPL2 and PsysPmaxDavid Wu
Update PsysPL2 and PsysPmax. BUG=b:253542746 TEST=Make sure PsysPL2 and PsysPamx values set properly (through debug output) Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I0ffad751e8a99b282a5d05563a60745ee09e892c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-04mb/google/rex: Fix fw_config probe for UFC and WFCKapil Porwal
Fix fw_config probe for UFC and WFC. BUG=b:255971791 TEST=Build Google Rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I5103e7da04004414d96f42057c105cf9fbf51b25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-04mb/google/brya/var/lisbon: update USB topology in devicetreeKevin Chiu
update USB topology per the schematic design BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I2976028d3efa20e25deedb34ffb8b3bab43b5f5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-04mainboard: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: Iccb7f28a2c913ae0983bf224a03610d7fdd13c68 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03mb/google/brya/gaelin: Configure GPIO settingsRaymond Chung
Override GPIO pad configuration based on the latest gaelin schematic. BUG=b:249000573 BRANCH=firmware-brya-14505.B TEST=FW_NAME=emerge-brask coreboot Change-Id: I649ac5131393008787cbb403fc64b914de23312b Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-03mb/google/skyrim: Disable SD ASPMEricKY Cheng
Disable ASPM on SD until b/245550573 is root-caused/fixed. Logical_lane 1 on winterhold is EMMC device. Disable ASPM for suspend issue. BUG=b:249914847, b:245550573 TEST=emerge-skyrim coreboot chromeos-bootimage and test on whiterun proto emmc sku with suspend_stress_test -c 10 Change-Id: If080cdb517a3f22aa89c8053fb6bba9e931c6f76 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68940 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02mb/google/skyrim: Use detect vs probed flag for touchscreensMatt DeVillier
Now that coreboot performs the necessary power sequencing, switch from using the 'probed' flag to 'detect' for all I2C touchscreens. This alleviates ChromeOS from having to probe to see which touchscreen model is actually present, prevents breaking ACPI spec by generating device entries with status 'enabled and present' which aren't actually present, and improves compatibility with upstream Linux and Windows. BUG=b:121309055 TEST=build/boot ChromeOS and Linux on skyrim, ensure touchscreen is functional, and ACPI device entry generated for correct touchscreen model. Change-Id: Id9e3089decf0f94a1358929684ce248e52cbe41f Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-11-02mb/google/hatch/var/kohaku: ensure FPMCU is power cycled on resetTarun Tuli
Leakage from the SPI CS line onto the FPMCU VDD rail was preventing the FPMCU from fully shutting down on AP reset. Instead of simply turning off the power rail, now ensure the CS line is not driven high until late in coreboot. This ensures it is completely off for the requisite minimum of 200ms (now measured at approx 1100ms). BUG=b:245953688 TEST=Confirmed FPMCU is still functional on Kohaku. Confirmed FpRebootPowerCycle unit test now passes BRANCH=Hatch Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I1e7e32f61c3ac1b3154d42821cc1dd4c5d3de303 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68819 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02mb/google/hatch: Add variant finalize support for hatch devicesTarun Tuli
Provide a variant_finalize() method and call to be invoked from mainboard_ops.final BUG=b:245953688 TEST=Hatch and variants build BRANCH=Hatch Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I9253ed4be1b08d0c7f65526c9b26dbcd00ffccc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68821 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02mb/google/brya/var/lisbon: Enable SaGvKevin Chiu
Enable SaGv support for lisbon BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot pass RMT verification Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Ic7d3203bfe06973b023a38d1aa3d69cce5c3a60c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69013 Reviewed-by: Ricky Chang <rickytlchang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-02mb/google/brya/var/lisbon: Include driver for GL9763E for eMMC boot diskKevin Chiu
Support GL9763E as a eMMC boot disk BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Ibe579a913225b5241412bbb1b8ea995a5102a3bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/68888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-02mb/google/brya: enable PCIe RP12 for lisbon eMMC supportKevin Chiu
BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Ief8ca9cf845156ac761556d0eb49edb65894c001 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-02mb/google/corsola: Add new board 'voltorb'Mars Chen
Add a new kingler follower 'voltorb'. BUG=b:256737049 TEST=emerge-corsola coreboot Signed-off-by: Mars Chen <chenxiangrui@huaqin.corp-partner.google.com> Change-Id: Ic7175c38fcde76ab0360f62da161994ba2ee6a69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-02mb/google/brya/var/gladios: use RPL FSP headersKevin Chiu
To support an RPL SKU on gladios, gladios must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for gladios so that it will use the RPL FSP headers for gladios. BUG=b:239513596 BRANCH=None TEST=FW_NAME=gladios emerge-brask intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Ic30f7fe30eb0a3151cdf46fff609819056b2fbfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/68570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-02mb/google/skyrim: Select GOOGLE_SMBIOS_MAINBOARD_VERSIONAmanda Huang
Select GOOGLE_SMBIOS_MAINBOARD_VERSION allows querying board revision from the EC. BUG=b:256723358 TEST=1. emerge-skyrim coreboot chromeos-bootimage 2. flash the image to the device and check board rev by using command `dmidecode -t 1 | grep Version` Change-Id: I97295083dbca1c285ef7359d86abac7315c654c9 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69087 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-02mb/google/rex: Disable TBT PCIe rp1 and rp3 root portszhaojohn
Rex board only uses TBT PCIe root ports 0 and 2. This change disables rp1 and rp3 root ports. BUG=b:254207628 TEST=Booted to OS and verified rp1 and rp3 root ports were disabled. Change-Id: Ia5c1d657c0ad0482619d739f8949bc9168eac25b Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68854 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-11-01mb/google/brask/variants/moli: remove fan settingRaihow Shi
Disable Active Policy and remove fan setting to let ec control fan indenpendently. BUG=b:236294162 TEST=emerge-brask coreboot Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ie8851800d30ebf4d948d6eaadda2387c8afe52d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-10-30mb/google/skyrim: Implement touchscreen power sequencingMatt DeVillier
Assuming variants have a touchscreen by default, set the enable GPIO high and hold in reset during romstage, then release reset in ramstage. This will allow the touchscreen to make use of the runtime I2C detect feature (enabled in a subsequent commit) so that an ACPI device entry is created only for the touchscreen actually present. Variants/SKUs which do not have a touchscreen (if any) can use the romstage/ramstage GPIO override tables to set the associated enable/ reset GPIOs to NC. BUG=b:121309055 TEST=build/boot skyrim with rest of patch series Change-Id: Ic4d7ac8f951bb94da2216a24dc85a96275c9d449 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-29mb/google/brya/var/skolas: Adjust I2C3 CLK to meet 400 kHzAlanKY Lee
Fine tune I2C3 clock frequency under the 400 kHz. From 402.7 kHz to 382.9 kHz. BUG=b:255505160 BRANCH=firmware-brya-14505.B TEST=FW_NAME="skolas" emerge-brya coreboot chromeos-bootimage measure by scope with skolas Signed-off-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com> Change-Id: Ib6c3f895751387256378964ec76be45a4fcbba4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-28mb/google/skyrim/var/winterhold: Update touchscreen devicetree settingEricKY Cheng
Update touchscreen setting. ELAN900C is the I2C over hid device with slave address 0x10. MELF0410 is the pure I2C device with slave address 0x34. The LCD team verification result is on b/251378772 comment#11. BUG=b:251378772 TEST=Build/boot ChromeOS on winterhold, ensure touchscreen is functional. Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I568346d2abc39d9427e49c3b21f38db0184b8b44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2022-10-28mb/google/skyrim/var/winterhold: Enable DPTC supportEricKY Cheng
Enable DPTC support for Winterhold BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I97c2d3ee29687cd8a9c459e90a45cef05ac4436b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2022-10-28mb/google/skyrim/var/winterhold:Generate RAM IDs for new memory partsEricKY Cheng
Update H58G56BK7BX068 and H58G66BK7BX067 support BRANCH=None BUG=b:243337816 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I2aa6169c6e824318e738878f8cd19e76fcfd5713 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-10-28mb/google/brask/variants/moli: keep SAGV disableRaihow Shi
Since there is not too many low power requirement for moli and it is doing FSI firmware qual, so it is not critical to enable the SAGV and keep SAGV disable. BUG=b:254600066 TEST=emerge-brask coreboot Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I4115b35fed35b74a307b08f7a10ebced2309297f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68898 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-27mb/google/brya: Update Crota's ELAN touchscreen delay to 150 msPaz Zcharya
ELAN updated the datasheet of component 4599 (qualification 10511) to version 0.6 (upload date: Oct 24, 2022), decreasing i2c delay during power-on sequence from 300 ms to 150 ms. BUG=b:232893949 TEST=Manually checked touchscreen works after reboot and suspend (on kernel v5.10) Signed-off-by: Paz Zcharya <pazz@google.com> Change-Id: I17e1f7d419637f6dff4049484ce1836ad98017ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/68868 Reviewed-by: Eran Mitrani <mitrani@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-10-27mb/google/brya/var/lisbon: use i2c1 for TPM for lisbonKevin Chiu
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the lisbon variant. BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I16be50258db2111d22f7465458873e92f44c7dac Reviewed-on: https://review.coreboot.org/c/coreboot/+/68887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-27mb/google/brya: Update devicetree setting for lisbonKevin Chiu
update devicetree setting per the schematic BUG=b:246657849 TEST=emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I4268a5b43690a22bb703337fed84b83c45da4ad2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-27mb/google/brask/var/lisbon: Update gpio tableKevin Chiu
Based on latest schematic to update the gpio table. BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I531f9ca9f6902d3318e99dadb58a811a4686a6e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-27mb/google/skyrim: Expand cbmem console bufferZheng Bao
Expand the size of cbmem console buffer from default value 0x20000 to 0x80000. Verified by running "cbmem -l" in Chromium OS shell. localhost ~ # cbmem -l CBMEM table of contents: NAME ID START LENGTH 0. FSP MEMORY 46535052 b97fe000 01000000 1. CONSOLE 434f4e53 b977e000 00080000 2. RW MCACHE 574d5346 b977d000 00000360 3. RO MCACHE 524d5346 b977c000 00000f20 4. FMAP 464d4150 b977b000 0000047c 5. TIME STAMP 54494d45 b977a000 00000910 6. VBOOT WORK 78007343 b9766000 00014000 7. RAMSTAGE 9a357a9e b9700000 00066000 8. ACPI BERT 42455254 b96fc000 00004000 9. CHROMEOS NVS 434e5653 b96fb000 00000f00 10. REFCODE 04efc0de b96ab000 00050000 11. MEM INFO 494d454d b96aa000 00000768 12. RAMOOPS 05430095 b95aa000 00100000 13. COREBOOT 43425442 b95a2000 00008000 14. ACPI 41435049 b957e000 00024000 15. TPM2 TCGLOG 54504d32 b956e000 00010000 16. SMBIOS 534d4254 b9566000 00008000 17. FSP RUNTIME 52505346 ba7febe0 00000004 18. POWER STATE 50535454 ba7feb80 00000060 19. ROMSTAGE 47545352 ba7feb60 00000004 20. EARLY DRAM USAGE 4544524d ba7feb40 00000008 21. ACPI GNVS 474e5653 ba7feb20 00000020 BUG=246268888 TEST=Skyrim Change-Id: I79205f31b4cc3276c1c213a171a6bf7e18d73a1c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-27mb/google/brya/gaelin: Change DDR4 from interleave to non-interleaveRaymond Chung
The brask DDR4 is set to interleave, due to the limited number of gaelin PCB layers and the traces need to be smooth, we will use non-interleave for gaelin DDR4. BUG=b:255399229, b:249000573 BRANCH=firmware-brya-14505.B TEST=Build "emerge-brask coreboot" and pass MRC memory training Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8 Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-10-26mb/google/guybrush,skyrim,zork: rework FCH IRQ mapping table generationFelix Held
This ports the changes to the way the fch_pic_routing and fch_apic_routing arrays get populated from Mandolin to Guybrush, Skyrim and Zork. This is a preparation to move the init_tables implementation to the common AMD SoC code in a later patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie550238dfa0d4c7cebe849966d40fa0b1984a0f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/amd,google: unify fch_irq_routing struct instance nameFelix Held
Use the same fch_irq_map name in all mainboards using the Picasso, Cezanne, Mendocino and Morgana instead of using a mainboard-specific name. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I035cffb9c6c8afd6bd115831e8eed4a395e2a7fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>