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1. Describe the FW_CONFIG probe for the settings for Palutena.
- WIFI_SAR_ID_0 for AW Wi-Fi module AW-CM421NF
- WIFI_SAR_ID_1 for Intel Wi-Fi module AX211NGW
2. In contrast to the AW Wi-Fi module, the Intel Wi-Fi module needs
to load a SAR table in dedede platform.
3. For Palutena project, the SKU ID segment of Palutena is set for
"0x350000~0x35FFFF".
BUG=b:319792428
BRANCH=firmware-dedede-13606.B
TEST=build pass
Change-Id: Ic4f38928d24c4398d90df226cfe0788a30075bf2
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79930
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
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Add 6w and 15w fan performance control.
BUG=b:318454915
TEST=emerge-nissa coreboot chromeos-bootimage
Thermal team test pass.
Change-Id: If21baa2f6f9bcd527cec2bced27c5fb2cd607830
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79988
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Modify 6w/15w DPTF parameters based on b:290705146#comment41.
2. 6W MSR power limit_1 power (Watts) increase to 20.
3. 15W MSR power limit_1 power (Watts) increase to 20.
BUG=b:290705146
TEST=emerge-nissa coreboot chromeos-bootimage
Thermal team test pass.
Change-Id: I15fa4b8f7c7088ff56da6493659ae45572913b5a
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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I got confused and used UFS (User Facing Side) for the User Facing
Camera (UFC) in the FW_CONFIGs. Change references of the camera from
UFS --> UFC.
BUG=b:300690448
BRANCH=None
TEST=None. The camera has not been enabled yet.
Change-Id: I4f8240ae51aad1e077f325a9eab5a2a92f1402cb
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79997
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the references from the chipset devicetree as this makes the
comments superfluous.
Built all variants with BUILD_TIMELESS=1 and the resulting binaries
remain the same.
Change-Id: I22bcde2dea726f47f8d64a762ca147efde0b610d
Signed-off-by: Marvin Evers <marvin.evers@stud.hs-bochum.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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to 6ms
Modify touchscreen enable_delay to 6ms to meet with spec.
eKTH3915N_Product Spec_V1.3_20221028_IPM.pdf
BUG=b:318443640
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: Id57ab04e61d9e95c962f2c564d3a7e2e7ed6b992
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79978
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
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Gothrax cannot boot into OS with a kernel loading failure.
Update eMMC DLL values to improve initialization reliability
How to get these values:
- Sending different speed TX/RX command/data signal to eMMC and check
the response is successful or not.
- Collecting above results from each eMMC model that project used.
- Analysing logs to provide a fine tuned DLL values.
BUG=b:310701323
TEST=Cold reboot stress test over 2500 cycles
Change-Id: Ie36cc9948e3d5dee46385e584baad141a249be79
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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These are specific to the brox board, so moving devices to the brox
variant.
BUG=b:311450057,b:300690448,b:319058143
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
will check if this helps detect the storage device in the factory
Change-Id: I18d096040c293abfd4cd0b1bb5f50ba6dcc2e183
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Brox project has FW_CONFIG bits already set up in the project file for
the retimer and for storage, so make sure that the brox device tree
matches those settings.
BUG=b:311450057,b:300690448,b:319058143
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
will check if this helps detect the storage device in the factory
Change-Id: Iaf43003b7e8210eee9016d779839d7048c15825f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79854
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new memory Micron MT62F1G32D4DR-031 WT:B.
DRAM Part Name ID to assign
MT62F1G32D4DR-031 WT:B 2 (0010)
BUG=b:319778218
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I9e54958490228beb7039d531c709d56ec244b9e7
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79914
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The IVO_T109NW41 will be the second source MIPI panel for Ciri.
BUG=b:319025360
TEST=boot Ciri with IVO_T109NW41 panel, see firmware screen
BRANCH=None
Change-Id: I9dc2228d39bb8bb048d1f37727c96b0ad621e912
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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The MIPI panel BOE_NV110WUM_L60 will be used for Ciri, enable it.
Also remove the `mdelay(10)` after mtk_i2c_bus_init, because MTK
confirms this is not needed. Add mdelay(2) between VDD18 and VSP/VSN
to meet the panel datasheet.
BUG=b:308968270
TEST=Boot to firmware screen
BRANCH=None
Change-Id: I0a04f062f81c543d38716d7ff185b5633c1aa3a9
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78957
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I09dd5871cb366ef95410efc1ca6c4337f23b52fd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79912
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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BUG=b:311450057,b:300690448
BRANCH=None
TEST=to be tested on a device with i2cdetect
Change-Id: If6da1c722e87a50c6d422b300f16a52d884fa08f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This is needed for NVMe to work when PCIe device is connected to the
CPU side of RPL soc.
BUG=b:311450057,b:300690448, b:319058143
BRANCH=None
TEST=Tested on device and was able to boot to the OS
Change-Id: Ic8a1fdcedf2ec6c7bf1dd00e02ef7c13e9338aac
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This needs to be disabled for RPL otherwise we'll hit the assertion:
[EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/fsp_params.c', line 1066
There is a comment in the referenced file/line in the assertion that
says that "C state demotion must be disabled for Raptorlake J0 and Q0
SKUs." So, disabling it.
BUG=b:311450057,b:300690448
BRANCH=None
TEST=Tested that we didn't hit this assertion on the device after this
change
Change-Id: Ib7b2484de2d84c980550fd951f1e30efab0ee197
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79855
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1.In contrast to the MediaTek Wi-Fi module, the Intel Wi-Fi module needs
to load a SAR table.
2.Describe the FW_CONFIG probe for the settings.
- WIFI_6 for MTK Wi-Fi module MT7921L
- WIFI_6E for Intel Wi-Fi module AX211NGW
BUG=b:315418153
TEST=emerge-nissa coreboot
Change-Id: I37e8adc3de02707b2df541cc5e6f88083554eeb4
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
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driver
Since DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER value on dedede
cannot meet DRIVERS_I2C_SX9324 on nissa, need to update the tuning
value. Update proximity sensor fine tune value with quandiso EVT
machine.
BUG=b:314550601
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot and verify p-sensor
watch 'cat /sys/bus/iio/devices/iio:device*/*raw'
Change-Id: I5fc3bc5876594f2df79d628bd986113d37087c3d
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add PIXA touchpad for variants of craaskov.
BUG=b:289962540
TEST=build craaskov firmware and test with PIXA touchpad
Change-Id: Iccf19b275548f44aec00be8631590b8a7ad1aa23
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79872
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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Removes unnecessary HAVE_FSP_LOGO_SUPPORT config from google/rex
baseboard. Intel Meteor Lake SoC now selects this config
automatically for supported platforms.
BRANCH=firmware-rex-15709.B
TEST=Able to build and boot google/rex and intel/mtlrvp.
Change-Id: I89bdd54cb73b11f74db2927a5eb86ab826c60517
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79860
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Due to some without mipi camera SKUs can't entering S0i3.
BUG=b:317670018
TEST=suspend_stress_test -c 1
Change-Id: Ifa8649a603c59946b530abd315113b405ceaf35a
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This partially reverts commit f493857c9bc1 ("mb/google/brya/var/*: Set
dGPU/LAN/WLAN device type to generic"). Setting the WLAN device type to
generic broke ACPI SSDT table definition, so set it back to pci.
BUG=b:318576073
TEST=build/boot google/nissa (pujjo), verify WLAN ACPI SSDT tables
contain the appropriate device entry.
Change-Id: If5dad9deb040c8cb0c507e11726f0ba44ccb2909
Signed-off-by: David Ruth <druth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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TEST=check FW screen on dojo
Change-Id: Ie870899226588ac2a2e80f77e434455f4913d387
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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TEST=check FW screen on Steelix, Tentacruel and Starmie
Change-Id: I429218d59389a6ab86b522dd597c07fa5b8ea821
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79777
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The sequences of configure_display() are similar on MediaTek platforms.
The sequences usually involve following steps:
1. Setup mtcmos for display hardware block.
- mtcmos_display_power_on()
- mtcmos_protect_display_bus()
2. Configure backlight pins
3. Power on the panel
- It also powers on the bridge in MIPI DSI to eDP case.
4. General initialization for DDP(display data path)
5. Initialize eDP/MIPI DSI accordingly,
- For eDP path, it calls mtk_edp_init() to get edid from the panel
and initializes eDP driver.
- For MIPI DSI path, the edid is retrieved either from the bridge or
from CBFS (the serializable data), and then initializes DSI driver.
6. Set framebuffer bits per pixel
7. Setup DDP mode
8. Setup panel orientation
This patch extracts geralt/display.c to mediatek/common/display.c and
refactors `struct panel_description` to generalize the display init
sequences. configure_display() is also renamed to mtk_display_init().
TEST=check FW screen on geralt.
Change-Id: I403bba8a826de5f3fb2ea96a5403725ff194164f
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79776
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The DQS mapping for DIMM idx 6 was discovered to be incorrect to what
was in the schematics. Correcting the mistake in this CL.
BUG=b:311450057,b:300690448
BRANCH=None
TEST=tested on device and it passed memory training
Change-Id: I21f50e2f5b4fae09725c1c7532636ed1cc1a9043
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79843
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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For brya variants with a touchscreen, drive the enable GPIO high
starting in romstage while holding in reset, then disable the reset
GPIO in ramstage (done in the baseboard).
BUG=b:317746281
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I3ca2e2d12a86eaae9e37870a2541c0287e354690
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79764
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To avoid code duplication and to also bring the mainboards using the
Picasso SoC more in line with Cezanne and newer, factor out the SoC-
specific code from the mainboard's dsdt.asl files to the SoC's soc.asl.
TEST=Timeless builds result in identical images for Bilby, Mandolin, and
Zork/Morphius
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id4ed3a3d3cb55c8b3b474c66a7c1700e24fe908e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot, preventing privacy LED blink.
BUG=b:317434358
TEST=none
Change-Id: I43044e64c2c3a645ec0cad2ac903cc19ac89c9af
Signed-off-by: Jason Chen <jason.z.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79803
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
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Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.
Built all variants with BUILD_TIMELESS=1 and the resulting binaries
remain the same.
Change-Id: I7752819091e2a75c8d818f7d0cf90eabc11c4759
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Marvin Evers <marvin.evers@stud.hs-bochum.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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1. Set PCIe related GPIOs to NC if fw_config use "WIFI_CNVI".
2. Set CNVi related GPIOs to NC if fw_config use "WIFI_PCIE".
3. Remove "ALC5650_NO_AMP_I2S" case in
fw_config_gpio_padbased_override(). bt_i2s_enable_pads should not
relevant to audio codec/amp, and it is already enabled in "WIFI_CNVI"
case.
BUG=b:312099281
TEST=Build and test on karis
Change-Id: Ib1a32f1a38ae33cf992b80a3408aa8e2fa3ddab0
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79765
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add touchscreen ILTK for craaskwell.
Refer to ILI2901A-A200 Data Sheet_V1.1_20231026.
BUG=b:308873706
TEST=build and check touchscreen function on craask
Change-Id: I6a68855b1659ff0c9cd33a0ec9acbd289f525a3d
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79735
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
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Create the dita variant of the taranza project by
copying the files to a new directory named for the variant.
BUG=b:317292413
BRANCH=dedede
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_DITA
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I843e33f30cd356e4f12330bdfe2d53a0b3920ef3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79655
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
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As a preparation for WiFi SAR table addition, adding hook for it.
BRANCH=nissa
BUG=b:315418153
TEST=emerge-nissa coreboot
Cq-Depend: chrome-internal:6790137
Change-Id: Idb200699bb8c8581b9512ec8ec9442f65f8822b3
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add GFX devices for DDI (eDP and HDMI) and TCP (USC C0 and C2
ports). Copied the PLD placements from USB PLDs.
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: Ic39916819f64ede1c80eccfd05ba4916b9f285af
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
|
|
Update definition to be more intuitive and extensible.
Port descriptors will be defined as individual entities and added
to the descriptor list as such.
BUG=b:281059446
TEST=builds
Change-Id: I23ddd11b7e4da35a0d81299aa648f928e81ea24e
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79626
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update definition to be more intuitive and extensible.
Port descriptors will be defined as individual entities and added
to the descriptor list as such.
BUG=b:281059446
TEST=builds
Change-Id: Ic5a06a7d1bdb9123a0a242a571f094ac3233d7b2
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79627
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
This is a preparation to make the next patch result in identical images
for timeless builds and also aligns Zork's DSDT more with Guybrush's
DSDT.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I46835b404be13f150c68680afb3fcc78639e08f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
update DTT settings for thermal control,the values before
Sensor1 and Sensor2 were set too high. Modify the protection
temperature to better meet DUT requirements.
BUG=b:291217859
BRANCH=none
TEST=emerge-rex coreboot
Change-Id: I8abc866c0d05a2437c34198e6b8fb4a58c1cb829
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79683
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
According to datasheet, EN_TCHSCR_PWR high --> SOC_TCHSCR_RST_R_L high
should over 5ms. And current measure result is 200us.
Set EN_TCHSCR_PWR to output high in bootblock to make it meet datasheet
requirment.
Measurement result of EN_TCHSCR_PWR high --> SOC_TCHSCR_RST_R_L high:
Power on --> 31.7 ms
Resume --> 38.7 ms
BUG=b:314245238
TEST=Measure the sequence
Change-Id: I56e455a980b465f27794b30df058ec0944befc2e
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79571
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add probe DB_C_A_LTE/DB_C_A for Type-C Port C1 (daughter board).
DB_A is only used for skus without Type-C Port C1.
BUG=b:316048649
TEST=emerge-nissa coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: Ifb702c497740953144b43c56653da16fade1053f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79629
Reviewed-by: Kyle Lin <kylelinck@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Some GPIOs were not configured correctly according to the HW
spreadsheet provided by the HW team.
* GPP_B5/GPP_B6 use NF1, not NF2
* GPP_B23 should use NF2, no GPI
* GPP_D11 should be set to NC
* GPP_E21/22 should be using NF (previous NC)
* GPP_F17 is a GPO
* GPP_F18 should be an interrupt, not a NF
BUG=b:300690448,b:316180020
BRANCH=NONE
TEST=emerge-brox coreboot
Change-Id: I9e1e62adb79bd7fdab935afdbf2d23f9061b88aa
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Did a pass through HW team's brox speadsheet and aligned the gpio.c
file with it. The changes in this CL are to fix the pad's reset field
as needed. See "Intel SoCs" section in
https://doc.coreboot.org/getting_started/gpio.html for reset
definitions.
BUG=b:300690448,b:316180020
BRANCH=NONE
TEST=emerge-brox coreboot
Change-Id: I4285136184c648adb9dc97748bd6b01cba3f8ddd
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Did a pass through HW team's brox speadsheet and aligned the gpio.c
file with it. The changes in this CL include fixing the pulls for
GPIOs as necessary, making sure that it matches what is in the HW
team's spreadsheet.
BUG=b:300690448
BRANCH=NONE
TEST=emerge-brox coreboot
Change-Id: Ie50cb3c6fc85f1633c1afd1330c0e040e04b0ec1
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79704
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Did a pass through HW team's brox speadsheet and aligned the gpio.c
file with it. The changes here include changing the pad config to NC
because it is not being used in ChromeOS.
BUG=b:300690448
BRANCH=NONE
TEST=emerge-brox coreboot
Change-Id: I15471e4d7ff25c858b05ef024f15ca7c0b9e598e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79703
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add HDMI GPIO configuration to early GPIO list to support
VGA text o/p in Pre-RAM stage on HDMI.
BUG=b:316982707
TEST=Erase MRC cache and reboot, SOL text display on HDMI/eDP
Change-Id: Idb2af56baeb4d0ef9db5fc1c5dbcebecee6515e6
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79572
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
|
|
Since the camera sensor and camera eeprom share GPP_A12, remove
the off timing to avoid issue of camera sensor loss, but this
will increase system power by 5mW.
(Before root cause, this is a short term workaround to unblock
function test.)
BUG=b:298126852
TEST=1. Run coldreboot/warmreboot check see if the camera sensor lost.
2. Run S0ix check to see if the camera function abnormal.
Change-Id: I49b6ecbfbf3dddd6575bdaaf9c8fd0ee6c09af25
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79647
Reviewed-by: Jason Z Chen <jason.z.chen@intel.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
|
|
set slew rate to 1/8 for GT domain.
BUG=b:312405633
BRANCH=none
TEST=Able to build and boot google/screebo
Change-Id: Ib5cb07b7effc4a51c2119183010a03e026f639f8
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
|
|
Some of the boards use the EC_SYNC pin to wake the AP but do not
advertise the pin as wake capable in the CREC _CRS resource. Relevant
boards were determined through empirical testing and inspection of gpio
configuration.
Update the ACPI tables for rex, brya, and brox based boards to advertise
their EC_SYNC pin as wake capable.
BUG=b:243700486
TEST=-Dump ACPI and verify ExclusiveAndWake share type is set when
EC_SYNC_IRQ_WAKE_CAPABLE is defined
-Wake Aviko via keypress and verify chromeos-ec as wake source
-Wake Screebo via lid open and verify chromeos-ec as wake source
Change-Id: I5828be7c9420cab6ae838272c8301c302a3e078c
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79374
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
FSP default value for LpDdrDqDqsReTraining is 1. For boards
that didn't set LpDdrDqDqsReTraining to any value, 0 was being
assigned and it caused black screen issue.
BUG=b:311450057
BRANCH=NONE
TEST=emerge-brox coreboot
Change-Id: I4a009076e50408a4f7ff16ddc96a0f2e47b09470
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79646
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
GPP_B02 and GPP_B03 were set incorrectly previously.
This CL corrects these settings according to schematics.
BUG=b:305793886
TEST=Built FW image correctly.
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Id62f15f7a77ac43c72cc6b2645816d6c87133a0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Only EC will use field "PANEL_PWRSEQ_EC_CONTROL".
Add this field in coreboot for align fw_config settings.
BUG=b:314245238
TEST=emerge coreboot pass
Change-Id: Icecb44a338ddc28027e362332c6a69cc9fd268d5
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79570
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
After confirm with thermal, only EC will reference FAN field in
fw_config.
Update the settings for align fw_config.
BUG=b:307822225
TEST=emerge coreboot pass
Change-Id: Id7c4cdba29c5500c06d0f2293495650bb14b9e9c
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79573
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
|
|
Use same indent levels for switch/case in order to comply with the
linter.
Change-Id: I602cf024ec84b15b783d36014c725826f9d6595e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79418
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable Acoustic noise mitigation for google/screebo and set slew rate
to 1/8 for IA domain and ignore the slew rate for SA domain.
BUG=b:312405633,
TEST=Able to build and boot google/screebo.
Before:
[SPEW ] AcousticNoiseMitigation : 0x0
[SPEW ] FastPkgCRampDisable for Index = 0 : 0x0
[SPEW ] SlowSlewRate for Index = 0 : 0x0
After:
[SPEW ] AcousticNoiseMitigation : 0x1
[SPEW ] FastPkgCRampDisable for Index = 0 : 0x1
[SPEW ] SlowSlewRate for Index = 0 : 0x2
Change-Id: Ib86939ab48c2c6e7d0491d7c1cb4a2c7c6a1b568
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79323
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
|
|
This updates all warnings currently being printed under the files_added
and build_complete targets to the show_notices target.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia14d790dd377f2892f047059b6d24e5b5c5ea823
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79423
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
when S0ix returns S0, PERST needs to delay until
Main 3V3 is stable and then pull up
BUG=b:313976507
TEST=emerge-rex coreboot,measurement waveform verify pass
Change-Id: I33a86e52fab3c5c8cba6ebed0cbdd1b88b6538b0
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79320
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
For EVT SCH:
1. Use GPP_D15 to control AVDD and AFVDD simultaneously for MIPI Camera.
2. Delay reset for 5ms when device power on.
BUG=b:312663347
TEST=1. Google Camera app working
2. Passed EA verified
Change-Id: I880fb309fcef006090e2849fa6c3a0d472851851
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
With 1ms delay, reset is de-asserted too soon, before power is fully
up, causing a glitch to the reset signal. The issue is resolved with
4ms delay.
TEST=tested on google/jinlon device and observed the issue is resolved.
BUG=b:260253945
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I4efe916824cc193a7c2db7599b37f0d4de40bfce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79474
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
BUG=b:312099281
TEST=Build and boot to Karis. Verify the config from serial logs.
w/o this CL -
```
[SPEW ] ------------------ CNVi Config ------------------
[SPEW ] CNVi Mode = 1
[SPEW ] Wi-Fi Core = 1
[SPEW ] BT Core = 1
[SPEW ] BT Audio Offload = 0
[SPEW ] BT Interface = 1
```
w/ this CL -
```
[SPEW ] ------------------ CNVi Config ------------------
[SPEW ] CNVi Mode = 1
[SPEW ] Wi-Fi Core = 1
[SPEW ] BT Core = 1
[SPEW ] BT Audio Offload = 1
[SPEW ] BT Interface = 1
```
Change-Id: Icd2c42261fdcfa5aac17be28fde3804348ddf9b4
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
1. Anraggar doesn't support SDCard, so disable SDCard contorller.
2. Not disabling it will cause can't enter S0ix on first suspend.
BUG=b:313585586
TEST=1. check lspci
2. can enter S0ix on first suspend
Change-Id: Ie4747d9c5d6ae93d29ef78b629855e0dd320c4db
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
This file is identical to the copy currently found in the blobs
repository; it is simply being relocated for consistency and since it
does not need to be in an external repo.
BUG=none
TEST=build/boot skyrim
Change-Id: I352f58e0d3965356f3282a2653c6c11b44853857
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
|
|
This file is identical to the copy currently found in the blobs
repository; it is simply being relocated for consistency and since it
does not need to be in an external repo.
BUG=none
TEST=build/boot guybrush
Change-Id: Ice4cbaccca13e9c4ae246fdcde5c89aa2086f1e1
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
|
|
This file is identical to the copy currently found in the amd_blobs
repository; it is simply being relocated since it is mainboard specific
and does not need to be in an external repo.
BUG=none
TEST=build/boot morphius
Change-Id: Ia78fcd065fbf4d5ba6ec4edc3f8f937badf66ecc
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79591
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
For initial debugging, we want to disable SW syncing. Will re-enable
in the future.
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
run gbb_utility --get --flags <image>
make sure that it returns 0xa39
Change-Id: I865e9585ab37d1328a0ff54c6343cdad2c02220c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79569
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
|
|
The default EPP is set at 50%, which is deemed insufficiently
aggressive for meeting the MTL performance expectations in
balance_performance mode.
# cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference
balance_performance
# iotools rdmsr 0 0x774
0x0000000080003f06
EPP=45% is giving the required performance in MTL.
# iotools rdmsr 0 0x774
0x0000000073003d06
NOTE: Kernel changes are necessary to ensure that the EPP (Energy Performance Preference) configured in the BIOS is not overwritten: https://patchwork.kernel.org/patch/13461932
BUG=b:314275133
TEST=Build and boot.
Change-Id: I1953994cdb4e9363fdd4b4728e3e5236276c06c8
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79386
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Non-touchscreen sku will set related GPIOs to NC. If touchscreen enabled
in overridetree for non-touchscreen sku, the boot time will be 6-7s. Set
touchscreen probed to TOUCHSCREEN_UNKNOWN for reduce boot time from 6-7s
to under 1s.
BUG=b:316434359
BRANCH=firmware-nissa-15217.B
TEST=Boot time (cbmem -t) from 6,460,972 to 922,844
Change-Id: I016ce762f726b7624bd060284f74f0992cb129b6
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
|
|
FSP default value for LpDdrDqDqsReTraining is 1. For boards
that didn't set LpDdrDqDqsReTraining to any value, 0 was being
assigned and it caused black screen issue.
BUG=b:302465393
TEST=Boot to OS with debug FSP, check LpDdrDqDqsReTraining = 1
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I301a6e43f2944ffbc63431393378ab8b23450032
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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The original DA7219 is designed to use a 500ohm mic detection
threshold. Some headset mics (e.g. Logitech H111) have a lower DC impedance that is lower than the threshold and thus cannot be
detected. Lower the threshold to 200ohm to match the new default
value provided by Renasas as in https://patchwork.kernel.org/project/alsa-devel/patch/20231201042933.26392-1-David.Rau.opensource@dm.renesas.com/ to support such headsets.
BUG=b:314062160,b:308207450
Change-Id: I6415e84a4622e0c61bc74b94536fe734048a043f
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
FSP default value for LpDdrDqDqsReTraining is 1. For boards
that didn't set LpDdrDqDqsReTraining to any value, 0 was being
assigned and it caused black screen issue.
BUG=b:302465393,b:315739133
TEST=Boot to OS with debug FSP, check LpDdrDqDqsReTraining = 1
Change-Id: I5d61301fddac6630bb1c48e992dd76e5cf02a272
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79533
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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Change GPP_B14 from UP_20K to NONE for compatible
with DVT1 and DVT2 board
BUG=b:272447747
TEST=enable usb OC2 function to ensure USBA work normal
Change-Id: Ib7720980335660f423b3a74199ceedc113ec70df
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79431
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Update DTT settings based on the suggestion of the thermal.
BUG=b:313833488
TEST=emerge-nissa coreboot
Change-Id: I2296990062cadc05202e3d1ab90af04234bda885
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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1. Ref to SCH, LTE use USB3 Port3, enable it.
2. Explicitly define the use of USB3 Port1 & USB3 Port2.
BUG=b:315061146
TEST=can pass PCIe Hardware Compliance Test
Change-Id: I03d6925020012fa740bbd0168a2f5b02ea6763b4
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Change code style to be compatible with Nissa's format:
register "option" = "{
[0] = value /* comment */
...
}"
to
register "option[0]" = "value" /* comment */
BUG=none
TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar
Change-Id: I60659bd44813173f9b984216473a0919c5f331b8
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Add the MICRON MT62F1G32D2DS-023 WT:B RAM part for brox:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
MT62F1G32D2DS-023 WT:B 2 (0010)
BUG=b:311450057,b:315913909
BRANCH=None
TEST=Run part_id_gen tool without any errors
Change-Id: Id120a5eb311d8299a8e59d2c1658fe0742e93934
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Adjust PL1 max value from 15W to 25W
BUG=b:314263021
TEST=emerge-rex coreboot
Change-Id: I4122a13d7e33c736299c1a759ec51f7a3b29340f
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79377
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update proximity sensor tuning value from dedede/kracko tuning.
Remove GPIO override to use the configuration from nissa baseboard:
- GPP_B5 ==> SOC_I2C_SUB_SDA
- GPP_B6 ==> SOC_I2C_SUB_SCL
BUG=b:310050220
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I7c687677a797415d80be4c420484d3346a8455f6
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79247
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Updated Linux FW works with PCI gen3 speed and PSPP.
This reverts
commit 05c9a850fd21 ("mb/google/nipperkin: Fix WLAN to GEN2 speed")
https://review.coreboot.org/c/coreboot/+/63593
and
commit 76fddd963925 ("mb/google/nipperkin: Disable PSPP for WLAN")
https://review.coreboot.org/c/coreboot/+/63722
The changes are overlapped and are reverted together.
BUG=b:240426142 & b:228830362
The system is able to ran over 2500 cycles on Nipperkin with command
suspend_stress_test -c 10000 --wake_min 10 --suspend_min 10 \
--nofw_errors_fatal
The whole variant_update_dxio_descriptors is empty and is pushed back
to weak function.
Change-Id: Id207076542edc8ea0cabc6e02e29856c2b6803c7
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
|
|
Enable BT offload when I2S option is selected for screebo.
BUG=b:275538390
TEST=Verified audio playback using BT speaker/headset in I2S mode on google/screebo.
Fixes: https://review.coreboot.org/c/coreboot/+/77755
Change-Id: I7ebe8e28d35428ce2fb8129dc145fec9ac60f9da
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79378
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Due to TCPC0 & TCPC1 exchanged compare to Neried design,
but related USB2 Ports not exchanged, keep mainboard C port to conn0.
BUG=b:312998945
TEST=can boot from external Type-c USB disk
Change-Id: Ib8df4a256bd9cd1b2ca229b09d68f97babc8092e
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Update brox devicetree based on the latest schematics.
- Configure typeC to EC mux ports settings.
- Configure USB2/USB3 ports settings.
- Configure TCSS ports settings.
BUG=b:311450057
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: Iac5a2e8be6cea64f107d267d4cf71529f08bb63d
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79391
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add the support LP5 RAM parts for brox:
1. HYNIX LPDDR5 6400 2GB H9JCNNNBK3MLYR-N6E
2. MICRON LPDDR5 6400 4GB MT62F1G32D4DR-031 WT:B
DRAM Part Name ID to assign
H9JCNNNBK3MLYR-N6E 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
BUG=b:311450057
BRANCH=None
TEST=Run part_id_gen tool without any errors
Change-Id: Ib17f26a310435e37088191594863a645aa751440
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79392
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
BUG=b:305793886
TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku
Change-Id: I41a64252f08304ffc66fd782e54720252064ca49
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Fix up the memory config for brox based on the schematics. Also,
since memory training needs to happen in romstage, initializing the
MEM_STRAP & MEM_CH_SEL gpios for use in romstage. Also consolidating
the GPIOs needing to be initialized in romstage into the baseboard
gpio.c file.
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
|
|
This patch allows variants to override the default baseboard PLx
limits.
Additionally, rearrange the include header files alphabetically.
BUG=b:313667378
TEST=Able to boot google/screebo with modified power limits.
Before:
[DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/rex/
ramstage.c/variant_devtree_update called
[INFO ] Overriding power limits PL1 (mW) (10000, 15000)
PL2 (mW) (40000, 40000) PL4 (W) (84)
After:
[INFO ] Overriding power limits PL1 (mW) (10000, 15000)
PL2 (mW) (40000, 40000) PL4 (W) (84)
Change-Id: Ic66872c530963238a0bf5eebbd5b5a76a7985e5c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
+-------------+----------------+------------+
| USB 2.0 | Connector Type | OC Mapping |
+-------------+----------------+------------+
| 1 | Type-C | OC_0 |
+-------------+----------------+------------+
| 2 | Type-C | OC_0 |
+-------------+----------------+------------+
| 3 | Type-C | OC-0 |
+-------------+----------------+------------+
| 4 | Type-A | OC_3 |
+-------------+----------------+------------+
| 5 | Type-C | OC_0 |
+-------------+----------------+------------+
| 6 | Type-A | OC_3 |
+-------------+----------------+------------+
| 7 | Type-A | OC_3 |
+-------------+----------------+------------+
| 8 | Type-A | OC_3 |
+-------------+----------------+------------+
| 9 | Type-A | OC_3 |
+-------------+----------------+------------+
| 10 | BT | NA |
+-------------+----------------+------------+
+---------------------+-------------------+------------+
| USB 3.2 Gen 2x1 | Connector Details | OC Mapping |
+---------------------+-------------------+------------+
| 1 | Type-A | OC_3 |
+---------------------+-------------------+------------+
| 2 | Type-A | OC_3 |
+---------------------+-------------------+------------+
+------+-------------------+------------+
| TCPx | Connector Details | OC Mapping |
+------+-------------------+------------+
| 1 | Type C port 0 | OC_0 |
+------+-------------------+------------+
| 2 | Type C port 1 | OC_0 |
+------+-------------------+------------+
| 3 | Type C port 2 | OC_0 |
+------+-------------------+------------+
| 4 | Type C port 3 | OC_0 |
+------+-------------------+------------+
BUG=b:305793886
TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I90d3d984af6d40efb4553cf5675617700161d2d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Add default Intel DPTF.
BUG=b:305793886
TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Id681754fc8e7b418de35f66df097cadd4aad7448
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
google/deku is a Chromebox featuring two LAN ports.
Add overridetree.cb entry to configure the LAN0 LAN1 devices.
BUG=b:305793886
TEST=Built FW image correctly.
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I8980dabc7f9fc731a2b60c599e1e48c9b11dabb4
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79292
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This patch adds the power limit configuration for MCH ID index 3 aka
0x7d14 DID which is identical to MCH ID 0x7d01 (index 1).
TEST=Able to perform power limit configuration for google/ovis.
[DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/ovis/
ramstage.c/variant_devtree_update called
[INFO ] Overriding power limits PL1 (mW) (19000, 28000)
PL2 (mW) (64000, 64000) PL4 (W) (120)
Change-Id: Iff71adb4e26d18970b5947927c258419f751de32
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79332
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
This patch removes the deprecated PL_PERFORMANCE and PL_BASELINE
configurations, relying instead on the refactored power limit flow.
This flow allows for seamless overrides by the baseboard and/or by
the variant board, if necessary.
Specifically, this patch:
- Removes PL_PERFORMANCE and PL_BASELINE configuration options from
mainboard.c in the google/rex directory.
- Relies on the baseboard_devtree_update() function, which is
implemented by the respective baseboard, to handle power limit
configuration.
- Leverages the variant_devtree_update() function, which is a
__weak implementation, to allow overrides by the variant directory.
This simplification improves code readability and maintainability while
maintaining the flexibility to handle power limit configurations as
needed.
Change-Id: I872e5cb59d7b2789ef517d4a090189785db46b85
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79331
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch expands the power limit override capability to include
variants directories, enabling them to modify power limit settings
configured by the baseboard.
Previously, only the baseboard could override power limit settings.
For instance, while the google/rex baseboard sets the PL1 max power
limit to 15W, the google/screebo variant couldn't override this value.
This enhancement empowers variants directories to override baseboard-
configured power limit settings, allowing for greater flexibility and
control over power limits.
BUG=b:313667378
TEST=Able to call into _weak implementation of `variant_devtree_update`
unless there is one override.
[DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/rex/
ramstage.c/variant_devtree_update called
[INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW)
(40000, 40000) PL4 (W) (84)
Change-Id: Ib07691625e075b0fbab42271512322ffc60ba13b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Trim all GPIO comments like "origin ==> current".
BUG=b:304920262
TEST=pass building
Change-Id: I05daa4df16b6da3d3f971b75c7c467032e3f854d
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79321
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Fix GPP_D6 configuration for LTE power enable.
BUG=b:304920262
TEST=mmcli -m any
Change-Id: I2996fd35c2897269997bc0290e0ce93bbbaa1bf8
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79166
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
|
|
Due to TCPC0 & TCPC1 exchanged compare to Neried design,
but related USB2 Ports not exchanged.
BUG=b:304920262
TEST=Tpye-C & DP functions workable
Change-Id: I9dacf06b1e672575a684856acdb10b6c88360b18
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79165
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
For proto PCB:
GPP_C0 for enable power supply which also for sensor subsystem.
GPP_C0 must allways turn power on, so GPP_C6 is not only used
for enable function but also for stop report.
BUG=b:304920262
TEST=1. touchscreen function workable
2. INT pin no active during suspend
Change-Id: I7dabf205dba616f57ef9717f950eba96282d8e3d
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
|
|
Update overridetree to correct AUX pin to USB-C port 3
BUG=b:299570339
TEST=emerge-brya coreboot chromeos-bootimage
Change-Id: I3a5a89c6008fbf28c927f83060e6e508d60845ba
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79343
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Brox has SSD and UFS storage per different SKU.
1. Set SSD on CPU PCIe port (PCIEX4_A) and configure related gpio
settings according to the schematic.
2. Enable UFS, also enable ISH since it is PCI function 0, required
for UFS function 7 to be enabled.
3. Set unused SRCCLKREQ signals to NC.
4. Remove unused gpio settings in variant gpio table to prevent
unexpected overrides.
BUG=b:311450057
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I88922bcfa13652006aa10078c3c444624fd4575e
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79295
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Based on Platform Mapping Document for Deku (go/cros-deku-mapping)
from Nov 8, 2023 (Rev 0.4)
BUG=b:305793886
TEST=WIP, not tested yet
Change-Id: Ib37a7ebf0aca788d14fafea0f97e364beafb4c4d
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78960
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Use fw_config to differentiate audio amps instead of the
kconfig option.
BRANCH=corsola
BUG=b:305828247
TEST=Verify devbeep in depthcharge console
Change-Id: I5f887f5e0d16dc14039fb12b636257d01339b2de
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79309
Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Quandiso does not use DB_1C, replace the fw_config with LTE only
daughterboard.
BUG=b:312094048
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Id7129e52d3733f62405f9d766f08563f05016c69
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79297
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Shawn Ku <shawnku@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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