| Age | Commit message (Collapse) | Author |
|---|
|
Modify DPTF parameters for OEM EVT build from thermal team.
BUG=b:153589525
BRANCH=None
TEST=emerge-puff coreboot chromeos-bootimage and boot on puff board
Change-Id: I36db172e4d2ccc854856641c510cff9fe04ea235
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
A verbatim copy of variants/puff
V.2: rebased on duffy.
BUG=b:152951180
BRANCH=none
TEST=none
Change-Id: I7ea28e96c8b6867e17097a8bfab848928195654d
Signed-off-by: Andrew McRae <amcrae@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
|
|
A verbatim copy of variants/puff.
BUG=b:152951181
BRANCH=none
TEST=none
Change-Id: I9ac262bba60a8d0059722e947ed1b47dddb94f55
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40223
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I4d9bc98863c4f33c19e295b642f48c51921ed984
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37069
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:152927525
BRANCH=none
TEST=builds
Change-Id: I691377624c870eb0fc6f7e84a4b9cd50b7b09654
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
|
|
Tunes the headphone amp i2c with measured signal shape.
BUG=b:147192377
BRANCH=none
TEST=builds and measured i2c frequency below 400khz
Change-Id: I60f73bcf60ed140f595c953be371b982a63f7b95
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
We decided to add a third RAM_CODE pin to the Trogdor family for devices
after rev1. This patch adds support to read it. Since the newly used pin
was previously unconnected (not pulled down) on rev1, this will change
the RAM_CODE result for previous versions (and actually make it
undetermined until we enable tri-state). But since we're not actually
using RAM_CODE for anything yet, and since those are development
revisions that will eventually be discontinued, this should be fine.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I9b52982f17646a305b1a3e2c7d37606a7c38d0c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
|
|
Update tdp_pl1_override value to 15W for CML-U based nightfury platform.
BUG=None
BRANCH=firmware-hatch-12672.B
TEST=Built
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: Ib0155b961b9d304bed2e9456c4964ebd598af4dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Reference Drallion to add device tree for Melfas touch screen.
BUG=b:152924290
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I7b0a42119891c6c2d5978d7f33eefffa2d62df76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Since the first LFPS timeout causes xHCI to enter compliance
mode, the SS hub cannot be enumerated. The resolution is to
disable xHCI compliance mode.
BRANCH=octopus
BUG=b:153782196
TEST=Verified usb operation successfully.
Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com>
Change-Id: If0bf68c8cf0a2a3b857395b6b82e46cc384ba65c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39874
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add ELAN EKTH6918 USI touchscreen support.
BUG=b:152936745
TEST="emerge-dedede coreboot chromeos-bootimage", build successful.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I030c7d7e76a9705be06fe907c4ac279e247cb163
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Add SiS9813 USI touchscreen support.
BUG=b:152936541
TEST="emerge-dedede coreboot chromeos-bootimage", build successful.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Id04c46c763fdf68418bf2e97be4c8bb6bb73c749
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40250
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I38d429245810f64a03253b5076391af843f8d0de
Fixes: e2ac5b7a36 ("mb/google/hatch/variants: Add DPTF based Fan control")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: Ia707295c55ce2e18eb8970506be10b7b0f3fbc39
Fixes: b77cbbe1b0 ("mb/google/poppy/variants/nami: Update DPTF table")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
BUG=b:151166040
TEST= build and boot volteer and check LTR and AER value
from FSP log
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ibbf55e6a08ff5e8f358325bb8e9f1487cc982f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40268
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
According to Intel Document #616599,
1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10
columns)
2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel
x16)
This change fixes those two values in the existing SPD files for
Volteer, and zero's byte 9 (bytes 8-11 should be zero'd out in a
generic SPD).
BUG=b:152827558
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
Volteer to kernel.
Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
Fix GPIO_PCH_WP (GPP_B11) to associate GPP_PCH_WP with community
zero instead of community 1.
BUG=b:152876091
TEST="emerge-volteer coreboot chromeos-bootimage", flash, boot to
and log into Volteer kernel, execute "wp enable" in H1 console,
execute "crossystem" at kernel prompt and verify that "wpsw_cur"
shows as being "1", Execute "wp disable" in H1 console, execute
"crossystem" at kernel prompt and verify "wpsw_cur" is 0.
Change-Id: I082154efd72459ec54999ed7c7bb7420a38f7b6e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
- Configure devicetree for enabling GbE on variant
and remove from baseboard.
- Configure Kconfig to enable GbE region.
- Configure fmd to incorporate GbE.
BUG=b:151102809
Cq-Depend: chrome-internal:2843183
Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I1c36b132546049e3e775585c41164072f4ece73e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
|
|
For Deltaur and Deltan variants return proper SKU ID based on EC
firmware type and sensor detect GPIO value
BUG=b:152544516
TEST=make build successful for deltan
Change-Id: I20a497739e5062400b093648c3a634203dec6105
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Update dq, dqs map based on deltan schematics.
Configure memory to read SPD.
BUG=b:151702387
Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Update memory configuration on Tiger Lake platform to enable Early
Command Training. This feature was not supported before FSP v2527.
BUG=b:150357377
BRANCH=None
TEST= Build and boot volteer
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I674c30f4dfc1af6c0c4a460d66684545a190caf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40023
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
When EC_GOOGLE_CHROMEEC_SKUID is selected provide an
implementation of smbios_mainboard_manufacturer() so the code
doesn't need to be duplicated in the mainboards.
BUG=b:153767369
Change-Id: Ib65fe373a79d606cffcba71882b0db61be5a18c3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Modify board name from "Kadadu" to "Kakadu"
BUG=b:153590144
TEST=CPU log show "Starting depthcharge on Kakadu..."
BRANCH=kukui
Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com>
Change-Id: Ibf387b0e0153315ff2ab5c19381db44a61c14e96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40283
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I02979a0632a7b356985f96c3ba239daba178b4e3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39989
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
TEST=Build and boot the mainboard. Ensure that the touchpad is
operational.
Change-Id: I937462cd3992a884194bbd1759a0802a147e925a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
According to the EDS, EC_AP_PWR_BTN_ODL has a default internal pull-up
of 20K. Retain it during the GPIO pad configuration.
BUG=b:150985246
TEST=Boot the mainboard.
Change-Id: I042ba70f78fca1a5b9eda30029df97b3f8e65656
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39852
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In some cases Hatch variants are not laptop form-factors such
as Puff. Ensure that the base configuration does not assume
the form factor and allow variants to elect their intended
use-case.
Note that the issue is that early ec sync needs to be
disabled for EFS2 to function correctly, see commit 6daa8c3ba5f
from the FIXME line. The relationship is that desktops do not
have a battery.
BUG=b:152951181
BRANCH=none
TEST=none
Change-Id: I15dc9efa51e9d61297868df287879dfb62909e33
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40252
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Apply initial DPTF parameters for nightfury from internal thermal team. Will update after further thermal/performance tuning.
BUG=b:149226871
BRANCH=firmware-hatch-12672.B
TEST=built and verified FAN worked by DPTF active policy
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I712bdd8edc999ef7ee33f4adf21893be12e86bec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Since the first LFPS timeout causes xHCI to enter compliance
mode, the SS hub cannot be enumerated. The resolution is to
disable xHCI compliance mode.
BRANCH=octopus
BUG=b:149723583
TEST=Verified USB operation successfully.
Signed-off-by: tong.lin <tong.lin@bitland.corp-partner.google.com>
Change-Id: I3e6ab6ec0c4865cf2467da900f13d18468ff356f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marco Chen <marcochen@google.com>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I0dea26da28a2879e34593907fef6f984317c347f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40191
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Idfc7a5713e231c4756b5faca8984c6598fe1e65a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40190
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I74fd273aff05e6635d4964f3614c2f1dd5562b4b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40194
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I8076155330100982de82d410b6579ac99ed89e7b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40187
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Ic3314eb6137a6fc9fa1f90685f37223ca1580cb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40197
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Ia64c49aed694eac1f98d176c646a60597c8ae66a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40193
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I377ee2c9dfa3113f88237bd6ea79031a79f18ad5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40180
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I78f386eb47fc9b91992884e309dbbf33fb3d4e92
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40179
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I57e6790e49032902703ba84b68f285749aab2573
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Iddcf70e9a0976cfe2e5fb6d557bfcd22ab1f68cf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40181
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I0f41016ea678f63f386c1ae7006b7221a05f6fd9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I8e2aaf681ba3543cfcd400d21f8e94454e9b1c98
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40202
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Ib28acdb91c5eb0c06413edfab62d6737932946f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40201
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I22232d098d34b9a642da157d07978b8d044926ff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Ie2f0dac5a0dee26b965616d410e343569588db7e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Icabeae8d5c6c8be8dc284354e1523cec04c9fe30
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40200
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Ie27b19e2a15855def11e366a86e43776ceb71083
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I46f098f38576dee14b34789c24ad5513ed47fac1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I267f0f989112907f45868c1bdfd3fa117851e586
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Ie6fb3a47a6ac39a435605ef6aeb30f8001c0a166
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I5e297e7c68d5c2646d1a086ae1a5b64fef7ed730
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Iea5f9af845fda3ffff303aed402edea8b9eb219a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40183
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I3be3f10d1f9399796f89071fb35c8e222ef93069
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I2ba6f07aa2568c6abf20d6c92ec26bc97f4acdbb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40198
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I90a3b2384797a15d5ac7f3cf9df808a5cfb1dc8c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40178
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: If85e246550abe323d6a2a7c6301e8e91858cbe3a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I34bd5147bc1763416f8c875828cd6ee5c2a465ac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40174
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I1d42341e9cf5e35142f9cc8e97a03e442655bc13
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I3c90ef02041799954aa656924df8c07325b83431
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: If2b94a05ccbb3bead292713719fdc914d96dbd0f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I377eb446b42d9427be9884f8bea4de6cbd8addcd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I5dd216564e66ba14207308a4606d53a1dd813076
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I8bd5b9621d85dbb08996653c0f66e528f85ba0b0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I2de1d93070abcfe3ee9926e5798a8a7b187c1351
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Ic650486d036d06d5df46e41826d38bb9b8e92ed1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I1122cdc74a71be6d108998fe7027033394ed6459
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I90a2643e8d2346cd634266af3d7b2dfc7e20bf2d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: If78d4f1715f91671b3fb9557a8c5dfbc46bb07a5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Ie7a2074c2319911395234e4ce8ec35b8209bcc01
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I890c2367799196e0b9f986d95bcda1d9090a694d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Enables backlight control under Windows.
Test: build/boot eve, verify screen backlight controls
available and functional under Windows 10.
Change-Id: Id4477d2ec71aefb4c9d2ead31cd5fd3bfad51981
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Enables ACPI backlight controls under Windows.
Test: build/boot chell variant, verify screen backlight
controls available and functional under Windows 10.
Change-Id: Ida0102ac828254ae195528a8f1de078abed4a491
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Enables ACPI backlight controls under Windows.
Test: boot Win 10 on cyan and edgar variants, verify
screen backlight controls available and functional.
Change-Id: I8976291b5bafaec934d0bfd91fcdab50b381beec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
All variants except NINJA have a built-in display.
Enables ACPI brightness controls under Windows.
Change-Id: I8dd026608de606fa33f28ccb2967f3beb83b3470
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Test: build/boot lulu and samus variants, verify backlight
control functional under Windows 10.
Change-Id: I4725fdea5206ae03df14a8b07e51fdf09f1edebd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Disable SoC serial output by default, since no production devices
have this exposed, but leave it as a user option so it can be selected
as needed (eg, for use with a Google debug servo).
Same change as made for google/cyan in CB:39872
Change-Id: Id6b2c28658aca03d8c5042d719a0f6f504c29288
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Since the variants' devicetrees are almost identical, convert to
using an overridetree setup for simplicity.
Change-Id: I52b71cf12a4e0b67135cfb106c3e89b00205d3bc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39996
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The jack detect GPIOs are initialized as dual edge-triggered GPIs,
and Linux doesn't care if they are set to ActiveLow, ActiveHigh, or
ActiveBoth -- a single interrupt is detected on jack insertion or
removal.
The Windows drivers on the other hand, will not function unless the
codec and LPE ACPI interrupts entries are set as in the Intel
Cherry Trail Tianocore platform reference code.
So adjust the ACPI interrupt triggers to make Windows happy, since
Linux doesn't care either way.
Test: boot Linux (GalliumOS 3.1) and Windows 10 on google/edgar,
observe functional audio output for both built-in speakers and
headphones.
Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/24989
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Adjust CID to allow for Realtek's Windows drivers to attach
without breaking functionality under Linux.
Both Linux and Windows use ACPI HID/CID matching for driver attachment.
Since the Realtek 5650 isn't used in standard Windows laptops, the
'10EC5650' HID/CID isn't contained in the Windows drivers' lookup file
(.inf), but a catch-all 'INTCCFFD' entry does exist, so concatenate
that to the existing CID to allow the drivers to attach.
Test: build/boot google/edgar, verify working audio under
both Windows 10 (with Realtek drivers 10.0.10586.4393) and Linux
(GalliumOS 3.1 / kernel 4.16.18, Manjaro 18.1 / kernel 5.1.x)
Change-Id: Idca5cc86ba1f5ef3978cfba291a0c06e56ef5958
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40003
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Braswell boards don't work well with the eMMC and SD controller
in ACPI in payloads other than depthcharge - SeaBIOS requires
an onerous workaround (manually determining the PCI BAR0 address
for each eMMC and SD controller, then adding adding etc/sdcard
entries to the CBFS), and Tianocore can't see the devices at all.
To make the common use-case work better, switch to PCI mode.
Test: build/boot cyan variants with SeaBIOS and Tianocore
payloads, verify eMMC and SD card visible and bootable to
both payloads and OSes.
Change-Id: I71947603e22a37fe2c8ef4eaac8a3aa0d0ed1cec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40002
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Simply cyan variants by converting to overridetree format.
A few differences were ignored as there appears to be no
reason behind them:
- cyan had PCIe RP2 enabled, but nothing is attached to it
- kefka had the SPI 1 device disabled
- reks, relm, and ultima had HSUART 1 disabled
- edgar had I2C1 UPD disabled
Test: build/boot cyan and edgar variants, verify everything
still works
Change-Id: I9928cc59adcfda4661ddfdfa95f53a7820053b4a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39964
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Simplify glados variants by converting to overridetree format.
Change-Id: I6dd7a4b1ae7f1d3ce9fadb06ea95e021a1c880a5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39983
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The VR config values used in the variants' devicetrees is
identical to the domain defaults in vr_config.c, with the
exception of the icc_max value, which is calculated dynamically
based on SKU, and again matches the default values for
each domain and each varaint.
Test: add a print function to dump the VR config values for each
domain from the UPDs after setting, verify same output before/after.
Change-Id: I4307f6e19ae6f99d4f5e475b181fd66c5b92f28c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39982
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In preparation for conversion to overridetree format, clean up
the variant devicetrees in order to minimize the differences
across glados variants. This entails:
- minor reformatting and reordering of devicetree entries
- addition of setting default values on boards which skipped them
- disabling unused I2C2 on boards which left it enabled
- ensuring TCC offset set for all SKL-Y boards
- setting VR mailbox command 1 for caroline
- skipping init for UART2 on cave and glados
- dropping unused PCIe RP5 for sentry
Change-Id: I628b20a69fab187e67901c9eb98c0e2ddcb76b0d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39981
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Since the variants' devicetrees are almost identical, convert to
using an overridetree setup for simplicity.
As part of the cleanup, drop unused PCIe RP5 for buddy as well.
Test: build all auron variants, compare generated static.c to ensure
resulting generated contents unchanged (although layout will)
Change-Id: I290e7243335a64afdcfc629db7b8ce18f5aa993c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
beltino variants are Chromeboxes without built-in displays,
so now that default_brightness_levels.asl is no longer required
for all boards in a platform, drop it.
Change-Id: Ie8147763fc9fdf4f184d3d000bffd6794e134d9e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: Ie7eb4c43178acff2dc5ff7c685e71990d8f353c9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
These two identifiers were always very confusing. We're not filling and
injecting generators. We are filling SSDTs and injecting into the DSDT.
So drop the `_generator` suffix. Hopefully, this also makes ACPI look a
little less scary.
Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: David Guckian
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change reorganizes memory initialization code for LPDDR4x on
TGL to allow sharing of code when adding support for other memory
types. In follow-up changes, support for DDR4 will be added.
1. It adds configuration for memory topology which is currently only
MEMORY_DOWN, however DDR4 requires more topologies to be
supported.
2. spd_info structure is organized to allow mixed topologies as well.
3. DQ/DQS maps are organized to reflect hardware configuration.
TEST=Verified that volteer still boots and memory initialization is
successful.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib625f2ab30a6e1362a310d9abb3f2051f85c3013
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
This commit creates a malefor variant for Volteer. The initial settings
override the baseboard was copied from variant ripto. Fine tune GPIO
and memory DQ based on malefor schematics.
BUG=b:150653745
BRANCH=volteer
TEST=emerge-volteer coreboot
Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com>
Change-Id: Idbeebb13e537287686344740211143df35b7863a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39857
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch adds GOOGLE_LAZOR which is just a copy of GOOGLE_TROGDOR for
now.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I0dca8e1c29bdd91625d58b3cb583b530ed925e9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
|
|
This implementation removes all JSL references from the TGL SoC code.
Additionally, mainboard code changes are done to support build.
BUG=b:150217037
TEST=build tglrvp and volteer
Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop
referring from soc/intel/tigerlake.
Addtionally mainboard changes are done to support build.
BUG=b:150217037
TEST=Build and boot waddledoo. Build jasperlake_rvp and volteer board.
Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Since the variants' devicetrees are almost identical, convert to
using an overridetree setup for simplicity.
Test: build all slippy variants, compare generated static.c to ensure
resulting generated contents unchanged (although layout will)
Change-Id: If237fad38a1bccfb8e51edfae3ecb75d05ade240
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Clean up Link's mainboard dir by putting the SPD files in
a spd subdirectory like all other/newer boards use, and
selecting GENERIC_SPD_BIN to include them in the build.
Test: build google/link and verify spd.bin unchanged
Change-Id: I9c2f9f77dbdd6552c5ae1e7a0df2051b9b85badc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Link's DID data makes no sense, and ACPI backlight controls don't work
as a result. Replace them with the default profile used by most/all
other boards.
Test: build/boot google/link, verify ACPI backlight controls functional
Change-Id: Ia7cb3f10bd3c05ebaf414c17a8f94d2e9b40ae26
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Add an enable reset delay to avoid messages like this in the
kernel:
i2c_hid i2c-WCOM50C1:00: failed to change power setting.
This gets rid of all the warnings except one on reboot/shutdown.
That last case likely isn't fixed because the sleep command is
being sent directly from i2c_hid_shutdown(), so no ACPI routines
get to run and provide the delay. Since the machine is going down
for shutdown/reboot anyway, fixing that last case is a lower
priority.
BUG=b:145094539
TEST=Run on kohaku, switch to guest mode and log out, no errors
Signed-off-by: Evan Green <evgreen@chromium.org>
Change-Id: I8fadf497dd09e5b95b1d74443fb0543d3555dbb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This initial devicetree attempts to correctly configure the status of
each PCI device. Not all required drivers are instantiated, nor are
all of the SoC options fully selected yet.
PCIe root ports are enabled and clocks are assigned.
USB ports are assigned.
BUG=b:150165131
BRANCH=none
TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I911ec08b0db3647d131113a138fb74a55612fd62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
This configuration sets up all of the GPIO pads for the first rev of
the board.
BUG=b:150165131
BRANCH=none
TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Created a new Google baseboard using Tiger Lake named deltaur, taking
volteer as a starting point.
BUG=b:151102807
TEST=make build successful
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib98f328df22f39e7d9d625a3292954881ee15b15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
In order to create a working baseline all ports are being set to have
retimers. Setting the TcssAuxOri UPD to 0 in order for the SoC to not
misconfigure the ports. Volteer will need some additional changes after
this is implemented to account for ports that do not have a retimer.
This setting is in the process of being documented in the TGL EDS and we
can update once it is fully understood what this setting is changing on
the SOC side.
BUG=b:145943811
BRANCH=none
TEST=Boot to OS and check Type-C port1 Display on Volteer,
Connecting Type-c display should work regardless of Type-c cable
orientation.
Change-Id: I29eb0513299126ad8d1ee11ded2c771f28ad13f3
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39460
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
