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2021-03-14mb/google/guybrush: Enable PCIe devices in devicetreeMathew King
BUG=b:181690884 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I8ceeb8db24be34588b370c13d865753f095e4be6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-14mb/google/guybrush: Add SPDs into buildMartin Roth
This enables the standard library method of adding SPDs to CBFS. BUG=b:178715165 TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I2ec94fd866409e1dfa5cb65f6960ea07cbe22f2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51022 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-14mb/google/guybrush: Enable EM100 support on guybrushMathew King
Add the option to build guybrush firmware with support for EM100. This will assist in bringup of the new board. BUG=b:180723776 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I2246d2952f341cd8fff8fd486cf989cdb7929411 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51071 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/amd/majolica,google/guybrush,google/mancomb: select HAVE_ACPI_RESUMERaul E Rangel
Since not all mainboards based on the Cezanne SoC have to support ACPI resume, select this option in the mainboard's Kconfig and not in the SoC's Kconfig. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I988276ccb5b61837d7f3f015d1d1aba783324b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/google/guybrush: Add guybrush APCBs into buildMartin Roth
This adds the Guybrush APCBs into the AMD firmware binary. BUG=b:182510885 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iba40cab1d68e9f8d7291e7d715be185a3b6249f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-13mb/google/guybrush: Add ACPI support for Chrome ECMathew King
BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Icb8aba87390475cad7a2a9911c3832a59c987b65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-13mb/google/guybrush: Configure eSPI GPIOs in early stageMathew King
BUG=b:181961514, b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I0d22de977f09cbf46b28243d9f0c1e9a36e1398f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51295 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/google/guybrush: Configure early GPIOs in earliest stageMathew King
Configure early GPIOs in verstage if it is run in PSP otherwise configure them in bootblock. BUG=b:181961514, b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ib9410089592776ffe198901f2de914fd04bdbade Reviewed-on: https://review.coreboot.org/c/coreboot/+/51348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-13mb/google/guybrush: Enable verstageMathew King
BUG=b:181961514 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I289a2ad1adc5dcc33c5863d6138f66b9b6dc6590 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-12mb/google/dedede/var/boten: Increase Goodix touchscreen reset delay to 180 msStanley Wu
1. Follow GT7375P Programming Guide_Rev.0.6 to increase reset delay to 180ms. 2. Add TOUCH_RPT_EN pin(GPP_A11) control to fix TOUCH_RPT_EN pin keep high after system suspend. BUG=b:181711141 TEST=Build and boot boten to OS. Confirm TOUCH_RPT_EN pin keep low after system suspend. Change-Id: I98efbe68dab538906802647582eba0e068d9c11f Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51254 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12mb/google/dedede/var/boten: Configure I2C5 p-sensor high and low timeStanley Wu
Configure I2C bus 5 high and low time for p-sensor device. BUG=b:181727056 TEST=Measured the I2C bus frequency reduce to 387 KHz. Change-Id: I4b6d78d84b8ea145093f52bbb13684e2c6aa979c Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-12soc/intel/braswell: Factor out common `acpi_fill_madt`Angel Pons
Function is identical for all mainboards, so factor it out. Change-Id: Ibe08fa7ae19bfc238d09158309f0a9fdb31ad21c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50028 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12mb/google/dedede/var/boten: Adjust p-sensor detect distance to 20mmStanley Wu
P-sensor vendor fine-tune detect distance as 20mm for WWAN SAR table switch. BUG=b:179000150 BRANCH=dedede TEST=run "i2cdump -y -f 15 0x28" to confirm registers as expected. un-approach： => register address: 0x01 value: 0x00 approach: => register address: 0x01 value: 0x02 Confirm WWAN SAR table work as expected. Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I659721e60aa0766ed4c277dae43ded222e18ad1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51343 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11mb/google/mancomb: Add eSPI configurationEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie3a3bb7526d734ae1936b8c4db43543b1174829d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11mb/google/mancomb: Enable mancomb variantEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I554e7193494a4bbf005aaf2fb4efd6ded383fe07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11mb/google/mancomb: Enable console UARTEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia03169c524dd12b8e7803ea8039c0e98a2b069e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11mb/google/mancomb: Enable ACPI tablesEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I623fd052404a08cf0adb471bb654622960f1aa62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11mb/google/mancomb: Enable CONFIG_CHROMEOSEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I45dcaa8b430721f864d4e5d78ae60883175085c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11mb/google/mancomb: Add stubs to configure GPIOsEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7de5e4a4d2273d0ea5a84210ea0ce28d312eaa95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11mb/google/guybrush: Enable USB ports in devicetreeMathew King
BUG=b:180529005 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I94d97a38d992f46b32c2c6aca4c8da688d3b76fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51257 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11mb/google/guybrush: Enable Chrome EC SKUID and BOARDIDMathew King
BUG=b:181910592 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I7851d3b11ea3b026b999019d02df1144f8393753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-11mb/google/guybrush: Log mainboard events to elogMathew King
BUG=b:180653357 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ifd43d9cc1832d8ed8d90c68ba88b5667e3c04f89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-10mb/google/guybrush: Add chomeec device to lpc bridgeMathew King
BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I7b8b2ab73d66e0aaa0e9b7570661c885f7f777ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/51296 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10mb/google/zork/var/shuboz: support regular/numpad touchpadKane Chen
Define the 26th bit of the fw_config for the regular touchpad and numpad touchpad selection. REGULAR_TOUCHPAD: 1 NUMPAD_TOUCHPAD: 0 BUG=b:174964012 BRANCH=zork TEST=build pass Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ie2055d6bb45a64bc0e59209cecc0f8a31c0f3718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-10mb/{amd/padmelon,google/zork}: Do not select `VGA_BIOS`Angel Pons
The VGA BIOS for AMD Padmelon and Google Zork are stored in `amd_blobs`. Do not force inclusion of VGA BIOS when `USE_AMD_BLOBS` is not enabled. Change-Id: I206e8fadc14ec0d9b162dc4d72813fdd3d43958b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-10mb/google/zork/var/shuboz: adjust I2C2 data hold time for TPKane Chen
Add ".data_hold_time_ns" to follow I2C specification. The adjusted result aobut 0.315us(more than 0.3us) BUG=b:181091107 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Id92fadcb54b9722709e32ced1f0be001b8c97975 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-10mb/google/zork: Use SOC defines instead of magic numbersMathew King
BUG=b:182269526 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I351fb4fc493bb92b31e2c8bc946dfb048045335c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-10mb/google/zork/var/vilboz: Add Mainboard Type for VCORE ICJohn Su
To define Mainboard Type config, use the fw_config bit[26]. Check MB Type to modify SDLE settings for different VCORE IC. BUG=b:177193131 BRANCH=zork Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/49683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-10mb/google/zork: add UPDM updating function before runing FSP-MChris Wang
Add the UPD updating hook in early stage for customization. BUG=b:117719313 BRANCH=zork TEST=build,check the hook function been executed. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I4954a438a51b29b086015624127e651fd06f971b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51181 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10drivers/i2c: sx9310: Replace register map with descriptive namesGwendal Grignou
The current driver is using chip registers map to configure the SAR sensor, which is opaque, especially when the datasheet is not published widely. Use more descriptive names, as defined in Linux kernel documentation at https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/proximity/semtech%2Csx9310.yaml BUG=b:173341604 BRANCH=volteer TEST=Dump all tables, check semtech property: for i in $(find /sys/firmware/acpi/tables/ -type f) ; do f=$(basename $i); cat $i > /tmp/$f.dat ; iasl -d /tmp/$f.dat done In SSDT.dsl, we have: Package (0x06) { Package (0x02) { "semtech,cs0-ground", Zero }, Package (0x02) { "semtech,startup-sensor", Zero }, Package (0x02) { "semtech,proxraw-strength", Zero }, Package (0x02) { "semtech,avg-pos-strength", 0x0200 }, Package (0x02) { "semtech,combined-sensors", Package (0x03) { Zero, One, 0x02 } }, Package (0x02) { "semtech,resolution", "finest" } } Change-Id: I8d1c81b56eaeef1dbb0f73c1d74c3a20e8b2fd7b Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-10mb/google/guybrush: Add smihandlerMathew King
BUG=b:180507707 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I25ce0ca869ca854ff33242d2c416319e9688cc6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51264 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10mb/google/guybrush: Enable Chrome ECMathew King
BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I3cdd6422b1bc53ea934346327359cbc6d86baeeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/51043 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-09mb/google/brya: Define ChromeOS GPIO support in ACPI tbalesTim Wawrzynczak
Define the ChromeOS GPIOs (physical write-protect and virtual recovery mode) in ACPI tables so the OS knows which physical pad is used for them. BUG=b:181887865 TEST=flashrom_tester is able to "see" the WP GPIO Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I3feed366afd6507894a1d31304891cc785a4d314 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51347 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-09mb/google/brya: Reorganize flashmapTim Wawrzynczak
Intel ADL-P supports an additional memory-mapped 16MiB window into the platform SPI flash. Support for this window already exists at the SoC level, so all that is needed is to properly organize the flash map to take advantage of this. FW_SECTION_A moves down to the bottom of the available space in the lower 16MiB half, and FW_SECTION_B moves to the bottom of the top 16MiB half. RW_LEGACY is squashed down to 2M. BUG=b:182088676 TEST=build and boot to OS from FW_MAIN_A Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I60483b7e638c0a7e41f1f7e2b5503ae02e9906bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/51345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-09mb/google/asurada: Enlarge CONSOLE_CBMEM_BUFFER_SIZEYu-Ping Wu
Enlarge CONSOLE_CBMEM_BUFFER_SIZE from 128K (default) to 512K, so that more DRAM calibration logs can be stored in CBMEM console. BUG=b:181933863 TEST=emerge-asurada coreboot TEST="cbmem -c" shows the whole full calibration log BRANCH=none Change-Id: If82cbee5d2d5e97d98cbdaecda739d91a7cca0f8 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51275 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-09mb/google/octopus/var/fleex: Only check LTE sku on fleexEric Lai
Fleex has other project share the same FW. Only fleex has LTE sku. So we need to make sure it is fleex then check if LTE sku. BUG=b:181946744 BRANCH=octopus TEST=Check no SAR table can be loaded with sku id 4 and 5. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9f3d5fed4315fc716acad1a07735221d154c377e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Henry Sun <henrysun@google.com>
2021-03-08soc/amd,mb/google/,mb/amd: Move sleepstates.aslRaul E Rangel
This file is common for all the AMD platforms. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I10ee600b4bcd7aaff39bfab075eb4dbc9096b435 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51299 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-08mb/google/guybrush: Enable internal graphicsMathew King
BUG=b:181809122 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I64475a475e9b72a6edd04ce0728591e0649d9f60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-08mb/google/brya: Add Board and SKU ID support from Chrome ECTim Wawrzynczak
BUG=b:180456030 TEST=`mosys` is able to detect the platform correctly Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ifbaa4a380bdb546bb54d579b46fe5760b2f4b754 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-03-08mb/google/brya: Finish support for ChromeOS GPIOsTim Wawrzynczak
BUG=b:181887865 TEST=`crossystem` shows correct state of WP signal when toggled Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If49ca1d70cc36ab74d70e858336679c0a9a3258e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-08mb/google/asurada: Add generic DRAM groupsXi Chen
To reduce qualification effort, we want to pre-populate DRAM by their size, package type and geometry so when a new DRAM is introduced we don't need to spin off a new firmware release. Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I42ee170c159e551e840ab4e748f18f5149506b4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-08mb/google/kukui: Add Micron 4GB discrete LPDDR4X DDR supportJessy Jiang
Support 4G+128G MT29VZZZAD9GQFSM-046 W.9S9 discrete DDR bootup. BUG=b:162292216 BRANCH=kukui TEST=Boots correctly on Kukui. Signed-off-by: Jessy Jiang <jiangchao5@huaqin.corp-partner.google.com> Change-Id: I5657a007154bc52c6f0f27e1de6e3294a5e74ad7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-06mb/google/brya: Move GPE configuration to baseboard/devicetree.cbFurquan Shaikh
This change moves GPE configuration from brya0/overridetree.cb to baseboard/devicetree.cb since all variants will end up using the same configuration. TEST=Verified using "abuild -p none -t google/brya -b brya0 --timeless" that coreboot.rom generated with and without this change is the same. Change-Id: Ie31bf2bf8a91da82fca77c78fb0a735a2645de55 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-06mb/google/brya: Fix MAINBOARD_PART_NUMBERFurquan Shaikh
This change updates MAINBOARD_PART_NUMBER string to use uppercase for first character. This matches what all others boards do. BUG=b:180456030 Change-Id: I10eaeef5ec662a5718b787a3f0e3705cf70d751d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51297 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-05soc/intel/adl, mb/google/brya: Add IPU to devicetreeTim Wawrzynczak
BUG=b:181843816 Change-Id: I25309a8f0900070a8307fbce90ccb6d47f9c3dfc Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51261 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-05mb/google/brya: Add IPU ASL to DSDTTim Wawrzynczak
BUG=b:181843816 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I74246cd0d2f866022604ec3e8a8d523c273cdef4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-05mb/google/brya: brya0: Add ACPI support for Type-C portsTim Wawrzynczak
BUG=b:181160586, b:181843816 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic201ad047fd0d593749d2b993f843f7e188a5c98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51258 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-05mb/google/volteer: Configure tcss port information for early tcss initBrandon Breitenstein
Implement the mainboard_tcss_get_port_info weak function so that the TCSS muxes can be properly configured to ensure mapping is correct in mux. This ensures that any devices that are connected during boot are not improperly configured by the Kernel. BUG=b:180426950 BRANCH=firmare-volteer-13672.B TEST= Verified that the SOC code that initialized TCSS muxes to disconnect mode is executing properly for all TCSS ports and verified that USB3 devices are no longer downgrading to USB2 speed if connected during boot. Change-Id: I59e5c5a7d2ab5ef5293abe6c59c3a585b25f7b75 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-05mb/google/dedede/var/blipper: Generate SPD ID for supported memory partsZanxi Chen
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR H9HCNNNBKMMLXR-NEE BUG=None TEST=Build the blipper board. Change-Id: Ia7e4c1d5c06013c1902816d6dcafb5a8a0386bb3 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-05mb/google/zork/var/vilboz: Update telemetry settingsJohn Su
Update telemetry settings for vilboz. VDD Slope : 26939 -> 27225 VDD Offset: 125 -> 187 SOC Slope : 20001 -> 26559 SOC Offset: 168 -> 89 BUG=b:177162553 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Iaf7c5083c4c5affec5ae0b5583efb5237e10d0ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/51165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: chris wang <Chris.Wang@amd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2021-03-05mb/google/volteer: Fix FPMCU pwr/rst gpio handlingNick Vaccaro
1. No gpio control in bootblock 2. Power on and then deassert reset at the end of ramstage gpio 3. Disable power and assert reset when entering S5 On "reboot", the amount of time the power is disabled for is equivalent to the amount of time between triggering #3 and wrapping around to #2. This change affects the following volteer variants that include an FPMCU: 1. Drobit 2. Eldrid 3. Elemi 4. Halvor 5. Malefor 6. Terrador 7. Trondo 8. Voema 9. Volteer2 10. Voxel BUG=b:178094376 TEST=none Change-Id: Ib51815349cea299907c10d6c56c27bd239e499e7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-04mb/google/volteer/variants/copano: Describe USB ports in devicetreehao_chou
Modify USB port to match schematics. And assigned USB2 port to type-c use. BUG=b:177481079 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Change-Id: I25412d16df8ad809c05635022c11bd8882d002c5 Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49980 Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03mb/google/zork/var/vilboz: Update WiFi SAR for VilbozFrank Wu
Loading wifi_sar-vilboz-1.hex for vilboz360 LTE sku for the present. BUG=b:177684735, b:176168400 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are in CBFS and loaded by iwlwifi driver. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I477b55d64fd9d33d753b10b2de443041a12d13e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-03mb/google/brya: Add support for 2 new DRAM partsAmanda Huang
1) Micron MT53E1G32D2NP-046 2) Micron MT53E2G32D4NQ-046 BUG=b:181378727 TEST=none Change-Id: I413e35cdb7c34388c3e159f8f9584fae2d21a355 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03mb/google/brya: fix BT enumeration issueAamir Bohra
Current implementation exposes GPP_F4 cnvi reset pin as reset gpio instead of GPP_D4(BT_DISABLE_L). GPP_F4 is native and driven by SoC. It should not be driven by driver. BUG=b:180875586 Change-Id: I589fc2b55ee2947cc638fe17540bbd24f5bfb8f4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51178 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03soc/intel: Retype `CnviBtAudioOffload` devicetree optionAngel Pons
The `FORCE_ENABLE` and `FORCE_DISABLE` names do not match what FSP UPDs say, and can be confused with the `PchHdaTestPowerClockGating` UPD. Replace the enum with a bool, and drop the confusing names. Note that the enum for Ice Lake was incorrect, but no mainboards used the option. Change-Id: I2c9b4c6a2f210ffca946ca196299fa672a06ccc7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51154 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03mb/*/*: Don't select PCIEXP_HOTPLUGArthur Heymans
PCIEXP_HOTPLUG has a prompt and as such is not supposed to be forced. Just change the default value to 'y'. Change-Id: Ie4248700f5ab5168bff551b740d347713273763c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03mb/google/dedede/var/drawcia: Re-tune override GPIO tableKarthikeyan Ramasubramanian
There is going to be an upcoming board version for Drawlat/man and Drawcia. Hence apply the override GPIO table without pad termination for board versions 6 or 8 alone. BUG=None BRANCH=dedede TEST=Build and boot to OS in Drawcia. Change-Id: I320de9a0c37ac033f3efda74eeb8f36e34667fd4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-03-03mb/google/guybrush: Add SPDs to build for Guybrush variantMartin Roth
These files were automatically generated by the lpddr4 version of gen_part_id.go. BUG=b:178715165 TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I3797ba6d52248961418000614a4f7885182521a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03mb/google/guybrush: Add generated LPDDR4x SPDsMartin Roth
These SPDs were generated by the lpddr4 version of gen_spd.go from the global_lp4x_mem_parts.json.txt file. BUG=b:178715165 TEST=None Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I7b9bd04534d6e45dbfe10a0028052978ef3d7c17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-02google/trogdor: Fix trogdor-rev1 eDP power GPIOJulius Werner
Looks like I forgot about trogdor-rev1 in CB:51004. Unlike rev0 (other special case) or rev2 (works like CoachZ/Homestar), rev1 used the same pin as Lazor and Pompom for EN_PP3300_DX_EDP. Apparently there are still some people using these, so add in another special case for that. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I7093aa63778d69fde240af3b0c62b97ac99c28dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51196 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02mb/google/guybrush: Set up FW_CONFIG fieldsMathew King
BUG=b:180523962 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ic8f30f6d7c4781d4e8451546b39395a74393608f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-02mb/google/guybrush: Add eSPI configurationMathew King
BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ic607d6bca5c70255332a6fbee2b63e6daba7d1e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51047 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02mb/google/brya: Fix a few mistakes in brya0 overridetreeTim Wawrzynczak
1) Both SAR sensors had a UID of `2`, making them indistinguishable 2) No `device` underneath max98357a `chip` Change-Id: Icf586229532819a7779652cbee73755b036dfbdc Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51145 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02mb/google/guybrush: Add option to toggle GPIO for sign of lifeMathew King
Enabling the GPIO_SIGN_OF_LIFE option will allow for early boot testing. BUG=b:180721202 TEST=builds Change-Id: I069623ae76a4e4d1e43a47dd95fdfcece398ebfb Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-01soc/intel/skylake: Clean up SD GPIO handlingAngel Pons
This is to align with newer platforms. Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01mb/google/zork/var/shuboz: Decrease I2C3 CLK below 400 kHzKane Chen
Modify I2C3 setting to follow I2C specification (lower than 400kHz). Original setting: .rise_time_ns = 184 .fall_time_ns = 42 Change to: .rise_time_ns = 110 .fall_time_ns = 34 BUG=b:181091107 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ibdbb9a7dde524bdbde4789ee7ea005646080d97a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-03-01mb/: Drop print of MAINBOARD_PART_NUMBERKyösti Mälkki
Change-Id: Ie3870bc666acaea316f00b205de512cf790e720c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-03-01mb/google/dedede/var/sasukette: Configure I2C times for touchpad/codec/AMPTao Xia
Configure I2C high / low time in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (400 kHz). Measured I2C frequency just as below after tuning: touchpad:372 kHz audio codec RT5682:386.8 kHz speaker AMP L:387.5 kHz speaker AMP R:388.9 kHz BUG=b:181342340 BRANCH=dedede TEST=Build and check after tuning I2C clock is under 400kHz Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I05d78c088190e349281a34b2aeed39ae8d867dc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51112 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01mb/google/dedede/var/storo: Enable ELAN touchscreenchenzanxi
Add ELAN touchscreen into devicetree for storo. BUG=b:177389448 BRANCH=dedede TEST=built storo firmware and verified touchscreen function Change-Id: I0d9e5005928c6fda3d1f0ce8bd9ae135e4a04867 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50981 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27mb/google/dedede/var/kracko: Add elan touchscreen supportTony Huang
BUG=b:177834652 BRANCH=dedede TEST=build kracko firmware Change-Id: I360920f80f4ce5dcbcde25c433e23803fa72569b Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-27mb/google/brya: add HAS_RECOVERY_MRC_CACHE flagEric Lai
Brya’s chromeos.fmd contains a region for RECOVERY_MRC_CACHE, but does not select HAS_RECOVERY_MRC_CACHE, so it’s unused. BUG=b:174266035 TEST=Check MRC cache can allocate in recovery mode. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I6b83eec3dcf27bafde610a701e55f1371a5d4571 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51081 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27vboot: update GBB flags to use altfw terminologyJoel Kitching
As per CL:2641346, update GBB flag names: GBB_FLAG_FORCE_DEV_BOOT_LEGACY -> GBB_FLAG_FORCE_DEV_BOOT_ALTFW GBB_FLAG_DEFAULT_DEV_BOOT_LEGACY -> GBB_FLAG_DEFAULT_DEV_BOOT_ALTFW BUG=b:179458327 TEST=make clean && make test-abuild BRANCH=none Signed-off-by: Joel Kitching <kitching@google.com> Change-Id: I0ac5c9fde5a175f8844e9006bb18f792923f4f6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-26mb/google/volteer/var/elemi: Configure IRQ as level triggered for elan_tsWisley Chen
Follow elan's suggestion to configure IRQ as level trigger to prevent touchscreen lost BUG=b:180778934 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I3aca0ad20791c989dec9e70d69d637b28c9cc043 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50417 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-26mb/google/volteer: add variant_ramstage_init()Nick Vaccaro
Add a weak variant routine to allow variants to perform any needed initialization in ramstage. BUG=b:178094376 TEST=none Change-Id: I65dc1cdf15b68d9f2239e02fcb4b2c902d749378 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50827 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-26mb/google/dedede/var/boten: route GPP_E11 via APICStanley Wu
GPP_E11 should be configured to be routed via APIC to avoid p-sensor communication error in OS. BUG=b:178465379 BRANCH=dedede TEST=run "i2cdump -y -f 15 0x28" to confirm registers as expected. un-approach： => register address: 0x01 value: 0x00 approach: => register address: 0x01 value: 0x02 verify sx932x IRQ in "/proc/interrupts" loading as expected. Change-Id: I7d639ec1f9b31b240475dc1c8025bf59ae1e8e0b Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50876 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-26mb/google/dedede: Create blipper variantchenzanxi
Create the blipper variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:179648964 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_BLIPPER Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com> Change-Id: I8e67521bd9ab05c257cb3d5d5d4cf506f258bfa7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-26mb/google/trogdor: Add new configs homestarxuxinxiong
New boards introduced to trogodor family. BUG=b:180668002 BRANCH=none TEST=make Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Change-Id: If0f9b6c89198a882acae7191d08b166eb8c1dd71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-02-25mb/google/zork: restore stamp_boost parameter to 2500 for dirinbozKevin Chiu
Stamp_boost 1640 parameter is too short to keep APU performance. Restore parameter to 2500 then APU could have longer boost time (~3xxx sec) BUG=b:175364713 TEST=1. emerge-zork coreboot 2. run balance performance and skin temperature test => pass Change-Id: Ie08394d0b1a693f71336cb4cb6ce9528dfdce14b Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-25mb/google/volteer: Fix eldrid DPTF's passive and critical policiesTim Wawrzynczak
Because the entries were formatted differently to the baseboard, the devicetree overrides didn't work as intended, and all 5 entries from the baseboard were included, and then the overrides were applied, but the baseboard's entries were kept, so there were duplicate ACPI entries, which causes errors when parsing the table. Fixes: 5f30ae3714d ("mb/google/volteer: update thermal table for Eldrid") BUG=b:181034399 TEST=compile, verify static.c is correct now Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I32fe2eae591ed4d3c08378977c463327f7ee1100 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51044 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-25mb/google/volteer/variants/drobit: Update DPTF parametersWayne3 Wang
Update the first version DPTF parameters. The TDP is down to 13w for acoustic concern. BUG=b:177777472 BRANCH=firmware-volteer-13672.B TEST=build test image and verified by thermal team. Change-Id: I36f016530a61e3660938ce8d2948bb3b0f275d88 Signed-off-by: Wayne3 Wang <Wayne3_Wang@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51030 Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-25mb/google/dedede/var/galith: Update DPTF parametersFrankChu
Update the first version DPTF parameters received from the thermal team. BUG=b:177628854 TEST=cros build-ap --debug -b dedede --fw-name galtic Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ia8e76d303db0add95e77693f15cad108fa92303b Reviewed-on: https://review.coreboot.org/c/coreboot/+/49480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-25mb/google/asurada: Enable RTC for event logYu-Ping Wu
BUG=b:177399759 TEST=firmware_EventLog passed on asurada BRANCH=none Change-Id: I759f9030f525fa9e34ed542198a9dba8f25909f5 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-02-24mb/google/dedede/var/storo: Enable ELAN touchpadchenzanxi
Add ELAN touchpad into devicetree for storo. BUG=b:177393444 BRANCH=dedede TEST=built storo firmware and verified touchpad function Change-Id: I95780d23b9ea5425d7762e850c25fd14d8a9caf4 Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50979 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24mb/google/dedede/var/lantis: Configure IRQ as level triggered for ELAN TSTony Huang
Follow vendor suggestion to configure IRQs as level triggered to prevent TS lost. BUG=b:171440909 BRANCH=dedede TEST=1. emerge-dedede coreboot chromeos-bootimage 2. power on, suspend DUT to check TS is functional Change-Id: I07a5cd5e2ac9caad9dbcca12e05bda7f08f42dce Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-24mb/google/dedede/var/sasukette: Adding LTE module support into devicetree andTao Xia
associated GPIO configuartion Adding LTE module support into devicetree and associated GPIO configuartion. BUG=b:177385043 BRANCH=dedede TEST=LTE function is OK Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I4d91045176fd6413ac6a5eed70289a5668e5b94f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-24mb/google/dedede/var/sasukette: Adding audio codec andTao Xia
speaker amplifier support into devicetree Adding audio codec and speaker amplifier support into devicetree BUG=b:177479444 BRANCH=dedede TEST=audio function is OK Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I90ff3a107278c711a085d04ae708e41f95d454ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/50984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-24mb/google/dedede/var/sasukette: Adding Touchpad support into devicetreeTao Xia
Adding Touchpad support into devicetree. BUG=b:177348842 BRANCH=dedede TEST=touchpad function is OK Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I7ecafb5b3e39ff2ed9e176531bd0939f830a6397 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-24mb/google/dedede/var/sasukette: Adding camera support in devicetreeTao Xia
and associated GPIO configuration Adding camera support in devicetree and associated GPIO configuration. BUG=b:177351873 BRANCH=dedede TEST=camera function is OK Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I539e969e180c8c71d4b54b50519d2e1ff25415f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-24mb/google/dedede/var/boten: Configure GPP_G7 as nativeStanley Wu
Configuring GPP_G7 as NC causes SD card detection issue. Remove the GPP_G7 override and keep the baseboard configuration as native function (SDIO_WP). BUG=b:179733306 BRANCH=firmware-dedede-13606.B TEST=Built and verified Kingston 64G SD card operation on boten Change-Id: Ied319437de0e867ee9821d0151ff0c76834c4726 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-24mb/amd,google: Rename static functions to mainboard_enableKyösti Mälkki
Let's not have 7 boards of all use a different name for the .enable_dev function in mainboard chip_operations. Change-Id: I07f3569e6af85f4f1635595125fe2881ab9ddd43 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-24mb/amd,google/zork: Move init_tables() callKyösti Mälkki
The semantics of pirq_setup() from previous platforms was to only setup the global pointers for PIC and APIC tables, not to create or modify the tables themselves. Change-Id: Iaa7c31eed21432dc2b3fe6b32803bd2658fd5e2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-23mb/google/zork: update USB 3 controller phy Parameter for gumbozKevin Chiu
Recommendation from SOC to config IQ=8 for U3 port0, vboost for all U3 ports for passing ESD pin test. BUG=b:173476380 BRANCH=zork TEST=1. emerge-zork coreboot 2. run U3 SI/ESD pin test => pass Change-Id: I0e6414f686a995536a0fd8aa0f6f70e5a36718a3 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50992 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-23mb/google/zork: Adjust Gumboz H1 I2C CLKKevin Chiu
Adjust H1 I2C CLK: 404kHz -> 391 kHz BUG=b:179753353 BRANCH=zork TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully 3. measure i2c freq by scope is close to 400kHz Change-Id: Iedd47dd6fc4f7ac7f0aac480d63ddbdf85a84ec2 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-02-23mb/google/dedede: Export EC_IN_RW GPIO to payloadIan Feng
Set up EC_IN_RW GPIO in coreboot. BUG=b:180686277 TEST=Verified that EC_IN_RW signal is read correctly in depthcharge. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ic41012d3d4843dcab0f6dd9c28396cb9d5c49f08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-23mb/google/oak: Add new DRAM modules K4E6E304EC-EGCG-4GBxuxinxiong
Samsung K4E6E304EC-EGCG-4GB # 1011 BUG=b:179455694 BRANCH=oak TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge, update FW to DUTs,these DUTs can pass stress test under run-in. Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Change-Id: I02cc34157fd03edb7d715a23ed404abc40ef8ccc Reviewed-on: https://review.coreboot.org/c/coreboot/+/50978 Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-23mb/google/zork/var/shuboz: Adjust GPIO settingsKane Chen
1. GPIO_4 to NC BUG=b:179333669 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I4342b2beb7fc755bee47ee4fad0023d7a6592c4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/50277 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22mb/google/brya: Fix chip driver and HID for Cr50 TPMTim Wawrzynczak
ChromeOS does not compile in CONFIG_OF, so PRP0001 will not successfully register the device with its driver. Change to GOOG0005 to match other ChromeOS devices with I2C-connected Cr50 TPM. BUG=b:180657076 TEST=abuild Change-Id: Ic1d4eb5e12ea7f7e693f1ffd3848e59668ac2deb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50920 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22mb/google/guybrush: Enable console UARTMathew King
BUG=b:180530492 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I468d76d0e061431bc819ec12978203614bfe72b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50919 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22mb/google/guybrush: Enable guybrush variantMathew King
Enable the building of guybrush variants and configure the first variant also called guybrush. BUG=b:180419462 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I3bed620378f9152277b4943ead1017f61a21ea82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50845 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 14:40:01 +0000