| Age | Commit message (Collapse) | Author |
|---|
|
To reduce qualification effort, we want to pre-populate DRAM by their
size, package type and geometry so when a new DRAM is introduced we
don't need to spin off a new firmware release.
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I42ee170c159e551e840ab4e748f18f5149506b4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Support 4G+128G MT29VZZZAD9GQFSM-046 W.9S9 discrete DDR bootup.
BUG=b:162292216
BRANCH=kukui
TEST=Boots correctly on Kukui.
Signed-off-by: Jessy Jiang <jiangchao5@huaqin.corp-partner.google.com>
Change-Id: I5657a007154bc52c6f0f27e1de6e3294a5e74ad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
This change moves GPE configuration from brya0/overridetree.cb to
baseboard/devicetree.cb since all variants will end up using the same
configuration.
TEST=Verified using "abuild -p none -t google/brya -b brya0
--timeless" that coreboot.rom generated with and without this change
is the same.
Change-Id: Ie31bf2bf8a91da82fca77c78fb0a735a2645de55
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This change updates MAINBOARD_PART_NUMBER string to use uppercase for
first character. This matches what all others boards do.
BUG=b:180456030
Change-Id: I10eaeef5ec662a5718b787a3f0e3705cf70d751d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51297
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:181843816
Change-Id: I25309a8f0900070a8307fbce90ccb6d47f9c3dfc
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51261
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:181843816
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I74246cd0d2f866022604ec3e8a8d523c273cdef4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
BUG=b:181160586, b:181843816
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic201ad047fd0d593749d2b993f843f7e188a5c98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51258
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Implement the mainboard_tcss_get_port_info weak function so that the TCSS
muxes can be properly configured to ensure mapping is correct in mux. This
ensures that any devices that are connected during boot are not improperly
configured by the Kernel.
BUG=b:180426950
BRANCH=firmare-volteer-13672.B
TEST= Verified that the SOC code that initialized TCSS muxes to disconnect
mode is executing properly for all TCSS ports and verified that USB3 devices
are no longer downgrading to USB2 speed if connected during boot.
Change-Id: I59e5c5a7d2ab5ef5293abe6c59c3a585b25f7b75
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
H9HCNNNBKMMLXR-NEE
BUG=None
TEST=Build the blipper board.
Change-Id: Ia7e4c1d5c06013c1902816d6dcafb5a8a0386bb3
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Update telemetry settings for vilboz.
VDD Slope : 26939 -> 27225
VDD Offset: 125 -> 187
SOC Slope : 20001 -> 26559
SOC Offset: 168 -> 89
BUG=b:177162553
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Iaf7c5083c4c5affec5ae0b5583efb5237e10d0ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: chris wang <Chris.Wang@amd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
1. No gpio control in bootblock
2. Power on and then deassert reset at the end of ramstage gpio
3. Disable power and assert reset when entering S5
On "reboot", the amount of time the power is disabled for is
equivalent to the amount of time between triggering #3 and wrapping
around to #2.
This change affects the following volteer variants that include an FPMCU:
1. Drobit
2. Eldrid
3. Elemi
4. Halvor
5. Malefor
6. Terrador
7. Trondo
8. Voema
9. Volteer2
10. Voxel
BUG=b:178094376
TEST=none
Change-Id: Ib51815349cea299907c10d6c56c27bd239e499e7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Modify USB port to match schematics.
And assigned USB2 port to type-c use.
BUG=b:177481079
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot
Change-Id: I25412d16df8ad809c05635022c11bd8882d002c5
Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49980
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Loading wifi_sar-vilboz-1.hex for vilboz360 LTE sku for the present.
BUG=b:177684735, b:176168400
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are
in CBFS and loaded by iwlwifi driver.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I477b55d64fd9d33d753b10b2de443041a12d13e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
1) Micron MT53E1G32D2NP-046
2) Micron MT53E2G32D4NQ-046
BUG=b:181378727
TEST=none
Change-Id: I413e35cdb7c34388c3e159f8f9584fae2d21a355
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Current implementation exposes GPP_F4 cnvi reset pin as reset
gpio instead of GPP_D4(BT_DISABLE_L). GPP_F4 is native and driven
by SoC. It should not be driven by driver.
BUG=b:180875586
Change-Id: I589fc2b55ee2947cc638fe17540bbd24f5bfb8f4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51178
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The `FORCE_ENABLE` and `FORCE_DISABLE` names do not match what FSP UPDs
say, and can be confused with the `PchHdaTestPowerClockGating` UPD.
Replace the enum with a bool, and drop the confusing names. Note that
the enum for Ice Lake was incorrect, but no mainboards used the option.
Change-Id: I2c9b4c6a2f210ffca946ca196299fa672a06ccc7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51154
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
PCIEXP_HOTPLUG has a prompt and as such is not supposed to be forced.
Just change the default value to 'y'.
Change-Id: Ie4248700f5ab5168bff551b740d347713273763c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
There is going to be an upcoming board version for Drawlat/man and
Drawcia. Hence apply the override GPIO table without pad termination for
board versions 6 or 8 alone.
BUG=None
BRANCH=dedede
TEST=Build and boot to OS in Drawcia.
Change-Id: I320de9a0c37ac033f3efda74eeb8f36e34667fd4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
|
|
These files were automatically generated by the lpddr4 version of
gen_part_id.go.
BUG=b:178715165
TEST=Build
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I3797ba6d52248961418000614a4f7885182521a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
These SPDs were generated by the lpddr4 version of gen_spd.go from the
global_lp4x_mem_parts.json.txt file.
BUG=b:178715165
TEST=None
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I7b9bd04534d6e45dbfe10a0028052978ef3d7c17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Looks like I forgot about trogdor-rev1 in CB:51004. Unlike rev0 (other
special case) or rev2 (works like CoachZ/Homestar), rev1 used the same
pin as Lazor and Pompom for EN_PP3300_DX_EDP. Apparently there are still
some people using these, so add in another special case for that.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I7093aa63778d69fde240af3b0c62b97ac99c28dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51196
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:180523962
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ic8f30f6d7c4781d4e8451546b39395a74393608f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
BUG=b:180507937
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ic607d6bca5c70255332a6fbee2b63e6daba7d1e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51047
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
1) Both SAR sensors had a UID of `2`, making them indistinguishable
2) No `device` underneath max98357a `chip`
Change-Id: Icf586229532819a7779652cbee73755b036dfbdc
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51145
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enabling the GPIO_SIGN_OF_LIFE option will allow for early boot testing.
BUG=b:180721202
TEST=builds
Change-Id: I069623ae76a4e4d1e43a47dd95fdfcece398ebfb
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
This is to align with newer platforms.
Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Modify I2C3 setting to follow I2C specification (lower than 400kHz).
Original setting:
.rise_time_ns = 184
.fall_time_ns = 42
Change to:
.rise_time_ns = 110
.fall_time_ns = 34
BUG=b:181091107
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ibdbb9a7dde524bdbde4789ee7ea005646080d97a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: Ie3870bc666acaea316f00b205de512cf790e720c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Configure I2C high / low time in device tree to ensure I2C
CLK runs accurately at I2C_SPEED_FAST (400 kHz).
Measured I2C frequency just as below after tuning:
touchpad:372 kHz
audio codec RT5682:386.8 kHz
speaker AMP L:387.5 kHz
speaker AMP R:388.9 kHz
BUG=b:181342340
BRANCH=dedede
TEST=Build and check after tuning I2C clock is under 400kHz
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I05d78c088190e349281a34b2aeed39ae8d867dc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51112
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add ELAN touchscreen into devicetree for storo.
BUG=b:177389448
BRANCH=dedede
TEST=built storo firmware and verified touchscreen function
Change-Id: I0d9e5005928c6fda3d1f0ce8bd9ae135e4a04867
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50981
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:177834652
BRANCH=dedede
TEST=build kracko firmware
Change-Id: I360920f80f4ce5dcbcde25c433e23803fa72569b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Brya’s chromeos.fmd contains a region for RECOVERY_MRC_CACHE,
but does not select HAS_RECOVERY_MRC_CACHE, so it’s unused.
BUG=b:174266035
TEST=Check MRC cache can allocate in recovery mode.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I6b83eec3dcf27bafde610a701e55f1371a5d4571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51081
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
As per CL:2641346, update GBB flag names:
GBB_FLAG_FORCE_DEV_BOOT_LEGACY -> GBB_FLAG_FORCE_DEV_BOOT_ALTFW
GBB_FLAG_DEFAULT_DEV_BOOT_LEGACY -> GBB_FLAG_DEFAULT_DEV_BOOT_ALTFW
BUG=b:179458327
TEST=make clean && make test-abuild
BRANCH=none
Signed-off-by: Joel Kitching <kitching@google.com>
Change-Id: I0ac5c9fde5a175f8844e9006bb18f792923f4f6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Follow elan's suggestion to configure IRQ as level trigger to prevent touchscreen lost
BUG=b:180778934
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I3aca0ad20791c989dec9e70d69d637b28c9cc043
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50417
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a weak variant routine to allow variants to perform any needed
initialization in ramstage.
BUG=b:178094376
TEST=none
Change-Id: I65dc1cdf15b68d9f2239e02fcb4b2c902d749378
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50827
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
GPP_E11 should be configured to be routed via APIC to avoid
p-sensor communication error in OS.
BUG=b:178465379
BRANCH=dedede
TEST=run "i2cdump -y -f 15 0x28" to confirm registers as expected.
un-approach：
=> register address: 0x01 value: 0x00
approach:
=> register address: 0x01 value: 0x02
verify sx932x IRQ in "/proc/interrupts" loading as expected.
Change-Id: I7d639ec1f9b31b240475dc1c8025bf59ae1e8e0b
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50876
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Create the blipper variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:179648964
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_BLIPPER
Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com>
Change-Id: I8e67521bd9ab05c257cb3d5d5d4cf506f258bfa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
New boards introduced to trogodor family.
BUG=b:180668002
BRANCH=none
TEST=make
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Change-Id: If0f9b6c89198a882acae7191d08b166eb8c1dd71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Stamp_boost 1640 parameter is too short to keep APU performance.
Restore parameter to 2500 then APU could have longer boost time (~3xxx sec)
BUG=b:175364713
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test => pass
Change-Id: Ie08394d0b1a693f71336cb4cb6ce9528dfdce14b
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Because the entries were formatted differently to the baseboard, the
devicetree overrides didn't work as intended, and all 5 entries from
the baseboard were included, and then the overrides were applied, but
the baseboard's entries were kept, so there were duplicate ACPI
entries, which causes errors when parsing the table.
Fixes: 5f30ae3714d ("mb/google/volteer: update thermal table for Eldrid")
BUG=b:181034399
TEST=compile, verify static.c is correct now
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I32fe2eae591ed4d3c08378977c463327f7ee1100
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51044
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update the first version DPTF parameters. The TDP is down to 13w for acoustic concern.
BUG=b:177777472
BRANCH=firmware-volteer-13672.B
TEST=build test image and verified by thermal team.
Change-Id: I36f016530a61e3660938ce8d2948bb3b0f275d88
Signed-off-by: Wayne3 Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51030
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update the first version DPTF parameters received from the thermal team.
BUG=b:177628854
TEST=cros build-ap --debug -b dedede --fw-name galtic
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ia8e76d303db0add95e77693f15cad108fa92303b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
BUG=b:177399759
TEST=firmware_EventLog passed on asurada
BRANCH=none
Change-Id: I759f9030f525fa9e34ed542198a9dba8f25909f5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Add ELAN touchpad into devicetree for storo.
BUG=b:177393444
BRANCH=dedede
TEST=built storo firmware and verified touchpad function
Change-Id: I95780d23b9ea5425d7762e850c25fd14d8a9caf4
Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50979
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Follow vendor suggestion to configure IRQs as level triggered to prevent TS lost.
BUG=b:171440909
BRANCH=dedede
TEST=1. emerge-dedede coreboot chromeos-bootimage
2. power on, suspend DUT to check TS is functional
Change-Id: I07a5cd5e2ac9caad9dbcca12e05bda7f08f42dce
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
associated GPIO configuartion
Adding LTE module support into devicetree and associated GPIO configuartion.
BUG=b:177385043
BRANCH=dedede
TEST=LTE function is OK
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I4d91045176fd6413ac6a5eed70289a5668e5b94f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
speaker amplifier support into devicetree
Adding audio codec and speaker amplifier support into devicetree
BUG=b:177479444
BRANCH=dedede
TEST=audio function is OK
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I90ff3a107278c711a085d04ae708e41f95d454ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Adding Touchpad support into devicetree.
BUG=b:177348842
BRANCH=dedede
TEST=touchpad function is OK
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I7ecafb5b3e39ff2ed9e176531bd0939f830a6397
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
and associated GPIO configuration
Adding camera support in devicetree and associated GPIO configuration.
BUG=b:177351873
BRANCH=dedede
TEST=camera function is OK
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I539e969e180c8c71d4b54b50519d2e1ff25415f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Configuring GPP_G7 as NC causes SD card detection issue.
Remove the GPP_G7 override and keep the baseboard
configuration as native function (SDIO_WP).
BUG=b:179733306
BRANCH=firmware-dedede-13606.B
TEST=Built and verified Kingston 64G SD card operation on boten
Change-Id: Ied319437de0e867ee9821d0151ff0c76834c4726
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Let's not have 7 boards of all use a different name for
the .enable_dev function in mainboard chip_operations.
Change-Id: I07f3569e6af85f4f1635595125fe2881ab9ddd43
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
The semantics of pirq_setup() from previous platforms was to
only setup the global pointers for PIC and APIC tables, not
to create or modify the tables themselves.
Change-Id: Iaa7c31eed21432dc2b3fe6b32803bd2658fd5e2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Recommendation from SOC to config IQ=8 for U3 port0,
vboost for all U3 ports for passing ESD pin test.
BUG=b:173476380
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run U3 SI/ESD pin test => pass
Change-Id: I0e6414f686a995536a0fd8aa0f6f70e5a36718a3
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50992
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Adjust H1 I2C CLK:
404kHz -> 391 kHz
BUG=b:179753353
BRANCH=zork
TEST=1. emerge-zork coreboot chromeos-bootimage
2. power on proto board successfully
3. measure i2c freq by scope is close to 400kHz
Change-Id: Iedd47dd6fc4f7ac7f0aac480d63ddbdf85a84ec2
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Set up EC_IN_RW GPIO in coreboot.
BUG=b:180686277
TEST=Verified that EC_IN_RW signal is read correctly in depthcharge.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Ic41012d3d4843dcab0f6dd9c28396cb9d5c49f08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Samsung K4E6E304EC-EGCG-4GB # 1011
BUG=b:179455694
BRANCH=oak
TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge,
update FW to DUTs,these DUTs can pass stress test under run-in.
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Change-Id: I02cc34157fd03edb7d715a23ed404abc40ef8ccc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50978
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
1. GPIO_4 to NC
BUG=b:179333669
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I4342b2beb7fc755bee47ee4fad0023d7a6592c4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50277
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
ChromeOS does not compile in CONFIG_OF, so PRP0001 will not successfully
register the device with its driver. Change to GOOG0005 to match other
ChromeOS devices with I2C-connected Cr50 TPM.
BUG=b:180657076
TEST=abuild
Change-Id: Ic1d4eb5e12ea7f7e693f1ffd3848e59668ac2deb
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50920
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:180530492
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I468d76d0e061431bc819ec12978203614bfe72b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50919
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable the building of guybrush variants and configure the first variant
also called guybrush.
BUG=b:180419462
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I3bed620378f9152277b4943ead1017f61a21ea82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50845
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:180419454
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I1e724e78b5ef378d474063417aa2b7e57a00886f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Follow elan's suggestion to configure IRQ as level trigger.
BUG=b:180570924
BRANCH=dedede
TEST=emerge-dedede coreboot
Change-Id: I292670580b4c2c18ed0c20a9fbb4ad4289f4eca6
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Rowan was the only Oak variant that used TPM2. However, it was removed
in commit 0aa1f9e905 (google/oak: Delete rowan). Since the other three
variants use TPM1, remove now-unnecessary Kconfig options from Oak.
Change-Id: If19df00463f63f1101475f59b5ecea5a9724a9ab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Sometimes the USB device will be lost after DUT resume.
Adjust USB phy settings for all USB ports to fix the failed symptom.
BUG=b:174538960
BRANCH=zork
TEST=USB devices stay connected after running suspend test
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I25bca968bb4a740161b36e2082d1e500ae648712
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50020
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Little point to replicate a string already provided both
as a global Kconfig and global mainboard_part_number.
Change-Id: I1fd138c711ebbb37c39b2c8f554b1f2e1a364424
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
|
|
Change-Id: I9d502882c4ddb54af1da42a41591804da2cee0ac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: I1d1323ab8bb8565c05fd50697e29c61f9932a2c7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Variable OSVR had a static value of 3 and OSFL() did not
actually call _OSI or _OS methods.
The conditional in HDA _INI method of OSVR is dropped and
use of DMA NoSnoop attribute remains disabled to retain
previous behaviour. For soc/amd/picasso a different decision
was made in CB:40782 as HDA _INI method was just dropped and
default configuration enables use of DMA NoSnoop attribute.
Change-Id: I967b7b2afbb43253cccb4b77f6c44db45e2989e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50592
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:175143925
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I8d038126b3e511bd16df2144652992c2d5b56c87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50507
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Mancomb is a new Google mainboard with an AMD Cezanne SOC.
BUG=b:175143925
TEST=builds
Change-Id: I1264f44a0b986f7f7c89ac7b42f1e4e4119a35e6
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50007
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The USB Type-A port on the MLB was added to the schematic at the last
minute and it was missed when adding brya0's overridetree. Also fix
a few USB ACPI entries.
BUG=b:180403898
TEST=`lsusb` shows plugged-in flash drive
Change-Id: I8bf96a8b365cb4ea2fc07d7cf673b08e8872ff88
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This comment is useless, and was dropped from the tree in the past.
Change-Id: Ie46bf13ec27ff9cd9423795fc170cc7526e18122
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49124
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'
Change-Id: I3ba39077014c50c2dfb9fddf78813f1058c45cc1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
With this selected, chromeos_reserve_ram_oops() is a no-op.
Change-Id: I2f3b7b3c4a9549a14f2ba039c769546f9698409a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Generated with a variant of
https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci
Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I6e0f33172fbcecebddfccdf64c22685636a23936
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50524
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Move `CROS_GPIO_DEVICE_NAME` to a new `chromeos.h` header, because
Lynxpoint uses a different value. Also drop unnecessary includes.
Tested with BUILD_TIMELESS=1, Google Tidus remains identical.
Change-Id: I38baed2c114fb93cfb82535a6ec00fb67e596d64
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50080
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The `GPIO_OUT_HIGH` macro is not present on Lynxpoint headers.
Change-Id: I12dd065bee49097c602febf18c6c9940ecec5106
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50078
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Prepare to unify Lynxpoint LP and Broadwell GPIO code.
Tested with BUILD_TIMELESS=1, Google Tidus remains identical.
Change-Id: I1521a51455e2aa148298853bb1878e82b9f0c368
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50077
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Prepare to unify Lynxpoint LP and Broadwell GPIO code.
Tested with BUILD_TIMELESS=1, Google Rikku remains identical.
Change-Id: I4d5bec4ec18b645a14d21fbee7334761901a30df
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50076
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Prepare to unify Lynxpoint LP and Broadwell GPIO code.
Tested with BUILD_TIMELESS=1, Google Jecht remains identical.
Change-Id: I193fe1471b8ade5d03e874f92425962c1ed960c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50075
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Prepare to unify Lynxpoint LP and Broadwell GPIO code.
Tested with BUILD_TIMELESS=1, Google Guado remains identical.
Change-Id: I3a806d07b0ca147492b90feaf90235ed919b1bb2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50074
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Prepare to unify Lynxpoint LP and Broadwell GPIO code.
Tested with BUILD_TIMELESS=1, Google Samus remains identical.
Change-Id: I465457ea8e9a9716121eacc0f6d64de463f41d89
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50073
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Prepare to unify Lynxpoint LP and Broadwell GPIO code.
Tested with BUILD_TIMELESS=1, Google Lulu remains identical.
Change-Id: I0f0a584b3354971ee8d478fd17825e498ff3e423
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50072
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Prepare to unify Lynxpoint LP and Broadwell GPIO code.
Tested with BUILD_TIMELESS=1, Google Gandof remains identical.
Change-Id: I168fcad7088706ca5b21f5fbf6790b13054499e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50071
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Prepare to unify Lynxpoint LP and Broadwell GPIO code.
Tested with BUILD_TIMELESS=1, Google Buddy remains identical.
Change-Id: I6e6256a9cc88c9d0743150bfdf12b1b482fe157d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50070
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Prepare to unify Lynxpoint LP and Broadwell GPIO code.
Tested with BUILD_TIMELESS=1, Google Auron Yuna remains identical.
Change-Id: I17e6bf20114f43da2897ec320ca26d8c6f6a4b09
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50069
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Prepare to unify Lynxpoint LP and Broadwell GPIO code.
Tested with BUILD_TIMELESS=1, Google Auron Paine remains identical.
Change-Id: I00b9184fe6f002c3e089c9fbc815862d60e7694f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50068
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:180013349
TEST=console shows successful EC <-> SoC communications
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie09dcfa8b0de2706ffc236a978dc159594e327c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Add Kconfig options and devicetree entries for cr50 TPM.
BUG=b:180017621
TEST=verify (via console) successful cr50 communications in
verstage and payload (depthcharge).
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I80e27d0377960fb81f9149efb6f062d06432d40d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Second pass GPIO configuration to enable the non-native function
GPIOs based on the guybrush Proto 0 reference schematic 0210.
BUG=b:177909472
TEST=builds
Change-Id: I0fdc4d7369353f88cf05e2e1ec08898d4605e602
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Rename structs, types and functions to match Lynx Point's names.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I11ea27b00b5820eb5553712e0420836470ec0d27
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50064
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Not referenced anywhere in ASL.
Change-Id: I52ac4722e48e1cc377386316dc034fb45a98181a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50471
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Needed to enable ACPI support for cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia5869905ed053cdca5f61697cffc7f9b59370859
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Some Trogdor variants will include a fingerprint sensor, so this patch
adds support for its power sequencing. There is a requirement that the
fingerprint power needs to be *off* for at least 200ms, and when it is
turned back on it needs to stabilize for at least 3.5ms before taking
the FPMCU out of reset. We meet these timing requirements by splitting
the sequence across bootblock, romstage and ramstage. On current Trogdor
boards we measured <end of bootblock> to <end of romstage> at ~430ms and
<end of romstage> to <start of ramstage> at 12ms, so we easily meet the
required numbers this way.
BRANCH=trogdor
BUG=b:170284663
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iccd77e6e1c378110fca2b2b7ff1f534fce54f8ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
This is ACPI specific config that applies to all the AMD SoCs. Stoney
doesn't currently use this, but we can add that functionality later.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0be7d917d7c5ba71347aa646822a883e2cf55743
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50557
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The code to read the SPD file and index it is not variant-specific.
Change-Id: Ifaedc39b683901b60abbb1d984f1d38c1ed364e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50542
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I72b717a41c5611cf578ce178722029b8646cbb35
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50539
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use global variables to provide mainboard USB settings, and have the
northbridge code copy it into the `pei_data` struct. For now.
To minimize diffstat noise, this patch does not reindent the now-global
mainboard USB configuration arrays. This is cleaned up in a follow-up.
Change-Id: I273c7a6cd46734ae25b95fc11b5e188d63cac32e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50538
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently, the address size field of AT24 NVM is incorrect, and
Linux v5.4 kernel logs the message below:
at24 i2c-PRP0001:02: Bad "address-width" property: 13
The valid size of the AT24 NVM is 16 bits so modify the value from
0x0D to 0x10.
BUG=b:177655681
BRANCH=none
TEST=Boot volteer and check the kernel log and see "Bad address-width"
error message is not shown.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: Ice6c3eac1e023b981217e1d7dc06587fc46b1a02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bingbu Cao <bingbu.cao@linux.intel.com>
|
