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Instead of hard-coding the polarity of the GPIO to active high/low,
accept it as a parameter in devicetree. This polarity can then be used
while calling into acpi_dp_add_gpio to determine the active low status
correctly.
BUG=chrome-os-partner:55988
BRANCH=None
TEST=Verified that correct polarity is set for reset-gpio on reef.
Change-Id: I4aba4bb8bd61799962deaaa11307c0c5be112919
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/16877
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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GPIO1_B3 (WLAN_MODULE_RST#) defaults as a pull-up input, but it is also
"pulled up" by 1.8V_WLAN. However, 1.8V_WLAN remains low for some time
during early boot. This leaves the signal floating somewhere in the
middle.
This has two potential issues:
(1) we're leaking some power for some (hopefully) short period of time
(2) we are possibly screwing with the Wifi power sequence; we aren't
supposed to deassert PDn (i.e., MODULE_RST#) until all the rails
have fully ramped for some period of time
Neither of the above issues are likely to be significant, but it is nice
to fix, I expect.
BRANCH=gru
BUG=chrome-os-partner:54026
TEST=measure WLAN_MODULE_RST# on scope at boot time
Change-Id: Ia6af9ad6954ad8feeda33015e3f205842380939e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0e890a2787bf034d3358a33fc88c2dd8078593ab
Original-Change-Id: I120e26ad0ca486a326874986e142dcaee965b62d
Original-Signed-off-by: Brian Norris <briannorris@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/388009
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16882
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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PHY_PER_CS_TRAINING is being enabled when DDR frequency >= 666.
For per cs training, the controller should consider the PHY
delay line switch time and there should be more cycles to
switch the delay line, so update the W2W_DIFFCS_DLY_ value
from 0x1 to 0x5.
BRANCH=none
BUG=chrome-os-partner:56940
TEST=do memtester on kevin board, and pass
Change-Id: I00df2d4724b0b77f3e7565809fb35bbd2ff01ea5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c135ea3e33d810ed322d947eb8d512d1ac119cfc
Original-Change-Id: I81b99cbc085769b7028e770509d79bd8d550820b
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/387506
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16721
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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To save power when entering suspend, gpios 2 to 4 need to be set
to input and 'pull none' mode.
Pass the APIO configuration to ATF so it can do a proper job here.
BRANCH=None
BUG=chrome-os-partner:56423
TEST=run suspend_stress_test on kevin board
Change-Id: Id57fe8f622ae3f9c2bc7e58be89518b2b846cd37
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9c42082d1ca9a6baa735821382d3e83c1f8dc9ad
Original-Change-Id: Iaf441e8e34c5591ffe7c65f6533fcf0b733ff5ac
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/378475
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16720
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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We need to disable some regulators when the device goes into suspend.
This means that we need to pass some gpios to bl31, and disable these
gpios when bl31 runs the suspend function.
BRANCH=None
BUG=chrome-os-partner:56423
TEST=enter suspend, measure suspend gpio go to low
[pg: also update arm-trusted-firmware to match]
Change-Id: Ia0835e16f7e65de6dd24a892241f0af542ec5b4b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0f3332ef2136fd93f7faad579386ba5af003cf70
Original-Change-Id: I03d0407e0ef035823519a997534dcfea078a7ccd
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/374046
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16719
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Create the initial Pyro variant which refers to the Reef.
Pyro is APL Chrome board that deviate from reference board Reef.
BRANCH=master
BUG=None
TEST=Build
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Change-Id: I9beed1f6895e8891d3d51b563edfe172f566718b
Reviewed-on: https://review.coreboot.org/16855
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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To improve sdram 800MHz and 933MHz stability, we
need to modify write leveling flow to get the
proper write leveling value.
BUG=chrome-os-partner:56940
BRANCH=none
TEST=Boot from kevin on 933MHz, and do stressapptest
Change-Id: I5b24c93d4a57917fb9af7e5e2a95d8423ccbaa7e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d84bf25b3e5de373c7913e6d534a810cb984b3fd
Original-Change-Id: I87efddf628c3683fcb85d6875e029cf3cbc482be
Original-Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/384292
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16716
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Since there's currently a limitation in coreboot's code that prevents
more than 4KB to be used by the eventlog anyway, this patch shrinks the
available RW_ELOG area in the FMAP for Gru down to 4KB. This may prove
prudent later if we ever resolve that limitation, so that tools can rely
on the area in the FMAP being the same as the area actually used by the
read-only firmware code on these boards.
BRANCH=gru
BUG=chrome-os-partner:55593
TEST=Booted Kevin, confirmed that eventlog got written normally. Ran a
reboot loop to exhaust eventlog space, confirmed that the shrink code
kicks in as expected before reaching 4KB.
Change-Id: I3c55d836c72486665a19783fe98ce9e0df174b6d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 05efb82ca00703fd92d925ebf717738e37295c18
Original-Change-Id: Ia2617681f9394e953f5beb4abf419fe8d97e6d3e
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/384585
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Simon Glass <sjg@google.com>
Reviewed-on: https://review.coreboot.org/16715
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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sdram noc timing will affect ddr latency, this patch improves
rk3399 sdram noc timing so improve memory performance.
BRANCH=gru
BUG=chrome-os-partner:57248
TEST=Boot from kevin board
Change-Id: I09e984490a7ad747ef8abfc6542d0e2c95ec19bc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 43dfe55d713d371e39d21312772fd353614b7642
Original-Change-Id: I393e74ecdeb72930ac38ae9bcf311e5654f65162
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/382725
Original-Reviewed-by: Sonny Rao <sonnyrao@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Sonny Rao <sonnyrao@chromium.org>
Original-Commit-Queue: Sonny Rao <sonnyrao@chromium.org>
Reviewed-on: https://review.coreboot.org/16713
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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We found some boards are not stable when sdram is run at 933Mhz.
Before we can fix it, we need to lower the sdram frequency to 800MHz.
In this patch we modify the DQS delay from 0x280 to 0x260 and extend
the DQS window.
BRANCH=None
BUG=chrome-os-partner:56940
TEST=Booted Kevin.
Change-Id: I68561c4aa4d9ab66acfa3515a42d696157aff759
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 877a7f6ad22a5bde9f9e458bcb65f133f2f001bd
Original-Change-Id: I5eab6bbe96f0dae095c5353403292022e7a25421
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/382724
Original-Commit-Ready: Douglas Anderson <dianders@chromium.org>
Original-Tested-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/16709
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add lpddr3-K4E6E304EB-2GB-1CH memory configuration for rialto.
BUG=chrome-os-partner:56759
BRANCH=none
TEST=Build
Change-Id: I698fe450d48b64a06232aa44ecf91d688d9dc17a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d3edecdb135939c3264ab1b831e7821d3a3e0149
Original-Change-Id: I7dae9fd822abeff5b08de0ab9262e1817ac58531
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/380443
Original-Commit-Ready: Alexandru Stan <amstan@chromium.org>
Original-Tested-by: Alexandru Stan <amstan@chromium.org>
Original-Reviewed-by: Alexandru Stan <amstan@chromium.org>
Original-Reviewed-by: Jonathan Dixon <joth@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16699
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch moves the big CPU cluster initialization on the RK3399 from
the clock init bootblock function into ramstage. We're only really doing
this to put the cluster into a sane state for the OS, we're never
actually taking it out of reset ourselves... so there's no reason to do
this so early.
Also cleaned up the interface for rkclk_configure_cpu() a bit to make it
more readable.
BRANCH=None
BUG=chrome-os-partner:54906
TEST=Booted Kevin.
Change-Id: I568b891da0abb404760d120cef847737c1f9e3ec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bd7aa7ec3e6d211b17ed61419f80a818cee78919
Original-Change-Id: Ic3d01a51531683b53e17addf1942441663a8ea40
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/377541
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/16698
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Several of the special function pins we're using in firmware have a
pre-assigned pull-up or pull-down on power-on reset. We don't want those
to interfere with any of the signaling we're trying to do on those pins,
so this patch disables them.
Also do some house-cleaning to group the bootblock code better, and
change the setup code for all SPI and I2C buses to first initialize the
controller and then mux the pins... I assume this might be a little
safer (in case the controller peripheral has some pins in a weird state
before it gets fully initialized, we don't want to mux it through too
early).
BRANCH=None
BUG=chrome-os-partner:52526
TEST=Booted Kevin.
Change-Id: I4d5bd3f7657b8113d90b65d9571583142ba10a27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f8f7fd56e945987eb0b1124b699f676bc68d0560
Original-Change-Id: I6bcf2b9a5dc686f2b6f82bd80fc9a1a245661c47
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/382532
Reviewed-on: https://review.coreboot.org/16711
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Increase the SPI bus speed to speed up boot time. The maximum supported
speed at 1.8V is 37.5MHz, and 33MHz is the next lowest convenient speed,
given the clock parents.
BUG=chrome-os-partner:56556
BRANCH=none
TEST=boot on gru and see that things still work correctly. Total time
spent on reading from SPI reduces from 185ms to 141ms.
Change-Id: I71436c9e343b18360fa63d528dea5cfcfbc831e6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d7576f6e53e407af61160be142c3d589e864a8cf
Original-Change-Id: I55a19f523817862e081d23469e94fd795456dd67
Original-Signed-off-by: Simon Glass <sjg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/381313
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Simon Glass <sjg@google.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16708
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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If we setup the PWM _after_ the pinmux then there's a period of time
when we're driving the PWM incorrectly. Let's setup the regulator and
_then_ configure the pinmux.
This fixes no known bugs, but it is more correct and probably makes the
signals look better at bootup.
BRANCH=None
BUG=None
TEST=scope
Change-Id: I311c0eded873b65e0489373e87b88bcdd8e4b806
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fcf4d0ba29d82cce779c0b25ead36de4a95d97a1
Original-Change-Id: I5124f48d04a18c07bbd2d54bc08ee001c9c7e8d1
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/381592
Original-Reviewed-by: Simon Glass <sjg@google.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16700
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Iab0c7c470a3105b5df7b6b74aebdd1329e7f93ba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16859
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Kconfig symbols of type bool are ALWAYS defined, so this code was
always being included and run, which isn't what the author wanted.
Change to use IS_ENABLED(), and a regular if() instead of an #ifdef.
Change-Id: I72623fa27e47980c602135f4b73f371c7f50139b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16837
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Everybody knows WHAT they're supposed to do with options, so the text
"Pick this" or "Select to" are redundant.
Change-Id: I327c5be755373e99ca0738593bd78e1084d4d492
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16838
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Kconfig hex values don't need to be in quotes, and should start with
'0x'. If the default value isn't set this way, Kconfig will add the
0x to the start, and the entry can be added unnecessarily to the
defconfig since it's "different" than what was set by the default.
A check for this has been added to the Kconfig lint tool.
Change-Id: I86f37340682771700011b6285e4b4af41b7e9968
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16834
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This patch increases the CPU specific passive temp. trip point
and critical temp. trip point value for DPTF policy.
BUG=chrome-os-partner:57903
TEST=Built, booted on reef and verified this passive and
critical temp. trip points with heavy workload.
Change-Id: I2a38d01a6539c1bd478f8716c4b543ebcd1f2080
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/16766
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
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For all mainboard variants use the "Google_Reef" family by default
which is populated in SMBIOS tables. A variant can provide their own
value if needed, but "Google_Reef" can reside as the family without
having to add conditions for each variant when MAINBOARD_FAMILY
have to be overridden.
BUG=chrome-os-partner:56677
Change-Id: Ic214eae1e6473b32f4cb442c09c34355357e1257
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16813
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
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These default values weren't being set with the default
keyword so were ending up with different values.
from the default generated config file before this change:
CONFIG_DRIVER_TPM_I2C_BUS=0x9
CONFIG_DRIVER_TPM_I2C_ADDR=0x2
CONFIG_DRIVER_TPM_I2C_IRQ=-1
Change-Id: I19514d0c9b2a9b7e479f003a4d3384e073f4d531
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16828
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Because these variables had "non-hexidecimal" defaults, they
were updated by kconfig when writing defconfig files.
Change-Id: Ic1a070d340708f989157ad18ddc79de7bb92d873
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16827
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I2402648b8c0b9dcc730ce7f099e1e4ccef3b79fc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16814
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Add the 'probed' flag to the touchpad and touchscreen devices so they
are probed by the kernel before being loaded, in case they do not exist
or are replaced with another vendor.
BUG=chrome-os-partner:57686
Change-Id: I0a61964e6874cd99fab0c21fa404a43548fc8ab5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16743
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add a header file to provide common declarations that the
mainboards can use regarding EC init.
BUG=chrome-os-partner:56677
Change-Id: Iaa0b37eff4de644e969a18364713b90b7f27fa1c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16734
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins)
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Defer to the lid switch implementation provided by the chromeec.
BUG=chrome-os-partner:56677
Change-Id: Ida451dc29c8cf55fb88015e48a9e0bca3740f645
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16733
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
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Instead of having each mainboard provide the power button,
uncondtionally provide the power button ACPI device on behalf
of each mainboard.
BUG=chrome-os-partner:56677
Change-Id: I94c9e0353c8d829136f0d52a356286c6bedcddd5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16731
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Some changes were made in upstream in the meantime that broke the build:
- CHROMEOS_VBNV_CMOS was renamed to VBOOT_VBNV_CMOS
- recovery_move_enabled() -> vboot_recovery_mode_enabled()
- chromeos.asl was replaced by an acpi generator
Change-Id: Icd4ed5111cce9db79e12efb0cb7e898bba725c20
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16683
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Migrate google/enguarde (Lenovo N21 Chromebook) from Chromium tree to
upstream, using google/rambi as a reference.
original source:
branch firmware-enguarde-5216.201.B
commit cf1f57b [Enguarde: Adjust rx delay for norm.]
TEST=built and booted Linux on enguarde with full functionality
blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.elf)
external reference code (refcode.elf)
Change-Id: I3ccda29d1e095d8b1b36766cda913172f72233a7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/15444
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during
verstage. The interrupt is left in APIC mode as the GPE is
still latched when the GPIO is pulled low.
BUG=chrome-os-partner:53336
Change-Id: Ib0247653bdcbaccb645cd16b81d7ec3c38f669af
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16673
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
These values are found in util/cbfstool/cbfs.h.
Change-Id: Iea4807b272c0309ac3283e5a3f5e135da6c5eb66
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16646
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: If3cdfdff60c92e3427f1b285e2bca92e2bb2a1cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16640
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
In kernel side we set 1.1v for 1.5G, even for coreboot RO,
a higher voltage could be safer, 1.2v now seems too high.
BRANCH=none
BUG=chrome-os-partner:56948
TEST=bootup
Change-Id: I852e0d532369aad51b12770e2efb01aacf6662ce
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 000b5c099373be2a1f83c020ba23a0e79ea78fab
Original-Change-Id: Iecc620deee553c61a330353ac160aa3a36f516df
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/380896
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16583
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This enhances gradation of some icons on vboot screens.
BUG=chrome-os-partner:56056
BRANCH=none
TEST=Booted Jerry
Change-Id: Ia19d585b69e7701040209e8bf0b8a6990a166c95
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4e7a42c999673ebd89c5b30845a4a5ec93852166
Original-Change-Id: I126cb7077c834e1a8b0a625a592dce8789b5876c
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/376884
Reviewed-on: https://review.coreboot.org/16581
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
We did yet another small adjustment to the PWM regulator ranges for
Kevin rev6... this patch reflects that in code. Also rewrite code and
descriptions to indicate that these new ranges are not just for Kevin,
but also planned to be used on Gru rev2 and any future Gru derivatives
(which as I understand it is the plan, right?).
BRANCH=None
BUG=chrome-os-partner:54888
TEST=Booted my rev5, for whatever that's worth...
Change-Id: Id78501453814d0257ee86a05f6dbd6118b719309
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4e8be3f09ac16c1c9782dee634e5704e0bd6c7f9
Original-Change-Id: I723dc09b9711c7c6d2b3402d012198438309a8ff
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/379921
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/16580
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This enhances gradation of some icons on vboot screens.
BUG=chrome-os-partner:56056
BRANCH=none
TEST=Booted kevin-tpm2
Change-Id: I2fc943f89386ccc6cd9293f5811182a5a51d99b0
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: bb1f0fb00d023c045305edc6c9fc655b764a4e8c
Original-Change-Id: Ieb61830b9555da232936087cdcf7c61a1e55bab4
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/376883
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16579
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This patch adds support to reboot the whole board after a hardware
watchdog reset, to avoid the usual TPM issues. Work 100% equivalent to
Veyron.
From my tests it looks like both SRAM and PMUSRAM get preserved across
warm reboots. I'm putting the WATCHDOG_TOMBSTONE into PMUSRAM since that
makes it easier to deal with in coreboot (PMUSRAM is currently not
mapped as cached, so we don't need to worry about flushing the results
back before reboot).
BRANCH=None
BUG=chrome-os-partner:56600
TEST='stop daisydog; cat > /dev/watchdog', press CTRL+D, wait 30
seconds. Confirm that system reboots correctly without entering recovery
and we get a HW watchdog event in the eventlog.
Change-Id: I317266df40bbb221910017d1a6bdec6a1660a511
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 3b8f3d064ad56d181191c1e1c98a73196cb8d098
Original-Change-Id: I17c5a801bef200d7592a315a955234bca11cf7a3
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/375562
Original-Commit-Queue: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/16578
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This reverts commit 24de342438208d9b843e87627f15b9a272285b0f.
|
|
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during
verstage. The interrupt is left in APIC mode as the GPE is
still latched when the GPIO is pulled low.
BUG=chrome-os-partner:53336
Change-Id: I28ade5ee3bf08fa17d8cabf16287319480f03921
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
|
|
This patch sets some magic number in magic undocumented registers that
are rumored to make USB 2.0 signal integrity better on Kevin. I don't
see any difference (unfortunately it doesn't solve the problems with
long cables on my board), but I guess it doesn't hurt either way.
BRANCH=None
BUG=chrome-os-partner:56108,chrome-os-partner:54788
TEST=Booted Kevin with USB connected through Servo. Seems to have
roughly the same failure rate as before.
Change-Id: If31fb49f1ed7218b50f24e251e54c9400db72720
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0c5c8f0f80ea1ebb042bcb91506a6100833e7e84
Original-Change-Id: Ifbd47bf6adb63a2ca5371c0b05c5ec27a0fe3195
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/370900
Original-Reviewed-by: Guenter Roeck <groeck@chromium.org>
Original-Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-on: https://review.coreboot.org/16265
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This implements PRW method for WLAN and configures PCIe wake pin to
generate SCI.
BUG=chrome-os-partner:56483
TEST=Suspend the system into S3 or S0ix. System should resume through wake
event from wifi.
Change-Id: I9bd078c2de19ebcc652b5d981997d2a5b5f0b1b7
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16611
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
There are certain board-specific options for reef variants. The
big one is the DPTF settings. Rearrange the ASL files such
that dsdt.asl is the main landing area. The ACPI options for
Chrome EC are contained in the variant/ec.h header so the
actual code #includes can just reside in dstd.asl. Since most
of the mainboard specific peripherals are auto generated by
the acpigen from devicetree there's no real separate need
for mainboard.asl. The one thing not addressed in this CL
is the notion of a variant having the Chrome EC or not (along
with lid, etc). Future indirection can be provided when needed
to address that requirement.
BUG=chrome-os-partner:56677
Change-Id: I5c888f5fc64913dcff010c28f87e69ac5449e6b6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16604
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
This patch removes setting of gpio_tier1_sci_en from mainboard
smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
now.
BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Change-Id: I26fd3fd9fcc83c988bcff1bda4da7a2e3da98ce6
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16566
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This patch sets tuned RAPL power limit PL1 value to
12W in acpi/dptf.asl for RAPL MSR register. With PL1
as 12W for WebGL and stream case, we measured SoC power
reaching upto 6W. Above 12W PL1 value, we observed that
Soc power going above 6W. With PL1 as 12W, system is
able to leverage full TDP capacity.
BUG=chrome-os-partner:56524
TEST=Built, booted on reef and verifed the package
power with heavy workload.
Change-Id: I8185ce890f27e29bc138ea568af536bc274fe7b8
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/16596
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This configures PERST_0 in devicetree. For boards without
PERST_0, the pin should be disabled. For boards with PERST_0
the correct GPIO needs to be assigned.
BUG=chrome-os-partner:55877
Change-Id: I705009b480e02b4c9b2070bb4f82cb4d552e9a46
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16603
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
Add MKBP as a SCI event: the EC is then able to send events coming from
the sensors.
BUG=b:27849483
TEST=With EC configure to send MKBP events, check sensor information are
retrieved by the kernel.
Change-Id: Ib06241bfcdc8567769baff4f3371cc0c6eab3944
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/16594
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This driver is only a prototype driver, real driver
will be integrated at a later time.
Testing: booted successfully.
Change-Id: I372764962e96e5c9c827d524bc369978c5c1fda8
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/16554
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I1f97b6f159a0ac36c96636066332ba355c056186
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15507
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This setting enables lpss to power gate in S0ix.
BUG=chrome-os-partner:53876
Change-Id: I0a0fecb0e2b6e5e2f89ac505dd603f4be1bc161e
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16558
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
1. Removes PCIe blocker for S0ix.
2. Set the correct PCIe root port for wifi/bt on EVT.
3. Turn off CLKREQs of unused PCIe root ports to power gate the IP.
Change-Id: Iefd8869688d3a44b435dab9fc792275cd7f7e091
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16557
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Move the current devicetree.cb to be under variants/baseboard.
New variants can provide their own devicetree as needed.
BUG=chrome-os-partner:56677
Change-Id: Ib109ca4be883884b318264500d14aa8d40e3072a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16510
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Removes S0ix blocker. Sets audio clock gate and power gate
bits when audio not in use. Reduces power in S0.
Change-Id: Id5c0adc2605480583dc90ee62a706dbfa4027c1b
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16424
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Enable the I2C based TPM on the reef board at
bus 2 and address 0x50.
This makes vboot functional without needing MOCK_TPM and
results in the following in the SSDT:
Device (TPMI)
{
Name (_HID, "GOOG0005") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_DDN, "I2C TPM") // _DDN: DOS Device Name
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
I2cSerialBus (0x0050, ControllerInitiated, 0x00061A80,
AddressingMode7Bit, "\\_SB.PCI0.I2C2",
0x00, ResourceConsumer)
Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive)
{
0x00000039
}
})
}
Change-Id: Ia9775caabeac3e6a3bd72de38f9611b4cea7cea4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16398
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The pull up for CLKRUN is required to resolve keyboard slowness
and malfunctioning observed on some reef systems. The CLKRUN
signal was probed and found to be floating when the pull up
was not enabled. Also Added pull ups for the LPC Multiplexed
command, address and data lines LAD0:3 because the LPC
Interface specification requires them.
BUG=chrome-os-partner:55586
BRANCH=none
TEST=When a key is pressed, the character is immediately visible
on the screen. Also the interrupt count for i8042 increments
immediately in /proc/interrupts.
Change-Id: I16df1a0301a3994c926a609f61291761219f9e01
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/16426
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
The last vestige of the proto boards is the memory sku id
gpios. The internal pullups are still required because there's
only pulldown stuffing options available on the reef boards.
BUG=chrome-os-partner:56791
Change-Id: I04d541a897ec9aacbf2011293d18242fa32896d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16432
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Move the current NHLT configuration implementation to the baseboard
area such that other variants can leverage it or provide their
own configuration.
BUG=chrome-os-partner:56677
Change-Id: If0d48cacdc793492e1618d0eda02a149e33f0650
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16431
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Move the current memory configuration implementation to the baseboard
area such that other variants can leverage it. The swizzle config
is exported as a global to allow duplicate swizzles to use the same
structure while still allowing different memory SKUs.
BUG=chrome-os-partner:56677
Change-Id: I57201118053051c01f0e3f164ab4bbaf650b892b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16430
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Add support for Chrome OS gpio ACPI table information by
providing weak implementation from the baseboard.
BUG=chrome-os-partner:56677
Change-Id: I517764b78f47fb7b3637482ff9efc053cdd1ac69
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16422
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Since multiple boards will be living within one directory move all
the macros for defining anyting related to GPIOs to the gpio.h
header file. That way, when other boards land they can override
or use them as is.
BUG=chrome-os-partner:56677
Change-Id: I36967e57fc61ef354e0b51d1ff1396ce562fa805
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16421
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
There's no common EC header file in the code base, and I didn't
want to use a header file for single declaration. Therefore,
just move the declaration to each file that uses that symbol.
BUG=chrome-os-partner:56677
Change-Id: Ibaebb0ea6a07029aec02d5185cf05ffb8593b117
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16420
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Provide APIs for the board_id() and gpio table functionality.
Default and weak implementations are provided from the baseboard.
BUG=chrome-os-partner:56677
Change-Id: I02d8deb7f60f8c4842916a9d35f51d8af74b1da4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16419
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Indent the I2C device for touchscreen with tabs so it
aligns properly.
Change-Id: Id9b2d26a4acdd6fe6c69055907258df3cc035b31
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16399
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
|
|
To further the ability of multiple variant boards to share code
provide a place to land the split up changes. This patch provides
the tooling using a new Kconfig value, VARIANT_DIR, as well as
the Make plumbing. The directory layout with a single variant,
reef (which is also the baseboard), looks like this:
variants/baseboard - code
variants/baseboard/include/baseboard - headers
variants/reef - code
variants/reef/include/variant - headers
New boards would then add themselves under their board name
within the 'variants' directory.
No split has been done with providing different logic yet.
This is purely a organizational change.
BUG=chrome-os-partner:56677
Change-Id: Ib73a3c8a3729546257623171ef6d8fa7a9f16514
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16418
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Instead of completely duplicating the a reference board's directory
when doing a variant or follower device start providing a means to
share code within a single directory. This change just starts the
process from the Kconfig side, but subsequent patches will follow
which disentangles the board specific pieces from and common
logic.
BUG=chrome-os-partner:56677
Change-Id: I96628920d78012e488ec008e35daac9c1be0cf79
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16417
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
The superio.asl wasn't being included within the right scope.
Fix that as well as clean up the per-mainboard header includes
to be in one place.
BUG=chrome-os-partner:56677
Change-Id: I5e6a82f9f2e3c7455132263d19b32b2f06220376
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16413
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
|
|
Some of the macros in gpio.h are no longer used because
devicetree.cb is being used to autogeneric the ACPI AML.
Therefore remove the unused macros.
BUG=chrome-os-partner:56677
Change-Id: I433a929229a0318f6c1df652655d046a5152cc63
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16412
Tested-by: build bot (Jenkins)
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
The following patch is based off of the UEFI 2.6 patch. The FSP header files
are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated
since the other headers expect it to be in the root of an includable directory.
Any struct defines were removed since they are defined in the headers and no
longer need to be explicity declared as struct with the UEFI 2.6 includes.
BUG=chrome-os-partner:54100
BRANCH=none
TEST=confirmed coreboot builds successfully
Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>#
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16308
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Many changes make proto boards very hard to work with since
proto boards were using A stepping processors. Everyone has
moved on. Therefore, drop non-proto support.
BUG=chrome-os-partner:56791
Change-Id: I2985e3965b1b69445e22506bd664b4cbca13c8ab
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16377
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
|
|
A pen interface was added. Prepare for possibly testing it by
plumbing in the gpio configuration. It's very possible these
changes need to be tweaked, but no driver code has been seen
yet nor a datasheet detailing how some of these signals actually
function.
BUG=chrome-os-partner:56739
Change-Id: I208ff3e151ce55d62e5fcc33a1e39cc87e229970
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16376
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The formerly name FP_INT_L net is actually active high and is push-pull.
Therefore adjust for the new net name, FP_INT, and polarity. The
pulldowns are there because the device is on another board that isn't
always available.
BUG=chrome-os-partner:56740
Change-Id: I6706fd2c2bd164cf3b5f1457aef69f5675f2112d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16375
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Two new SKUs are being utilized for reef DVT. Add the following:
Hynix 8GiB using H9HCNNNBPUMLHR-NLE -- id: 4'b0100
Hynix 4GIB using H9HCNNN8KUMLHR-NLE -- id: 4'b0101
BUG=chrome-os-partner:56738
Change-Id: I39ed9e827501939b92cbcce6092302b5a23d1d78
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16374
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The reef DVT build added another way to assert the wifi module's
reset line. Ensure it's deasserted by default. For previous boards
this GPIO doesn't matter because it wasn't routed anyway.
BUG=chrome-os-partner:56737
Change-Id: I63e97b091ca0a278682c883303b1d7e052d8e677
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16373
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Before, we calculate the pwm duties for cpu cores and centerlogic by
hand, adding pwm_regulator.c to handle this. The default pwm design
min/max voltage may be different between revs.
With the pwm regulator, this patch changes the little cpu frequency from
600M to 1512M, and raises CPU voltage to 1.2V correspondingly.
This also means we decide to drop the ES1 because it may fail to
bootup with 1.5G ~ 1.2v.
BRANCH=none
BUG=chrome-os-partner:54376,chrome-os-partner:54862
TEST=Bootup on kevin board
Change-Id: Id04c176bddfb9cdf3d25b65736e40249a85f6aa1
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: ee4365c787ec523b7ee1028ea100dcfbb331b3a9
Original-Change-Id: Ide75bbd92d1cbb14f934baeec0e38862bc08402b
Original-Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/364410
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16368
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The romstage.c is more board related than soc specific, like
setting the pwm regulators, so moving it to mainboard/gru.
BRANCH=none
BUG=chrome-os-partner:54819
TEST=Bootup on kevin board
Change-Id: I83c6cde9f451480e47e2b4b549cedf65b345134c
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 35feeb07131a6a9de4adde035236987391833474
Original-Change-Id: If2bf245302eb4fb20bb089c1b3ffa03909722443
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/375398
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16367
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Provide GBB's hardware ID (used on Chrome OS devices) because it will be
dropped from depthcharge.
BRANCH=none
BUG=none
TEST=none
Change-Id: I4851c1bdb21863983277d3283105c88b85a6166b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 705251d2899bc006e21ff3e34a3fc3eba2dd4d00
Original-Change-Id: I7488533b83b8119f8c85cbf2c2eeddabb8e9487d
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/372579
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16363
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Certain LPDDR4 models have some HW issues that can be worked around
by turning off Periodic Retraining feature in the memory controller.
Add option to disable PR per SKU.
BUG=chrome-os-partner:55466
TEST=run RMT test, pass
Change-Id: Ie7aa79586665f6d3a7edd854a9eef07e6a1b2ab8
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16320
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
This corrects indentation for sdram configs in nyan_blaze.
Change-Id: Ia9ad2a37c6e3b79e1260f490db893244c32685b6
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/16342
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The reef board needs at least ~28ms for its S0 rails to discharge
when S3 is entered. Because of the granularity in the chipset the
effective SLP_S3_L assertion width is 50ms.
BUG=chrome-os-partner:56581
Change-Id: I20514eb0825cd4bc2ee9276b648204b7bfd6a7b0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16327
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This patch changes Gru SDRAM parameters from structures that just get
compiled into the romstage to individual CBFS files. This allows us to
only load the parameter set we need for the board we're booting from
flash, which reduces our boot time and the SRAM memory footprint
required to hold the romstage.
TEST=Booted Kevin.
Change-Id: Ie88a515cbdb19a794ca0a230a56bcc82bed1e550
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16274
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
On x86 platforms, google_chromeec_early_init() is used to put the EC
into RO mode when there's a recovery request. This is to avoid training
memory multiple times when the recovery request is through an EC host
event while the EC is running RW code. Under that condition the EC will
be reset (along with the rest of the system) when the kernel verification
happens. This leads to an execessively long recovery path because of the
double reboot performing full memory training each time.
By putting this logic into the verstage program this reduces the
bootblock size on the skylake boards. Additionally, this provides the
the correct logic for all future boards since it's not tied to FSP
nor the mainboard itself. Lastly, this double memory training protection
works only for platforms which verify starting from bootblock. The
platforms which don't start verifying until after romstage need to
have their own calls (such as haswell and baytrail).
Change-Id: Ia8385dfc136b09fb20bd3519f3cc621e540b11a5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16318
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Apply eMMC tuned DLL settings for reef evt.
Modify comments to avoid replicating info.
Add EDS reference.
BUG=chrome-os-partner:55648
BRANCH=none
TEST=Verify that reef evt boots to OS from eMMC.
Change-Id: If3bf51f3b7d38320f504ea6fbecf7c188a94ae5c
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Reviewed-on: https://review.coreboot.org/16296
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add support for SMBIOS memory HOB save.
Add DIMM 'part_num' info to be saved as part of SMBIOS memory HOB.
BUG=chrome-os-partner:55505
TEST='dmidecode -t 17' and 'mosys -k memory spd print all'
Change-Id: I53b4a578f31c93b8921dea373842b8d998127508
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/16249
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
We should be running faster. Faster = better.
BRANCH=None
BUG=chrome-os-partner:54873
TEST=Boot; stressapptest -M 1028 -s 10000
Change-Id: I7f855960af3142efb71cf9c15edd1da66084e9d8
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 51bfd2abb1aba839bd0b5b85e9e918f3cc4fd94d
Original-Change-Id: Iec9343763c1a5a5344959b6e8c4dee8079cf8a20
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/362822
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16241
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Before entering sleep, ensure that the NFC gpios are configured
correctly to avoid leakage.
BUG=chrome-os-partner:56281
Change-Id: I2bb2e7ba468df445aa5f6c2b22ae0a74fcaa44f6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16243
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Provide a default value of 0 in drivers/spi as there weren't
default values aside from specific mainboards and arch/x86.
Remove any default 0 values while noting to keep the option's
default to 0.
BUG=chrome-os-partner:56151
Change-Id: If9ef585e011a46b5cd152a03e41d545b36355a61
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16192
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Almost all boards and chipsets within the codebase assume or
use SPI flash as the boot device. Therefore, provide an option
for the boards/chipsets which don't currently support SPI flash
as the boot device. The default is to assume SPI flash is the
boot device unless otherwise instructed. This falls in line
with the current assumptions, but it also allows one to
differentiate a platform desiring SPI flash support while it not
being the actual boot device.
One thing to note is that while google/daisy does boot with SPI
flash part no SPI API interfaces were ever implemented. Therefore,
mark that board as not having a SPI boot device.
BUG=chrome-os-partner:56151
Change-Id: Id4e0b4ec5e440e41421fbb6d0ca2be4185b62a6e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16191
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector
code) the reboot counter stored in `reboot_bits` isn't reset on a reboot
with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR
enabled, later stages (e.g. payload, OS) have to clear the counter too,
when they want to switch to normal boot. So change the bits to (h)ex
instead of (r)eserved.
To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also
remove all occurences of the obsolete `last_boot` bit that have sneaked
in again since 24391321 (mainboard: Remove last_boot NVRAM option).
Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/16157
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This reverts commit 462e1413 ("rockchip: rk3399: enable sdhci clk
for emmc")
Enabling this clock in coreboot is no longer needed as it's handled
in the kernel driver now.
BUG=chrome-os-partner:52873
TEST=boot from usb/sdcard and check there is /dev/mmcblk0
BRANCH=none
Change-Id: I92cf51f175fe56a09ab9329b29a27c77ef4328e1
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 5707d1269a253dabf825be120d1f9348ffaab6d0
Original-Change-Id: I8bca870c663d8ce8fac5daaaaf8225489f22ed13
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/367421
Original-Commit-Ready: Brian Norris <briannorris@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16152
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This is a temporary work-around since the current threshold of 70 on
TSR2 results in thermal trip and shutdown while the kernel is
booting. Changing this threshold to 100 allows kernel to boot up to
userspace. Following values were read:
$ cat /sys/class/thermal/thermal_zone4/temp
81800
$ cat /sys/class/thermal/thermal_zone4/type
TSR2
BUG=chrome-os-partner:56155
BRANCH=None
TEST=Boots to OS.
Change-Id: I951553ed4c93b02239a51a0d3036e4a750eea04b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16156
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
|
|
The BOOT_MEDIA_SPI_CHIP_SELECT option is not used in any of the
code. Remove its usage.
BUG=chrome-os-partner:56151
Change-Id: I522b62a2371b8a167ce17c48117669390cda14cd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16185
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15987
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This reverts commit 850e45f19f498eedd80da4a97a5ce641e2cec6d5.
google_chromeec_init() is a weird function that can lead to confusing
behavior. I'm not sure how it's meant to work on the boards that use it,
but it causes problems on Kevin and other non-x86 boards have never used
it either. It doesn't really do anything anyway (the EC works fine
without an initial HELLO), so at best it's just a waste of time... let's
take it back out.
There's also no need to display the current time on every boot... other
boards don't do that and the eventlog already fills the same purpose.
Cut it out to avoid one extra host command overhead.
BRANCH=None
BUG=chrome-os-partner:55995
TEST=Recovery reasons now get correctly propagated across the EC reboot.
Change-Id: Ic3b772780d4d05e362c269969e6e4e7069482bb6
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 103d86e68cd164bea39aa1edc8668d80358edbde
Original-Change-Id: I58fd5e6094e1c8cb6368e7a4569ab9231375fbc9
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/367351
Original-Reviewed-by: Simon Glass <sjg@chromium.org>
Original-Reviewed-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/16153
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
1. Get rid of LBP2 partition
2. Shrink RO size
3. Increase RW-A and RW-B sizes
4. Increase RW_MRC_CACHE size
CQ-DEPEND=CL:366793
BUG=chrome-os-partner:52127, chrome-os-partner:55699,
chrome-os-partner:55778
BRANCH=None
TEST=Compiles successfully. Boots to OS.
Change-Id: Iad41d8cc7697e6d73f1aa2c699b0e8559349b77e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16145
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The Rockchip RK3399 integrates a USB Type-C PHY in charge of things like
SuperSpeed line muxing for rotated cable orientations in the SoC. While
fancy, this is very complicated and we don't want to implement support
for the whole thing in firmware. The USB Type-C standard has
intentionally been designed in a way that the USB 2.0 (HighSpeed) lines
always "just work" in any orientation (by just shorting different pins
in the connector together) so that simple use cases like ours can get
basic USB functionality without much hassle.
However, a semi-configured Type-C PHY can confuse USB 3.0 capable
devices into thinking we're actually supporting SuperSpeed, and fail at
that rather than establishing a reliable HighSpeed connection. This
patch sets enough bits in the Type-C PHY to electrically isolate the
SuperSpeed lines from the connector so that the connected device isn't
going to get any fancy ideas and reliably falls back to USB 2.0.
Also clean up the rest of the USB code while we're at it: avoid writing
a few bits that are already in the right state from their reset values
anyway, or reading values whose content we already know for this SoC.
Rename the USB controllers to the name actually used in the Rockchip
documentation (USB OTGx) rather than the name blindly copied from
Exynos code (USB DRDx).
BRANCH=None
BUG=chrome-os-partner:54621
TEST=Plug a USB 3.0 Patriot Memory stick into both ports in all
orientations, observe how it gets reliably detected now (safe for some
known hardware issues on my board).
Change-Id: Ifce6bcddd69f2e8f2e2a2f48faf65551e084da1e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: c526906f998bf66067d3addb8b3d3a126c188b1e
Original-Change-Id: Ie80a201a58764c4d851fe4a5098a5acfc4bcebdf
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/366160
Original-Reviewed-by: liangfeng wu <wulf@rock-chips.com>
Original-Reviewed-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-by: <515506667@qq.com>
Reviewed-on: https://review.coreboot.org/16125
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This patch adds mainboard_smi_gpi_handler which handles the
SMI event. This can happen in situations like lidclose and
system goes to shutdown.
BUG=chrome-os-partner:54977
TEST=When system is in firmware mode executing the command
lidclose from ec console shuts down the system.
Change-Id: I8ff6001e48dcbbd4cee5097e759352d8fea6189b
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15834
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The write protect GPIO is active high, not active low.
After fixing I can see this after removing the write-protect screw:
$ crossystem | grep wpsw_boot
wpsw_boot = 0
Putting the screw in shows:
$ crossystem | grep wpsw_boot
wpsw_boot = 1
Caution: this CL contains explicit material. It explicitly sets the
pullup on the WP GPIO even though that's the boot default.
BRANCH=None
BUG=chrome-os-partner:55933
TEST=See desc.
Change-Id: I23e17e3bbbe7dcd83e81814de46117491e61baaa
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: e6969f4be42c00c6e88bbb14929cf0454462ad21
Original-Change-Id: Ie65db9cf182b0a0a05ae412f86904df6b239e0f4
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/366131
Original-Tested-by: Brian Norris <briannorris@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16115
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The rush_ryu board was a development platform that never made it into
a product. Remove it as it's not available to anyone.
BUG=chrome-os-partner:55932
Change-Id: Ia3836ff8cade3009730543177a66736ae197572b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16107
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The rush board was a development platform that never made it into
a product. Remove it as it's not available to anyone.
BUG=chrome-os-partner:55932
Change-Id: I0f77bb791491509da7bd9cf25050e01c2f734a2f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16106
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Looks like our hardware guys have decided to change some voltage ranges
in the Gru/Kevin ADC IDs since we last wrote a table. This patch updates
it to the latest values from the Spreadsheet of Truth. Also adds further
values up to rev15.
BRANCH=none
BUG=none
TEST=none
Change-Id: I1aa093ca3abe952afd658eb7da01b325f798eaa0
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: e42b4685c91f01ce1cff61638b17042be9d575fd
Original-Change-Id: I646fd03dc385df1a8f0af8cb85ff3128cc31f8d8
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/365111
Original-Tested-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/16053
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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