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2019-09-28mb/google/drallion: Set UART for console to UART controller 0Aamir Bohra
Drallion uses UART 0 for console, change the config accordindly. BUG=b:139095062 Change-Id: I0ae2f8459b6225b99b758180413afa22386355d4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35633 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26mb/mainboard/hatch: support elan touchpad for AkemiPeichao Wang
Modify IRQ pin from D21 to A21 and support wake-up from touchpad BUG=b:141519690 TEST=build bios and verify elan touchpad works fine Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6cc5b780ffcee24f1f2a04e88c30628ceb5904e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35551 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26google/grunt: add new two DDR source for TreeyaPeichao Wang
new DDR particle: 1. Samung K4A8G165WC-BCWE 2. Hynix H5AN8G6NCJR-XNC BUG=b:139085024 BRANCH=master TEST=rework new source to DUT and re-flash bios to DUT and verify DUT will bring up successfully Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I0d039af53938086733308a081a77a7398e7bf5d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-09-25mb/google/kukui: Add new build target 'Juniper'Hung-Te Lin
Add the configuration 'Juniper' for the new mainboard. BUG=b:137517228 TEST=make menuconfig; select 'juniper' and build Change-Id: I94e3ac7f6de3fecf177e344cb217eaecf6362d69 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-09-25mb/google/hatch: Move SOC_INTEL_COMETLAKE selection to KconfigFurquan Shaikh
All variants of hatch are using Comet Lake and so the selection can be done in Kconfig without requiring each variant to do the same. Change-Id: Ief34296334ede5ba0f5f13381e92427ccc440707 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Andrew McRae <amcrae@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-24mb/google/kohaku: Update DPTF parameters and TCC offset settingSeunghwan Kim
This change applies fine-tuned DPTF parameters and TCC offset setting for kohaku. Also enables EC_ENABLE_MULTIPLE_DPTF_PROFILES for tablet mode. BUG=b:137688474 BRANCH=none TEST=built and verified the setting values Change-Id: I92e268b2e07ca5a04e29bda84ddb8fc21eb23251 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-09-22mb/mainboard/hatch: add spd: 8G_3200 for AkemiPeichao Wang
BUG=b:140545732 TEST=build bios and spd index set to 6, verify DUT bring up normally Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I337b0bdcd37a9c4baacccbc6786968031a41b31e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35511 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-22mb/google/hatch: Add G2Touch Touchscreen supportWisley Chen
Add G2Touch Touchscreen support for dratini BUG=b:141281841 TEST=emerge-hatch coreboot chromeos-bootimage, and check touchscreen work. Change-Id: I0dbde7f8396da6335b22aeb4a9703336e2b862b8 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-09-20mb/google/hatch: Remove GPIO_DRIVER from pen eject GPIO configurationTim Wawrzynczak
A closer read of the EDS indicates that when GPIO Driver mode is selected, GPIO input event updates are limited to GPI_STS only. GPI_GPE_STS updates are therefore masked, and we don't want to enable this behavior. It masks the GPE and does not allow us to see this GPE as a wake source, obscuring the reason that the system woke up. Also switch the IRQ from level-triggered to edge-triggered, otherwise the system will auto-wake from any sleep state when the pen is ejected from the garage. BUG=b:132981083 BRANCH=none TEST=Wake up system from S0ix using pen eject, verify that mosys eventlog shows GPE#8 as the S0ix wakeup source. Wake up system from S3 via pen eject, and verify that the wakeup source shows as GPE#8. Change-Id: If017e12e23134f5cfed7cbb6047cc9badd9bf7e8 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35459 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-20mb/google/hatch: override smbios manufacturer name from CBIWisley Chen
BUG=none TEST=emerge-hatch coreboot, use ectool to write oem name in CBI, and checked smbios manufacturer name. Change-Id: I9be85fbc47031d049b5bd51cfaf6232cab24e9fe Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-19mb/google/drallion: add sku id base on sensor detectionEric Lai
Implementing logic base on sensor detection to determine SKU id. BUG=b:140472369 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5e71ae6b97378b78055735bbf4b6b55ffe38b978 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35366 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-19mb/google/drallion: Add memory init setup for drallionThejaswani Putta
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-09-18mb/google/hatch/variants/helios: Add DPTF control for ambient sensorSumeet Pawnikar
Add DPTF based thermal control for ambient sensor for CML based Helios system. Also, update other sensor names information. BUG=b:139335207 BRANCH=None TEST=Build and Boot on Helios board and check all sensor details. Change-Id: I322d53536fbdf6db70f5a24afb322d9f206eaeac Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-18mb/google/hatch/variants/helios: Update DPTF parametersSumeet Pawnikar
Update DPTF thermal temperature threshold values for CML based Helios system. This updates CPU active cooling temperature threshold to appropriate values which addresses the issue of running the Fan at lower CPU temperature as per bug. Also, added active cooling temperature thresholds for other TSR sensors. BUG=b:141087272 BRANCH=None TEST=Build and boot on Helios board to check the fan functionality. Change-Id: I5c8502f8c9e6121c18024d2a8d5a4f7680797b8d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35446 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18mb/google/octopus/variants/garg: add LTE sku to config power sequenceKevin Chiu
Add SKU#18 to config power sequence below: GPIOs related to power sequnce are GPIO_67 - EN_PP3300 GPIO_117 - FULL_CARD_POWER_ON_OFF GPIO_161 - PLT_RST_LTE_L 1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161 2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67 3. Power reset: - keep GPIO_67 and GPIO_117 high and - pull down GPIO_161 for 30ms then release it. BUG=b:134854577,b:137033609 BRANCH=octopus TEST=build Change-Id: I58e07518f6daaf608684c9fa1b1c88fc592ea117 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-18mb/google/drallion: Add SPD files for drallionAmanda Huang
This change adds SPD files for Drallion. Use spd_index matrix to correspond mem_id. This can save the dummy spd index to reduce the size of SPD.bin. BUG=b:139397313 TEST=Compile successfully Change-Id: I2f7e75fdbca4183bcd730e40fef4bfe280ab900b Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35346 Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18mb/google/drallion: Enable 360 sensor detectionBernardo Perez Priego
Implementing logic to detect SKU model and enable ISH accordignly. BUG=b:140748790 Change-Id: I22fafb43dce6545851883be556a02d65a01fc386 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35303 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18mb/google/drallion: Update gpio config for drallionVarun Joshi
Source: Pin Schematics BUG=b:139370304 Signed-off-by: Varun Joshi <varun.joshi@intel.com> Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35175 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-17google/kukui: Pass reset gpio parameter to BL31Tristan Shieh
To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui and ATF(BL31) can get this parameter. Change-Id: Iefa70dc0714a9283a79f97d475b07ac047f5f3b0 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-16src/mainboard: Remove unused include <device/pci_ops.h>Elyes HAOUAS
Change-Id: Icdbccb3af294dd97ba1835f034669198094a3661 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33528 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-16mb/google/kohaku: Update USB port settingsSeunghwan Kim
This change overrides USB port settings for kohaku. Some port settings are same with baseboard, but I'd like to describe all settings here to be aware of current setting and usage of USB ports on kohaku. BUG=none BRANCH=none TEST=built and measured SI of USB ports internally Change-Id: I5ac05485d1cd94416e5a0aecf7fa6769bd7c9e84 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-15src/mainboard: Remove not used #include <elog.h>Elyes HAOUAS
Change-Id: I901cb35488e08f58cdf97f3a8d0f5a8d03560f86 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33729 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-14arm64: Uprev Arm TF and adjust to BL31 parameter changesJulius Werner
This patch uprevs the Arm Trusted Firmware submodule to the new upstream master (commit 42cdeb930). Arm Trusted Firmware unified a bunch of stuff related to BL31 handoff parameters across platforms which involved changing a few names around. This patch syncs coreboot back up with that. They also made header changes that now allow us to directly include all the headers we need (in a safer and cleaner way than before), so we can get rid of some structure definitions that were duplicated. Since the version of entry point info parameters we have been using has been deprecated in Trusted Firmware, this patch switches to the new version 2 parameter format. NOTE: This may or may not stop Cavium from booting with the current pinned Trusted Firmware blob. Cavium maintainers are still evaluating whether to fix that later or drop the platform entirely. Tested on GOOGLE_KEVIN (rk3399). Change-Id: I0ed32bce5585ce191736f0ff2e5a94a9d2b2cc28 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-13mb/google/hatch: Merge emmc_sku_gpio_table and gpio_table to one tablePeichao Wang
BUG=b:140008849, b:140573677 TEST=verify eMMC SKU and SSD SKU will bring up normally. Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I0c0adf569cc92e8b44ab72379420f2b190fa31f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-09-13mb/google/drallion: Use arcada_ish.bin for arcada_cmlSelma BENSAID
drallion_ish.bin is updated for drallion GPIO changes and not compatible with arcada_cml. TEST=Build and boot arcada_cml Signed-off-by: Selma BENSAID <selma.bensaid@intel.com> Change-Id: Idb35c33425bfd50533df74349dd645db18a65bc5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-09-13mb/google/hatch/var: Increase Goodix touchscreen reset delay to 500msPhilip Chen
Even though GT7375P programming guide rev0.4 only requires a reset delay of 120ms, in practice, we have to increase the reset delay to 500ms, or Goodix FW update would fail. This is a workaround. In the long run, we hope Goodix can fix the power sequence in touch firmware. BUG=b:138795891, b:138796844 TEST=boot helios board and verify Goodix FW update succeeded Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: Ic0049bf240de0a1c7f1b1f39bf155d48bb76fb86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35350 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-12mb/google/drallion: Update memory mapIvy Jian
This will increase ME region size and reduce the BIOS region size. BUG=b:140665483 TEST='compile successfully' Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I5be2580d280569421d0870a06f9b93124b564b6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35304 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-12soc/intel/cnl: Remove unnecessary FSP UPD “PchPwrOptEnable” usageSubrata Banik
PchPwrOptEnable FSP UPD is for internal testing and not really available in externally released FSP source hence assigning this UPD using devicetree config dmipwroptimize doesn't do anything. TEST=Build and boot sarien/arcada. Change-Id: I6da2a088fb697e57d12008fa18bd1764b3da7765 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-09-12mediatek/mt8183: tune EDID for BOE panelPeichao Wang
BUG=b:140545315 TEST=builds Kodama image and verify display working properly Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I52a56f9bbbbef5937a9601f9371e415c74ac9a7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/35317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2019-09-12mb/google/hatch: Configure SATA DEVSLP pad reset config to PLT_RSTAamir Bohra
BUG=b:133000685 Change-Id: Ia12174e3254153dbca55070f5daf84fd8aac51d0 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-09-11src: Remove unneeded include <arch/interrupt.h>Elyes HAOUAS
Change-Id: I3323d25b72dab2f9bc8a575ba41faf059ee1ffc4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-11mb/google/hatch: Create dratini variantWisley Chen
Create dratini variant BUG=b:140610519 TEST=emerge-hatch coreboot, and boot into chromeos on proto board Change-Id: Ied1240d1be831568e4ab4695b893c3f48821f68b Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35285 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-11mb/google/drallion: enable Elan and Melfas touch panelEric Lai
Drallion uses the same touch panel as Sarien. Copy the deivce from Sarien. BUG=b:140415892,b:138082886 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I8e6d2dcf4bd2ed2325137a05811af03692d40342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35305 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-10mb/google/kukui: Enable MT8183_DRAM_EMCPHuayang Duan
MT8183_DRAM_EMCP is enabled for devices using eMCP to run at a high DRAM frequency (e.g., 3600Mbps). BUG=b:80501386 BRANCH=none TEST=Memory test passes on EMCP platform Change-Id: Icf875427347418f796cbf193070bf047844d2267 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34433 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-10mb/google/poppy/variant/nocturne: add EC_SYNC_GPIONick Vaccaro
Setup EC_PCH_ARCORE_INT_L, tied to GPP_D17, and define as EC_SYNC_GPIO.. - change GPP_D17 definition to PAD_CFG_GPI_APIC_INVERT as EC_PCH_ARCORE_INT_L is active low - add EC_SYNC_GPIO to the group of chromeos_gpios for use by depthcharge BUG=b:139384979 BRANCH=none TEST="emerge_nocturne coreboot depthcharge chromeos-bootimage", flash & boot nocturne in dev mode, verify that volume up and down buttons work in the dev screen and that the device boots properly into the kernel. Change-Id: Ia43c622710fde8686c60b836fb8318931d79eb61 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-10mb/google/hatch/variants/helios: Modify FPU power on sequenceFrank_Chu
pull in the FPU VDDIO turn on to fix the power leakage problem on FPU VDDIO and FPU CS during power on sequence. BUG=b:138638571 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I3f6bf3676922e987c2e282b697a2333e2d90289e Reviewed-on: https://review.coreboot.org/c/coreboot/+/34858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-09-10mb/google/octopus: Add a new sku for meepWisley Chen
Add a new sku4 for meep: sku4: Stylus + no rear camera BUG=b:140360096 TEST=emerge-octopus coreboot Change-Id: Icde7f032c0acf7562b5d5f2c6a8b0c2de91c45b2 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-09-10mb/google/kahlee/treeya: Tune I2C bus 1, 2 and 3 clockPeichao Wang
Tune I2C bus 1, 2 and 3 clock and make them meet spec. BUG=b:140665478 TEST==flash coreboot to the DUT and measure I2C bus 1,2,3 clock frequency less than 400KHz Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6b2a51a866e57d13fe528452e4efdcf17a72317f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35298 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-09mb/google/hatch: Distinguish SKU1 and 2 for eMMC and SSD respectivelyPeichao Wang
1. SKU1 for eMMC 2. SKU2 for SSD BUG=b:140008849, b:140573677 TEST=Verify SSD is disabled when SKU ID = 2/4/21/22 Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I827e6f1420801d43e0eb4708b8b8ad1692ef7e9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35204 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-09lib/spd_bin: Extend DDR4 spd informationEric Lai
From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks. Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-09mb/google/drallion: modify USB settingEric Lai
Based on HW schematic to modify USB setting. Drallion has two type C on left and two type A on right. BUG=b:138082886 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I925de209635d92ef61ccb9114efebb4b10f30e87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-09-06mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2Frank_Chu
Applying first tuned DPTF parameters and TDP PL1/PL2 values for helios. BUG=b:138752455 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ic7a96c33ce710c32b57e2ad8066830ff83398c57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-09-05mb/google/octopus: Set sar file name for meep skuWisley Chen
Set meep sar file name by sku number Cq-Depend: chromium:1768380 BUG=b:138261454, b:118782854 BRANCH=octopus TEST=emerge-octopus coreboot, and check wifi_sar-meep.hex Change-Id: I25aa3080392ce277e537c973088dde569246630e Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35211 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-05mb/google/drallion: modify PCIE settingEric Lai
Based on HW schematic to modify PCIE setting. BUG=b:138082886 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia744a6f3cba76c507c1c43b0a981cb6d89c1a40f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-09-05mb/google/octopus: Load custom SAR values by SKU ID for BloogTony Huang
Use sku-id to load the SAR values for Bloog device. BUG=b:138180187 BRANCH=octopus TEST=build and verify load Bloog SAR by sku-id Cq-Depend: chromium:1771477 Change-Id: Id0bc2609fd1c4eaeb380f8f1532ab30d34e2aeb3 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-04mb/google/kahlee/treeya: Update the memory timing table for Treeya to the 2T ↵Peichao Wang
table Rename the table from Liara specific to simply specifying that it's using 2T command rate BUG=139841929 TEST=build and do stress test Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6e10b95c8aea50e68d8a3b710f30dda4f6b807d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-09-04mb/google/kahlee/treeya: override sku_id() functionPeichao Wang
override 'uint32_t sku_id(void)' so that lib_sysinfo.sku_id get a correct value in depthcharge BUG=b:140010592 BRANCH=none TEST=boot treeya board, in depthcharge stage, lib_sysinfo.sku_id print correct value. Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I631f62021e8104a69a43667a811c9c23e3105596 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Magf - <magf@bitland.corp-partner.google.com> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-09-04mb/google/hatch/var/kindred: Update DPTF parameters and TDP PL1/PL2David Wu
Add TEMP_SENSOR_3 to DPTF, Update DPTF parameters and TDP PL1/PL2 values Cq-Depend: chromium:1751304 BUG=b:140127035 TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-ec chromeos-bootimage Change-Id: I1817e277f4641db6bedc8b640b1dc5d57502d5dd Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-09-03mb/google/hatch/var/kindred: Update DRAM IDs for 8G and 16G 3200David Wu
Update DRAM IDs to support 8G and 16G 3200 spds BUG=b:132920013 b:131132486 TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-bootimage Change-Id: I8e55b5e24ee2cefe90472a331e829b073bf0f92a Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-09-02mb/google/drallion: add memory sku idEric Lai
Drallion will use soldered down memory and use GPP_F12 to GPP_F16 indicates mem_id. BUG=b:139397313 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib5ada54fd2b8f358b59de8089e5405cf3e34825a Reviewed-on: https://review.coreboot.org/c/coreboot/+/35133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-09-02mb/google/drallion: Enable HDA for drallion platformAamir Bohra
Enable PchHdaIDispCodecDisconnect and PchHdaAudioLinkHda for drallion variants. This is needed with FSP 1263. Signed-off-by: Selma BENSAID <selma.bensaid@intel.com> Change-Id: I13d3dd832c6fbdc2aad5ba578695edb8470806e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-02mb/google/hatch/var/helios: Increase touchscreen reset delay to 120msPhilip Chen
As per GT7375P programming guide rev0.4, we want to enforce a delay of 120ms after the reset is completed, before HID_I2C starts. BUG=b:140276418 Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: Id69a9db996bcd9001ef850c50898fbd55327b4df Reviewed-on: https://review.coreboot.org/c/coreboot/+/35158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-30mb/google/octopus/variants/garg: update new SKUKevin Chiu
For Garg EVT build, add new SKU ID below: SKU4 LTE DB, touch: SKU ID - 18 SKU5,6 Convertible, 2A2C, Touch, Stylus, rear camera: SKU ID - 37 BUG=b:134854577 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: Iea1d17efb9a5f274f8eefb2aaa683e75ab5de7d2 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-08-30mb/google/kahlee/variants/careena: override DRAM SPD tableKevin Chiu
override DRAM SPD and add new 4 DRAM: Samsung (TH) K4AAG165WA-BCTD Hynix (TG) H5ANAG6NCMR-XNC Micron (TF) MT40A1G16RC-062E:B Samsung (TH) K4AAG165WA-BCWE BUG=b:139912383 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage extract spd.bin and confirm 4 new SPD was added. Change-Id: Ie1b2c1bae5ffe9f3a6a6560348f6e1b117ffd457 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-30google/buddy: adjust CID for realtek audio codecMatt DeVillier
Adjust CID to allow for Windows driver to attach without breaking functionality under Linux. Same change made as to google/cyan (which uses same Realtek RT5650 codec) in commit 607d72b. Test: build/boot Windowns 10 on google/buddy, observe audio drivers correctly attached to codec and Intel SST devices. Change-Id: I839acc8427ee9b5c425885858a513e9b0b9d0f93 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-30mb/google/drallion: change servo board debug to UART 0Eric Lai
Drallion will change debug port UART from 2 to 0. Followed HW schematic to modify it. BUG=b:139095062 BRANCH=N/A TEST=Build without error Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib2bcded8de3c9fb2c0a4ccbd002b1f219bccceb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-08-30mb/google/hatch: Add settings for noise mitgationDtrain Hsu
Enable acoustic noise mitgation for hatch platform, the slow slew rates are fast time dived by 8 and disable Fast PKG C State Ramp(IA, GT, SA). BUG=b:131779678 TEST=waveform test and reduce the noise level. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I49e834825b3f1e5bf02f9523d7caa93b544c9d17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-30mb/google/hatch: Add 16G 3200 generic SPD fileShelley Chen
BUG=b:139792883 BRANCH=None TEST=None Change-Id: I22974b015a40fb7ae592e182cf5da83a8252c031 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-29arch/arm: Make ARM stages select ARCH_ARMArthur Heymans
This removes the need to select ARCH_ARM in SOC Kconfig Also don't define the default as this result in spurious lines in the .config. Change-Id: I1ed4a71599641db606510e5304b9f0acf9b7eb88 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31313 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-29mb/google/drallion: Update memory mapBernardo Perez Priego
This will enable to optionally inject ISH binaries into coreboot. BUG:b:139820063 TEST='compile successfully' Change-Id: I38659460726a3f647cda3bc3efd442f18aea24f0 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-08-29mb/google/drallion: Correct drallion HWID and add HWID for variantsMathew King
The current HWID for drallion is reported as invalid by chrome, generate new valid HWID with the following command and taking last 4 digits. `printf "%d\n" 0x$(crc32 <(echo -n '$1'))` BUG=b:140013681 Change-Id: I410d37fc3f3372e9420d674b65f2c9a704b670f2 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-28google/rambi,intel/baytrail: Simplified romstage flowKyösti Mälkki
Change-Id: I99440539d7b7586df66395776dcd0b4f72f66818 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34964 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28mb/google/hatch/variants: Increase touchscreen reset delay to 120msSumeet Pawnikar
During boot sequence sometime touchscreen reset keeps failing. Also, kernel dmesg shows "dmesg:i2c_hid i2c-GDIX0000:00: failed to reset device" message. This adds around 4 more seconds to the boot sequence. Setting the appropriate delay of 120ms between enable and reset for Goodix Touchscreen helps to synchronize and address this failure. This value is 120 ms as per Goodix Spec. BUG=b:138413748 BRANCH=None TEST=Built and tested on Hatch system Change-Id: I15005c568f285ec7bad9a0bec4498e2fdd20782b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34626 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28google/leon: Add DRIVERS_I2C_RTD2132Kyösti Mälkki
This is LVDS bridge, I assume this was lost while upstreaming or converting boards to variants. Change-Id: I816a6b4035c4e935150cc77089c4224eee719c10 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-08-28mb/google/hatch: Enable Override DLLs for KindredJamie Chen
Enable SOC_INTEL_COMMON_MMC_OVERRIDE for Kindred BUG=b:136784418 BRANCH=none TEST=Boot to OS 100 times on Kindred proto 1 board. Change-Id: I390d237b9119ae42f4b0bb802bf9857552af78bf Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-28mb/google/hatch: Override DLL values for KindredJamie Chen
New emmc DLL values for Kindred BUG=b:136784418 BRANCH=none TEST=Boot to OS 100 times on Kindred proto 1 board. Change-Id: I52acb445c47fcdb9b60512dd501d810b1ae4dc10 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35041 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28mb/google/drallion: remove GBE fileEric Lai
Drallion doesn't have on board LAN, remove GBE bin file config. BUG=b:139906731 TEST=emerge-drallion coreboot chromeos-bootimage and check image-drallion.bin not include GBE region Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifbc295afd8d875b5098b0ce75252b51523a5c76e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-08-28mb/google/drallion: add dummy SPD fileEric Lai
Drallion will use soldered down memory. Add dummy spd file. BUG=b:139397313 BRANCH=N/A TEST=Build and check cbfs has the dummy spd.bin Change-Id: Ife59c2dd689d72b117f30e832a3ce7eed4fa4220 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35113 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28mb/google/poppy/variant/nami: add sku ids of bard/ekkoRen Kuo
add sku ids of bard/ekko BUG=b:139886622 TEST=emerge-nami coreboot Change-Id: Iabc3d587c3839e4a3121cea8504c50e2dc4f9699 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35115 Reviewed-by: Vincent Wang <vwang@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26soc/intel: Use common romstage codeKyösti Mälkki
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26Split MAYBE_STATIC to _BSS and _NONZERO variantsKyösti Mälkki
These are required to cover the absensce of .data and .bss sections in some programs, most notably ARCH_X86 in execute-in-place with cache-as-ram. Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26google/kukui: Enable CHROMEOS_USE_EC_WATCHDOG_FLAGYu-Ping Wu
Kukui AP doesn't remember if the last AP reset was due to AP watchdog. We need to enable CHROMEOS_USE_EC_WATCHDOG_FLAG so that it will query the reset reason from EC. BUG=b:109900671,b:118654976 BRANCH=none TEST=1. run 'mosys eventlog clear; stop daisydog; echo > /dev/watchdog' 2. wait for watchdog reset 3. check 'mosys eventlog list | grep watchdog' Change-Id: I053cc7664bbaf0d3fcae26ba9481a0ad700dca90 Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-26google/link: fix detection of dimm on channel 1Matt DeVillier
Changes to the sandybridge memory init code (both MRC and native) now require SPD data on all populated channels in order for dimms to be detected properly, so copy spd_data[0] to spd_data[2], as LINK always has 2 channels of memory down. Test: boot google/link, observe onboard RAM correctly detected on both channels Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-08-24mb/google/octopus: Re-assign sku number for vortininjaWisley Chen
Re-assign sku number for vortininja. BuG=b:138177049 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: I3166a635151fcc7b2e3c0122fa05925cfa5df7d0 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-23mb/google/hatch/var/kindred:: Add enable signal for touch screenPhilip Chen
In the next board version, we will use GPP_D9 as enable control for touch screen. BUG=b:137133946 TEST=build Change-Id: I213d0878bfca1ce4059ec0393f59d8e79e1b274c Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-23mb/google/hatch/variants/kindred: Remove unused devicesPhilip Chen
sx9310 and FPMCU are not used in Kindred. BUG=none TEST=build Change-Id: Ied09d4bdb899d991131a75d7c848ff8637022f53 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-23mb/google/rambi: update GPIO, RAM config for clapperMatt DeVillier
When upstreamed, GPIO and RAM config for clapper variant was taken from an older branch, leading some boards to fail to boot. Update based on chromium branch firmware-clapper-5216.199.B, commit 362d845 [baytrail: implement baytrail technical advisory 556192] Change-Id: I099ee2cd0833e4b9ab093663c4549c79ec044127 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-23Revert "mb/google/octopus: Disable WLAN prior the entry of S5"Kane Chen
This reverts commit 38dbd6892080c93ccd24fbfa46ed5d9bdb7d9e99. Reason for revert: ODM helped to verify w/ BT runtime suspend disabled + revert this change And issue is gone. so I revert this change see the test result in https://partnerissuetracker.corp.google.com/issues/136039607#comment32 Change-Id: I248e9613cc39247a2bb88270c234c7d36d0ff60f Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-08-23mb/google/drallion: Add two variants - arcada_cml & sarien_cmlThejaswani Putta
These variants are to support the sarien and arcada boards with CML SOC, the drallion variant will be used to support the upcoming drallion board. Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I766bdccb6f8b6924d6ae1abbe57035f4ff1f6f17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-08-23mb/google/kukui: Add panel for KodamaPeichao Wang
Declare the following panel for Kodama: - AUO B101UAN08.3 BUG=b:139699622 TEST=builds Kodama image and working properly Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I3f688ffd0ece6afac08d353ab5a6cf1cf876b32f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35001 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-22mb/google/kukui: Add flapjack panelsHung-Te Lin
Add panels supported by flapjack. Change-Id: I547bf6f26bdbfed52a00c8cfb268d4e7c17ed889 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-21mb/google/kukui: Move panel description to CBFS filesHung-Te Lin
The panel description may be pretty large (for example, 1.3k for BOE TV101) due to init commands and we should only load the right config when display is needed. BUG=None TEST=make -j; boots and see display on Krane. Change-Id: I2560a11ecf7badfd0605ab189d57ec9456850f75 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-21mediatek/mt8183: add scp voltage initializationHsin-Hsiung Wang
Add scp voltage initialization. BUG=b:135985700 BRANCH=none Test=Boots correctly on Kukui and scp can boot up normally Change-Id: I5afb60af3c14490e20f28f1c089cfca42ddf7fcf Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-21arch/x86: Rename some mainboard_romstage_entry()Kyösti Mälkki
These platforms use different signature for this function, so declare them with different name to make room in global namespace. Change-Id: I77be9099bf20e00ae6770e9ffe12301eda028819 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34909 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21mb/google/kohaku: Correct DPTF temp sensor IDsSeunghwan Kim
This change corrects DPTF temperature sensor IDs BUG=none BRANCH=none TEST=none Change-Id: I25c76b0e938b2568da1833a4a5685ed36c00275e Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-21mb/google/octopus/variants/bloog: Add G2Touch touchscreen supportTony Huang
Add G2Touch touchscreen support for blooglet. BUG=b:139725457 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage, and check touchscreen by evtest. Change-Id: I6ebcc60f58857d8b28446932787742c2740fadd8 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-21mb/google/kahlee/treeya: Update Raydium TS device ACPI nodesChris Wang
Update I2C irq to EDGE trigger for Raydium TS. BUG=b:135551210 BRANCH=master TEST=emerge-grunt coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ic0a00a31eefa756b6e4ee9aac8d25c1be5ac9195 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-21mb/google/kahlee/treeya: remove keyboard backlight supportChris Wang
Treeya doesn't support the keyboard backlight. BUG=b:135551210 BRANCH=grunt TEST=emerge-grunt coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I02dfc77d3cb7ac00b3f10d577d92775db99c1bdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/34903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
2019-08-21mb/google/kahlee/treeya: Use GPIO_10 for EC_SYNC_IRQChris Wang
Use AGPIO 10 as the EC sync interrupt for MKBP events for sensor data. Reference to Aleena project. BUG=b:135551210 BRANCH=grunt TEST=emerge-grunt coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ie0b719ebce90710bca2109b7ff255e19329f9cac Reviewed-on: https://review.coreboot.org/c/coreboot/+/34902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
2019-08-21mb/google/kahlee/treeya: Add EC_ENABLE_TBMC_DEVICEChris Wang
Enable ACPI TBMC notification on tablet mode change to support convertible treeya devices. BUG=b:135551210 BRANCH=grunt TEST=emerge-grunt coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Id0618c8df66267b88008dc5057892de6b530629f Reviewed-on: https://review.coreboot.org/c/coreboot/+/34899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
2019-08-21mb/google/kahlee/treeya: Enable Synaptics touchpad andPeichao Wang
Synaptics touchscreen BUG=b:139699619 TEST=emerge-grunt coreboot chromeos-bootimage flash bios image to DUT and make sure the touchpad and touchscreen can work Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I002badd49e678e1c32c802352923ca51efb45cef Reviewed-on: https://review.coreboot.org/c/coreboot/+/35000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-20mb/google/hatch: Skip SD card controller WP pin configuration from FSPAamir Bohra
BUG=b:123907904 TEST=SD WP GPIO PAD retains coreboot configuration and FSP ScsSdCardWpPinEnabled UPD is set to 0. Change-Id: I30367cda09cc8c88abb649f70b4587889083f9af Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34901 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20mb,autoport: Fix GCC 9 Port_List build errorJacob Garber
Port_List is an array of 8 elements, and GCC 9 is warning that there are no 'others' when all 8 elements are explicitly initialized, which is causing the build to fail. Remove the 'others => Disabled' clause to silence this. Change-Id: Id082e7a76641438f3fb4c4d976dbd254a7053473 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34918 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20mb/google/{eve,glados}: Copy channel arrays separatelyJacob Garber
DqByteMapCh0 and DqByteMapCh1 are declared adjacently in the FSP_M_CONFIG struct, so it is tempting to begin memcpy at the address of the first array and overwrite both of them at once. However, FSP_M_CONFIG is not declared with the packed attribute, so this is not guaranteed to work and is undefined behaviour to boot. It is cleaner and less tricky to copy them independently. The same is true for DqsMapCpu2DramCh0 and DqsMapCpu2DramCh1, so we change those as well. Change-Id: If394f14c4a39d6787ae31868241229646c26be7a Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1365730, 14013{38,39,40,42,43} Reviewed-on: https://review.coreboot.org/c/coreboot/+/33066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-20mb/google/kohaku: Use level trigger for touchscreen interruptSeunghwan Kim
Level trigger is recommended setting for touchscreen interrupt of kohaku, so we would change it as the recommedation. BUG=b:139179200 BRANCH=none TEST=Verified touchscreen works on kohaku Change-Id: Ibbcdbe3ab555d014048f66ff527e539c5b566187 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-20google/stout: Use MAYBE_STATICKyösti Mälkki
Change-Id: I11027acb11a4656536384134d0caebd14b63770c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-20google/butterfly: Replace use of __PRE_RAM__Kyösti Mälkki
Change-Id: Iae944b589d587b30826e935feae029aa8d07d5d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-19google/rambi: Replace __PRE_RAM__ with ENV_ROMSTAGEKyösti Mälkki
Change-Id: I9d86f8475221b52ccdb45cdeaf538e85ab7a17c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-19mainboard/google: Remove use of __PRE_RAM__Kyösti Mälkki
Change-Id: I2ebeb393e4a5a4bfac8a37a877d067aca484ca2e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-18cpu/intel: Enter romstage without BISTKyösti Mälkki
When entry to romstage is via cpu/intel/car/romstage.c BIST has not been passed down the path for sometime. Change-Id: I345975c53014902269cee21fc393331d33a84dce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 15:22:54 +0000