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kconfig incorrectly builds fatcat instead of feilino.
Modify the kconfig file to successfully compile felino.
BUG=b:379797598
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_FELINO
2. Run part_id_gen tool without any errors
Change-Id: Icd76fa97b9879d8f90ae9ee13998b6667f10b39c
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85315
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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Modify overridetree based on the schematics revision 20241120.
BUG=b:379797598
TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino
Change-Id: I40362b5c823144b6ab0acb878e58b4f5a295bbdd
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The TCSS configuration now relying on the PD<->PMC communication
for the fatcat board.
This removes the need to override the `TcssAuxOri` UPD setting.
TEST=Booted fatcat successfully. Verified USB-C device detection and
functionality on both TCSS#0 and TCSS#1 ports.
Change-Id: I37d5c6fe68ad529b4da46aad460e5c1bf92179a8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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Add/update FP enable/disable based on SKU ID. This is meant
to resolve a UMA issue with devices that had the FPMCU populated on
non-fp devices. Since the FPMCU is present, and the firmware enables
the power GPIO's based on variant, not SKU, the devices were reporting
data on fingerprint errantly. Specify the SKUs which should not have a
FP sensor and default to true to maintain the legacy behavior for
undefined devices and limit risk. Variants which do not have FP SKUs
will be unaffected.
BUG=b:354769653
TEST=Flash to zork, test FP.
Disable test SKU, flash on zork, test FP.
To test, run `ectool --name=cros_fp version` in the shell
When enabled, the fpmcu fw version should be displayed.
When disabled, an error should be displayed because the fpmcu
is inaccessible.
Change-Id: Ic6dc71013a1c0d5ee5263109eed87a1b31800232
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85294
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow schematic(ver.1122A), set GPP_V14 to NC.
BUG=b:380218793, b:366291025
TEST=emerge-rex coreboot pass
Change-Id: I91abc4e07836abb163c8bb28d54a711d2b25375d
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add LAN RTL8125BG related settings based on schematic(ver.1122A).
BUG=b:380218793, b:366291025
TEST=emerge-rex coreboot pass
Change-Id: Icc24f00406d5f91e38725588109c61b7bad099c3
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85322
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update following fw_config settings:
+-----------+-------------------------+----------------------------+
| Bit 0-1 | DB_USB | 0 --> DB_USB_UNKNOWN |
| | | 1 --> DB_2USBA |
+-----------+-------------------------+----------------------------+
| Bit 2-3 | RETIMER | 0 --> INTEL_HAYDEN_BRIDGE |
+-----------+-------------------------+----------------------------+
| Bit 4-6 | AUDIO | 0 --> ALC5682I_ALC1019 |
+-----------+-------------------------+----------------------------+
| Bit 7-8 | FAN | 0 --> ABSENT |
| | | 1 --> PRESENT |
+-----------+-------------------------+----------------------------+
| Bit 9-10 | MIPI_CAM | 0 --> UF_CAM_HI556 |
+-----------+-------------------------+----------------------------+
| Bit 11-12 | FP_MCU | 0 --> FP_MCU_ABSENT |
| | | 1 --> FP_MCU_NUVOTON |
+-----------+-------------------------+----------------------------+
| Bit 13 | WIFI_TYPE | 0 --> WIFI_CNVI |
| | | 1 --> WIFI_PCIE |
+-----------+-------------------------+----------------------------+
| Bit 14 | KB_TYPE | 0 --> KB_TYPE_DEFAULT |
| | | 1 --> KB_TYPE_CA |
+-----------+-------------------------+----------------------------+
| Bit 15 | PANEL_PWRSEQ_EC_CONTROL | 0 --> WIFI_CNVI |
| | | 1 --> DISABLE |
+-----------+-------------------------+----------------------------+
| Bit 16 | KB_BACKLIGHT | 0 --> KB_BACKLIGHT_ABSENT |
| | | 1 --> KB_BACKLIGHT_PRESENT |
+-----------+-------------------------+----------------------------+
BUG=b:377377766
TEST=emerge-rex coreboot pass
Change-Id: Ic6ab99a05cd6d995dc71b39e002c8ad5b1dafc4a
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85293
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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BUG=b:366291025
TEST=emerge-rex coreboot pass
Change-Id: I8a9de4098739cbcdc09f2ec685c374bee3c236a7
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85248
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch refactors the configuration of GPP_E07 (EC_SOC_INT_ODL) to
accommodate the fatcat_ish variant
The GPP_E07 is not connected on google/fatcat variants using the
Microchip EC AIC.
BUG=b:370984186
TEST=Able to build fatcat/fatcat_ish w/o any error.
Change-Id: I88bd76b2110b4c0742569f1ccb2030ea516b3782
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85223
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Adjusts the EC host command range for the fatcat_ish variant
to 0x800-0x807 & 0x200-0x20f.
This change is necessary because the microchip EC used on the Fatcat
board has a smaller host command range than the ITE/Nuvoton ECs used
on other Fatcat variants.
without this patch:
[SPEW ] LPC: Trying to open IO window from 800 size 8
[ERROR] LPC: Cannot open IO window: 800 size 8
[ERROR] No more IO windows
with this patch:
[SPEW ] LPC: Trying to open IO window from 800 size 8
BUG=b:370984186
TEST=Able to build fatcat/fatcat_ish w/o any error.
Change-Id: I0d726d60d2a15d2dfaff35f570de479fdc6d15aa
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch adds the "fatcat_ish" board to the fatcat Kconfig.
BUG=b:370984186
TEST=Able to build fatcat/fatcat_ish and verify the correct configs
selected in coreboot.config
Change-Id: I8a49ce54e946dfdfad253ff946da1b37ed50dd0a
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85220
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure memory according to schematics revision 20241120.
BUG=b:379797598
TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino
Change-Id: I8420c5cf0421ec9265613c3e1374542a067ce6ed
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85320
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Pass SD card detect GPIO to payloads for SD card detection.
BUG=b:317009620
TEST=build pass
Change-Id: I1901fd45833f2415c61b61f9e04ebb54440df80a
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85250
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The RAPL PL1 limit and MMIO PL1 max values should be set as per
silicon TDP as specified in the PDG doc#646929.
BUG=b:378623372
TEST=Build and boot on Trulo board.
Verified PL1 value is updated in DTT and sysfs interfaces.
Output with 15W silicon as below:
cd /sys/class/powercap/
cat intel-rapl/intel-rapl\:0/constraint_0_max_power_uw
15000000
cat intel-rapl/intel-rapl\:0/constraint_0_power_limit_uw
15000000
cat intel-rapl-mmio/intel-rapl-mmio\:0/constraint_0_max_power_uw
15000000
cat intel-rapl-mmio/intel-rapl-mmio\:0/constraint_0_power_limit_uw
15000000
Change-Id: I798c4f10e10a579f470e00dbdb77a84619ad796a
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85184
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Update the TSR1 target's source to CHARGER in Passive Policy.
BUG=b:378623372
TEST=Build and boot on Trulo board.
Verified the source for TSR1 is updated to Charger in Passive Policy
Change-Id: I43db616fd48fc4659dcba359f17854e14adb6039
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Configure GPIOs according to schematics revision 20241120.
BUG=b:379797598
TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino
Change-Id: I4e9e81af9c3d8807e65ecd552e73305c1d109a2d
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85234
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
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Create the uldrenite variant of the brya reference board
by copying the template files to a new directory named
for the variant.
BUG=b:376781355
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_ULDRENITE
Change-Id: Ife666c6f2fe69643033e2ce3b299e7414e16eef1
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85207
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit c89ccaf2816a781ae0acb997557aed7d8cf10b7c.
Reason for revert: b:378775630#comment11
Intel believes that the AC only issue should be addressed head-on and
the previous power limit default settings should be maintained.
BUG=b:378775630
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I9f8344288a1811bddce702c16a244e3d4a59f195
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85276
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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The CSE sync in the payload would allow CrOS devices to render the user notification when updating. Currently, CrOS devices typically take 8-20 seconds to do a CSE sync.
BUG=b:380220737
TEST=Able to build and boot google/fatcat.
Change-Id: I8f1dd2e153ed0f1e671699002cf34a58d758ce2f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85233
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add entries in overridetree.cb required for exposing fan control via
ACPI, which is used then by acpi-fan driver in Linux kernel. This
includes:
1. Fan duty-cycle/rpm table. The RPM numbers were adjusted to the values
reported by ACPI on different duty cycle levels.
2. Dummy Active DPTF policy. This is required to mark the TFNx devices
as active and therefore let the acpi-fan driver probe.
BUG=b:358089775
TEST=Build and flash on redrix and check /sys/class/thermal for TFN1
Change-Id: Iaeffe8bc48cd8cd800efa7be29ec81447ecf2935
Signed-off-by: Stanislaw Kardach <skardach@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85175
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add a variant specific S0ix hook to fill the SSDT table to disable and
enable camera during suspend and resume respectively. For safety concern,
our client LENOVO want us to follow the Boten project to create the function.
BUG=b:378525209
TEST=Build Pujjoga BIOS image. Ensure that camera is disabled during
suspend and enabled during resume. Do the powerd_dbus_suspend and
measure the camera power 3.3V which is disable. And resume will recover.
Change-Id: I7c7f5d314e8b2a4d5f72c452128f6c4b57c45993
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85133
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow latest schematics MB_SCH_1102A to add the DQ map.
BUG=b:372395010
TEST=emerge-fatcat coreboot
Change-Id: I2ea0c5a07d83df108e41fc838e702b793c878096
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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Change the ram_id to 1 for MT62F2G32D4DS-020 WT:F based on the
hardware schematic MB_SCH_1102A.
BUG=b:372395010
TEST=Run part_id_gen tool and check the generated files.
Change-Id: I8cf0e65036c2da7641f29b2975dece718f7c83e3
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85206
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This commit enables the UFS controller on the Google Fatcat mainboard
based on FW_CONFIG.
This change allows the system to utilize the UFS storage device.
TEST=Built google/fatcat with UFS enabled.
Change-Id: Ib32523e7865b2ea23d990b2cf9b7406a4d6ecde3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85192
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Add initialization of DPM drvier for DRAM low power mode. This DPM flow
adds 3ms to the boot time, making the total boot time 860ms.
coreboot logs:
CBFS: Found 'dpm.dm' @0x19880 size 0x5b7 in mcache @0xfffdd1fc
mtk_init_mcu: Loaded (and reset) dpm.dm in 0 msecs (1888 bytes)
CBFS: Found 'dpm.pm' @0x19ec0 size 0x7fb5 in mcache @0xfffdd258
mtk_init_mcu: Loaded (and reset) dpm.pm in 3 msecs (43844 bytes)
TEST=Build pass. Check with cbmem -1.
BUG=b:317009620
Change-Id: Ib855e133a30067fc89c88d5c0fb454cc78504ff3
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85122
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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MT8196 equips new DPM hardware which is different from precedent SoCs.
Therefore, we need implement a new DPM loader (said version 2) to run
the blob. Considering the version iteration, rename the original dpm to
dpm_v1.
TEST=Build pass.
BUG=b:317009620
Change-Id: I07afb8f5c23e96aad3c6cb0887cb7efd16ebf296
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Initialize and calibrate DRAM in romstage.
DRAM full calibration logs:
dram_init: dram init end (result: 0)
DRAM-K:
Fast calibration passed in 1119 msecs
TEST=Full calibration pass.
BUG=b:317009620
Change-Id: Ibb18675caa11a828d27860eeab48c49acf6b938d
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85120
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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1. Add DB_HDMI_LTE 5 on DB_USB fw_config .
2. Due to refer Nivviks, used GPP_A20/GPP_E20/GPP_E21 as default
to set for NF1. Moreover, set to disable HDMI to NC when
fw_config not for DB_HDMI_LTE.
3. Set related DB_USB fields to probe correct devices.
BUG=b:369509276
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: Ic5e3b596ff3681f79f31c262e9e59d163e471e3c
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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The power limit parameters were defined for 378775630#comment5
by the power team.
BUG=b:378775630
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I069869fa01dc157cf2544e72468f43ce1bb64035
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85209
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lei Cao <caolei6@huaqin.corp-partner.google.com>
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Add RAM ID for DDR MICRON MT62F1G32D2DS-023 WT:B
BUG=b:378821948
BRANCH=None
TEST=boot to kernel success
Change-Id: I22e00cffaf6007c64d0c9ffa5f5dde528e3d8952
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Lei Cao <caolei6@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Remove "include <bootstate.h>" when it is not used.
Change-Id: Ic27acf9f8dfbbccb8f48a139032b1463e7185030
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85216
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the felino variant of the fatcat reference board by copying
the fatcat files to a new directory named for the variant.
BUG=b:379797598
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_FELINO
2. Run part_id_gen tool without any errors
Change-Id: Iff7989c19e775d65d5fb04aa4489854150390a35
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85185
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change removes the GPIO configuration for Type C DP HPD, as the
Type C port does not require HPD setup.
BUG=b:366156678
TEST=Build and boot google/orisa. Test Type C port for external usb and
DisplayPort functionality.
Change-Id: I59ec5c19dbbd053bda25f4260321220524d785b3
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This change removes the GPIO configuration for Type C DP HPD, as the
Type C port does not require HPD setup.
BUG=b:366156678
TEST=Build and boot google/trulo. Test Type C port for external usb and
DisplayPort functionality.
Change-Id: Iad602c9a15c65d37a37d06d486843f45e341b6bc
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85180
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch calls `xhci_host_reset()` function to perform XHCI
controller reset. This is proactively pulled in to avoid any potential
timeouts when PMC sends an IPC command to disconnect the active USB
ports.
BUG=b:364158487
TEST=Build Brox BIOS image and boot to OS. Perform warm reset, cold
reset and suspend/resume cycle.
Change-Id: I33fd3aa13e81c7b1ae1ebf6674cc8ac1437ecc03
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
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Remove <assert.h> when it is not used.
Change-Id: Icb8ee7dcfd05e0a3131d02d1bc8fe150bbf9527b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85164
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Add RAM ID for DDR Hynix H58G56BK8BX068
BUG=b:378821948
BRANCH=None
TEST=boot to kernel success
Change-Id: I4c4ad191a5e9703ee0f3bed150c816bfb098daf5
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85117
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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BUG=b:366291025
TEST=emerge-rex coreboot pass
Change-Id: Ie76b20cab9e15a1944451697ebf243c0f0cc4740
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Add support for Realtek audio codec ALC5682I-VS and Realtek audio amp
ALC1019.
BUG=b:366291025
TEST=emerge-rex coreboot pass
Change-Id: I0cac934004b0b1b72feaacea99a602fffd2f1457
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85100
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update initial overridetree settings, it's basically copied from karis.
This patch includes:
1. USB port related settings
2. Display Port Configuration
3. DPTF settings
4. PCIE settings for NVME
5. Settings of MIPI camera HI556
6. Settings of ELAN9004 touchscreen
7. Settings of ELAN and PIXA touchpad
8. PCIE settings for WLAN card
9. Settings of NUVOTON FPMCU
BUG=b:368501705
TEST=emerge-rex coreboot pass
Change-Id: I468ca388f495b2e527841145f8162b21074058cc
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Initial GPIO config for kanix, it's copied from karis.
Will update more GPIO config in future.
BUG=b:368501705
TEST=emerge-rex coreboot pass
Change-Id: Id23b836b48925a30b212b444c9f51cfd6166b9f8
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85042
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add kanix supported memory parts in mem_parts_used.txt, generate
SPD id.
1. MICRON MT62F1G32D2DS-023 WT:B
2. HYNIX H9JCNNNBK3MLYR-N6E
3. HYNIX H58G56BK8BX068
4. SAMSUNG K3KL8L80CM-MGCT
5. MICRON MT62F512M32D2DR-031 WT:B
BUG=b:378390643
TEST=Use part_id_gen to generate related settings
Change-Id: I6ce92bac8d8e7ed64135c26387f52b7cc488c391
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85040
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add override devicetree based on schematic_20241104.
BUG=b:376245884
TEST=emerge-fatcat coreboot
Change-Id: I8a50ca095922cdd67c3f2b13e4727608c3644d86
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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1. Select BOARD_GOOGLE_BASEBOARD_FATCAT for francka.
2. Set VARIANT_DIR to BOARD_GOOGLE_FRANCKA for francka.
3. Set TPM I2C bus to 0x01 for francka.
BUG=b:377819511
TEST=emerge-fatcat coreboot
Change-Id: I5890a1f02ef88c591973c71a2adb2bba889733e7
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85115
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure GPIOs according to schematics_20241112.
BUG=b:377819511
TEST=emerge-fatcat coreboot
Change-Id: I759df174a47a08319c1ada649d8bfb6f64b5aecd
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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GPE route for GPE0_DW0 was not being programmed (i.e. 0) which made it
route to GPP_B since a value of 0 means GPP_B. GPE route for GPE0_DW1
is also being programmed to GPP_B which makes the overall configuration
invalid.
The fix is to program the GPE0_DW0 route to a GPIO group which is not
already being used for GPE0_DW1 & GPE0_DW2 i.e. GPP_A.
Additionally, the common GPE route configuration is moved to baseboard.
BUG=b:378455259
TEST=Verify wake from S0ix when charger is connected
Change-Id: I674cf7db160b6bc1ec3d620f9c99ea91041c48bb
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85157
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Remove unused include <console/console.h>.
Change-Id: I2a7cafd7b755a5c3e2bbfa9fc814bf2686c1ccf1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85163
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Fn key on telith emits a scancode of 94 (0x5e).
BUG=b:372506691
TEST=Flash telith, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: Ib69af9a8448312b275de46f9c835f8a9d592312a
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85045
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The DPTF parameters were defined by the thermal team.
Based on thermal table in 377955793#comment2
BUG=b:377955793
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I7cb44a707d7a87f5caaf259b069a21826f5c0a2e
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch refactors the configuration of GPP_E07 (EC_SOC_INT_ODL) to
accommodate different hardware configurations.
Specifically, GPP_E07 is not connected (NC) on google/fatcat boards
with the Microchip EC AIC. However, it is required for google/fatcat
boards with Nuvoton/ITE AICs.
BUG=b:378603337
Change-Id: I540ba1feadc962866be16d44d2ad607fd0e97ad2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85106
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The current WWAN(LTE) does not require any sar setting from RF team's
suggestion, and sar sensor will be removed from DVT schematic.
To reserve the extendibility, add the fw_config DB_1A_LTE_SAR:
field DB_USB 11 12
option DB_1A 0 (None LTE)
option DB_1A_LTE 1 (LTE without sar sensor)
option DB_1A_LTE_SAR 2 (LTE with sar sensor)
end
Base on the fw_config to enable/disable related functions:
0)Disable WWAN and Sar if DB_USB = DB_1A
1)Enable WWAN and disable sar sensor if DB_USB = DB_1A_LTE
2)Enable WWAN and Sar sensor if DB_USB = DB_1A_LTE_SAR
BUG=b:375341992
TEST=Build and verify on jubilant by DB_USB= 0,1,and 2 of fw_config
Check sar sensor and WWAN module from commands:
ls -l /sys/bus/i2c/devices
i2cdetect -y -r
lsusb
Change-Id: If9231ac8df94e1dc514ecf0780c99adbfb902893
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85107
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Create a new config option to indicate that a board has Google Strauss
keyboard. The scan code for Fn key will be set to 94 if the new config
is selected.
Previously each board was setting the integer config option for Fn key
scan code which was not scalable. The new option is a bool and can be
easily selected by different boards.
BUG=none
TEST=Verify coreboot.config before and after this change.
Change-Id: I2b5d54879d415e4403b2d7948432bb06ab983b86
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85109
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We use ALC256 as HDA codec on francka, add the verb table.
BUG=b:370668037
TEST=emerge-fatcat coreboot
Change-Id: I579c9fd23c763d6791944732889021ffa03da448
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85036
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds support for the ALC721 codec in the device tree
and enables it based on the fw_config.
BUG=b:368495490
TEST=Boot on google fatcat board
Change-Id: If5ca1502942f0ca009db398589c4a243d9e2804c
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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When we use PCIE wifi7, CNVI BT and BT offload should be turned off.
BUG=b:378053901
BRANCH=None
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I0adc446220051da59560c9a59d6f334b3a11ac7b
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Pass the reset gpio parameter to BL31 to support SoC reset.
BUG=b:334753311
TEST=run reboot command
Change-Id: I4ddecfb8f36a8f721b57ca16e6a861f933b058b4
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84933
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Add Google Ti50 TPM support
2. Configure I2C speed to I2C_SPEED_FAST_PLUS
3. Pass GPIO_GSC_AP_INT_ODL to the payload
4. Configure IRQ type to IRQ_TYPE_EDGE_RISING for now
BUG=b:317009620
TEST=build pass, boot ok and there is no CR50 TPM timeout log
Pass log:
[INFO ] Probing TPM I2C: done! DID_VID 0x504a6666
[DEBUG] GSC TPM 2.0 (i2c 1:0x50 id 0x504a)
Change-Id: I582f010a9033ccb1771dbb3ccab9f16314628796
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84932
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Rauru has MT8196 SoC. Following previous MediaTek SoCs, MT8196 will
enable CACHE_MRC_SETTINGS, in order to store the DRAM parameters in the
FMAP section RW_MRC_CACHE. As the size of the MT8196 parameters is
larger (15968 bytes) compared to previous SoCs (7616 bytes), enlarge
RW_MRC_CACHE from 8K to 16K.
TEST=Build pass
BUG=b:317009620
Change-Id: I35aad5a3a82686a68dd66e993355aa32cc19043e
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85094
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Due to the hardware limitation on francka, reduce the memory speed to
7467 MT/s.
BUG=b:373394046
TEST=emerge-fatcat coreboot
Change-Id: I9c45c90952e20fc96943df03f591075338624e88
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85102
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Brox mainboard does not reliably support S3 entry/exit. Hence do not
select HAVE_ACPI_RESUME config option. Also trigger a fail-safe board
reset if the system resumes from S3.
BUG=b:337274309
TEST=Build Brox BIOS image and boot to OS. Ensure that the _S3 name
variable is not advertised in the DSDT. Trigger a S3 entry and ensure
that on S3 exit, the board reset is triggered.
Change-Id: Ief0936fbcd9e5e34ef175736a858f98edf840719
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add Elan touchscreen override devicetree for rull based on the latest
schematic NB7559_MB_SCH_V1_2024_1010.pdf.
BUG=b:374629673
BRANCH=None
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. touchpanel function is normal and 'evtest' command displays the
touch point
Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85015
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Reduce stop delay for touchscreen based on the latest spec (EKTH6915
Product Spec_V1.0). This will optimize the touch response time to keep
the S0ix resume time under 500ms.
BUG=b:378012214
TEST=Verify improvement in resume time on Riven.
Change-Id: Id7dcbc393bfae9bb62b5700bb9042a543152e968
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85039
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca96
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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As per commit 05a13e7ed9b9 ("sconfig: Move (WEAK_)DEV_PTR from device.h
to static.h"), sources that require access to devicetree static devices
should directly include static.h. This allows static.h to be removed
from device.h, eliminating unnecessary dependencies on the devicetree
for objects that only need the device types and function declarations.
The DEV_PTR macro resolves to names declared in static_devices.h, which
is then included in static.h, so include the header whenever the macro
is used.
Change-Id: I05662e601af00866b7f26f4c6c6794b491bf676e
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84678
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds support for the Integrated Sensor Hub (ISH) on the
Fatcat mainboard.
ISH can be enabled or disabled via FW_CONFIG bit 24. This allows for
flexible configuration depending on the system requirements.
The GPIO configuration for ISH is also updated based on CBI settings,
ensuring correct initialization and communication.
Verified that the device tree correctly probes ISH based on the
FW_CONFIG setting:
* FW_CONFIG with bit 24 set: ISH is probed successfully.
* FW_CONFIG with bit 24 cleared: ISH is not probed.
BUG=b:370984186
TEST=Verified ISH probing behavior with different FW_CONFIG settings
using CBI.
Change-Id: I1a9734139a49be982a7dd43d5afd92e7fea6b29c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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1. Configure ChromeOS EC
2. Pass GPIO_EC_AP_INT_ODL to the payload
TEST=build pass
BUG=b:317009620
Change-Id: I20828eee93975e75dfb777fe29d5e1c3454b5059
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84931
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
Follow the power team’s recommendation:
- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to SLEW_FAST_4
- Set FastPkgCRampDisable VCCIA and VCCGT to 1
BUG=b:376165743
TEST=built firmware and verified by power team,
the acoustic noise can be improved a lot.
Change-Id: Ia71985ef21d634763fc5ae22e4f611f7f5e9652a
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
|
|
Realtek AX generation IC utilizes LTR-issued latency requests to
optimize WiFi latency and power consumption, it requires host
enabling LTR to meet the design requirement. We enabled the host's
LTR by enabling PCIe root port 8, which met resltek's technical
requirements.
BUG=b:377400590
TEST=Tested on Drawman with RTL8852BE
Use command $ lspci -vv, LTR+ is listed on DevCtl2
BRANCH=firmware-dedede-13606.B
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Change-Id: I093951f71e971fe83d61d9fcda8bf16cc5f82ffe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85011
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a new Rauru follower 'Hylia'.
BRANCH=rauru
BUG=b:376357839
TEST=emerge-rauru coreboot chromeos-bootimage
Change-Id: I79c4525347fd7b1ecea6df05e1a6b726b78e946f
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84924
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
The Fn key on rull emits a scancode of 94 (0x5e).
BUG=b:372211281
TEST=Flash rull, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: Idb02d7013fa78233abff556bc6fa1d224c434338
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lei Cao <caolei6@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
The previous method made cnvi wifi6 configuration cumbersome
and unusable. And delete unused pins. We abandoned the
fw_config judgment method and changed to the better rtd3.
BUG=b:374629673
BRANCH=None
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. wifi7&wifi6 function is normal
Change-Id: Ia95dc9f6b707db63840de9b15b38bdaea48ea192
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85000
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
|
|
Add Synaptics&PIXART init cpnfig, enable touchpad function
BUG=b:374629673
BRANCH=None
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. touchpad function normal
Change-Id: Iacf09cd46d4a97fb79f91043c84452f76689462f
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84999
Reviewed-by: Lei Cao <caolei6@huaqin.corp-partner.google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
The previous GPIO config will cause the SSD device to not be recognized. Based on schematics NB7559_MB_SCH_V1_2024_1010.pdf. So we adjust the position of the enable and reset pins.
BUG=b:374629673
BRANCH=None
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. power on proto board successfully
Change-Id: Idb36f67206450612655cb3efd3cce240475ef3ab
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Add support for the mainboard to check for any potential firmware
component update and hence the assosicated reset. This indication can be
used to avoid any redundant resets during the boot flow.
BUG=b:375444631
TEST=Build Brox BIOS image and boot to OS. Ensure that the hints are
provided correctly and 2 redundant resets are filtered out.
Change-Id: Ieed3f9013dee9aa501a3f0403f3a28722a3878f1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This patch reduces PL4 only for no battery condition i.e. when battery
is disconnected or not physically present.
BUG=b:377305625
TEST=Build Brox and boot when the battery is disconnected
Change-Id: I59a1028ce9cd3a6cf98f865d9c085a64f391f201
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Realtek AX generation IC utilizes LTR-issued latency requests to
optimize WiFi latency and power consumption, it requires host
enabling LTR to meet the design requirement. We enabled the host's
LTR by enabling PCIe root port 8, which met resltek's technical
requirements.
BUG=b:366383364
TEST=Tested on Awasuki with RTL8852BE
Use command $ lspci -vv, LTR+ is listed on DevCtl2
Change-Id: I0c80f89b4fdb52a5d9da17548537072ec2d40418
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
ext_vr_update should be run after board version 0xb, but skipped by
return. Drawper LTE board version was set after 0x9, but there are more
board added after that. Specific Drawper board version as 0xa, 0xb and
0xf.
BUG=b:376828839
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage and test on DUTs.
Change-Id: I13f4709b6f490169f69054cf2b26430b4de0746a
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
1. Add DB_1C_LTE 4 on DB_USB fw_config.
2. Implement WWAN power sequencing.
3. Disable LTE-related GPIOs based on fw_config.
4. Add I2C SX9324 (P-sensor) support.
Refer Schematic file: CA31AC_R10_MB_SUB_240903A_P.pdf
BUG=b:374666995
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Confirm the device node i2c-STH9324:00 created correctly,
and command for # i2cdump -f -y 11 0x28 is workable.
Change-Id: Ida56ff338d82f48aef419a65830a3380c83123d5
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84925
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
Irq2axi translates wire-based interrupt into message signal interrupt.
Since MT8196 uses legacy wire-based interrupt, this feature needs to be
disabled. If the interrupt is not handled, it will cause the system fail
to boot.
TEST=Build pass, check irq2axi_disable log and the interrupt can be
correctly handled by checking /proc/interrupts.
BUG=b:317009620
Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84896
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
De-assert PERST# at romstage to reduce the waiting time in ramstage.
BUG=b:361728592
TEST=The boot time improves 62ms
Change-Id: I2cd5cd59e7513b6e4036c3e8013a3c7322d2f787
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
1. Extend 1 bit [34] for the TOUCHSCREEN_SOURCE.
SSFC range for TOUCHSCREEN_SOURCE is bit[32:34].
2. Touchscreen panel: MUTTO A153728S1Y,
and set TOUCHSCREEN_ILIT2901 to value "4"
3. Datasheet: #153728S1V1.0 SPEC_20240923.pdf
BUG=b:375986645
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. Confirm command evtest and touchscreen function is workable.
Change-Id: I6e13c948edca5a894e1a00a1954f0f88c4a079cf
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84894
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
commit 6c83a71b0a80 ("skl mainboards/dt: Move usb{2,3}_ports settings
into XHCI device scope") not only moved the USB port definitions under
the XHCI device reference, but also combined multiple register
definitions. In doing so, it broke the inheritance from the baseboard,
since the variant overridetree registers now replaced the entire
usb2_ports/usb3_ports structs, rather than replacing individual array
elements therein. This resulted in any USB ports inherited from the
baseboard and not overridden by the variant being non-functional as they
were not included in the resulting combined devicetree.
To fix this, return to overriding individual array elements in the
usb2/3_ports structs.
TEST=build/boot google/fizz/var/karma. Verify all USB ports present and
functional. Verify mainboard/static.c in built shows all ports.
Change-Id: I0e80bf4949a857c21d44537eb720a7a8a7db2f80
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84955
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch configures the ESPI_SOC_ALERT_L GPIO pad on fatcat as
NC to enable S0ix low power entry.
TEST=Build fatcat and check the platform boots without an issue.
Change-Id: Icb80a56177105c0281d05fe1f5daa87e6f7e291f
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84957
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
|
|
Package C-state auto demotion feature allows hardware to determine lower
C-state as per platform policy. Since platform sets performance policy
to balanced from hardware, auto demotion can be disabled without
performance impact.
TEST=Build fatcat and check the platform boots without an issue.
Change-Id: I01f2cb8ac1093ae98cc076e35ad1924baa53aa59
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
1. Modify the I2C frequency of the touchpad between 380 Khz and
400 Khz to meet the spec.
2. Increase clk the time of high (TH) to greater than 600ns.
Before:
I2C0 - 420KHz
TH - 557ns
After:
I2C0 - 398Khz
TH - 630ns
BUG=b:351968527
TEST=Check that the wave form meets the spec.
Change-Id: I5ccaa3a669e18319311de14833966410c7adf40d
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84898
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
|
|
Add Micron part MT62F2G32D4DS-020 WT:F only for Francka.
DRAM Part Name ID to assign
MT62F2G32D4DS-020 WT:F 0 (0000)
BUG=b:373394046
TEST=emerge-fatcat coreboot
Change-Id: I2de56c8c7a028edefbd3dc53f8b1e26dee3286f7
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84781
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update device tree to support speaker o/p on MAX98357A AIC.
BUG=b:357011633
TEST=build coreboot image and test audio playback on Google/Fatcat board.
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I20de87f673e947f0e2332b818ebca01c0fa5e200
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84888
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP
headers for FSP as banshee is using a converged firmware image.
This effort also helps to save banshee boot time by 80-100ms as
RPL FSP is better optimized.
Additionally, Raptor Lake platform only needs 1 SIPI-SIPI which
saves 10ms of the boot time.
BUG=b:358254132
TEST=Able to build and boot google/banshee.
cold boot time w/o this CL
```
Total Time: 1,399,888
```
cold boot time w/ this CL
```
Total Time: 1,295,334
```
Change-Id: If22e07a4c1b35fe1d060ca523743c6c503937287
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
|
|
From power team's recommendation, increase the VccIn Aux Imon IccMax
to 30A to meet HW settings.
BUG=b:376306118
TEST=Build firmware and check the value is changing as expected.
Paste the firmware log.
[SPEW ] VccInAuxImonIccImax= 0x78
[SPEW ] (MAILBOX) VccInAuxImonIccImax = 120 (1/4 Amp)
[INFO ] Override VccInAuxImonIccImax = 120
Change-Id: I71020c2f631cb517a52d4bb65e35277eb731ced7
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
According to the PCIe CEM specification, the deassertion of PERST#
should occur at least 100ms after the assertion. Right now we simply
wait for 100ms in ramstage for that.
To speed up the boot time, pre-initialize PCIe by asserting PERST#
earlier in the bootblock stage. The pre-initialization time is stored
in the early init data region, so that the PCIe initialization in
ramstage could make sure the required 100ms delay is still reached.
This pre-initialization will speed up the boot time by 100ms on rauru.
TEST=Build pass, show pcie init pass log:
mtk_pcie_domain_enable: PCIe link up success (1)
BUG=b:317009620
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I2b84c25ae3ea9069fd38fa6b20b8235a7fc3a484
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
We want to configure different VBT timings for panels of different sizes
and distinguish them through SSFC. We select the reserved bit 6 of SSFC
as the flag bit. When using a 12-inch panel, set this bit to 0; when
using an 11-inch panel, set this bit to 1.
Without splitting, the platform_BootPerf test will fail.
BUG=b:374428465
TEST=
1. can match VBT with SSFC
-When SSFC is set to 0x40:
$ cat /sys/firmware/log | grep vbt
Bit 6 of SSFC is 1, use vbt-teliks_panel_11_inch.bin
CBFS: Found 'vbt-teliks_panel_11_inch.bin' @0x1c6140 size 0x50f in mcache @0x76adda14
-When SSFC is set to 0x0:
$ cat /sys/firmware/log | grep vbt
Bit 6 of SSFC is 0, use vbt-teliks.bin
CBFS: Found 'vbt-teliks.bin' @0x1c5bc0 size 0x50e in mcache @0x76add9b0
2. can pass platform_BootPerf test
The platform_BootPerf time measured for all SKUs is less than 1.55s.
Change-Id: Ia8fb45aede5ead4826d983760506c366a70643ee
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84871
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This commit adjusts the EC host command range for the Fatcat board to
0x800-0x807 & 0x200-0x20f.
This change is necessary because the microchip EC used on the Fatcat
board has a smaller host command range than the ITE/Nuvoton ECs used
on other Fatcat variants.
The `gen1_dec` register in the devicetree is updated to reflect this
change.
As per boot log, the `gen1_dec` aka offset 0x84, base address is 800
and size is 8 bytes.
AP FW Boot log:
[SPEW] PCI: 00:00:1f.0 resource base 800 size 8 align 0 gran 0 limit 0 flags c0000100 index 84
BUG=b:376207365
TEST=Able to build and boot google/fatcat w/o any error.
without this patch:
[SPEW ] LPC: Trying to open IO window from 800 size 8
[ERROR] LPC: Cannot open IO window: 800 size 8
[ERROR] No more IO windows
with this patch:
[SPEW ] LPC: Trying to open IO window from 800 size 8
Change-Id: Ifcee533341fa583d841a4b564f25831c6d04e951
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84919
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
|
|
This commit defines the EC_SYNC_IRQ and GPIO_PCH_WP macros for
different Fatcat variants.
The EC_SYNC_IRQ macro is used for tight timestamps and wake support,
while the GPIO_PCH_WP macro is used for the WP signal to the PCH.
These macros were previously undefined or incorrectly defined for some
variants. This commit fixes these issues and ensures that the macros
are defined correctly for all variants.
Specifically, this commit:
- Defines EC_SYNC_IRQ and GPIO_PCH_WP for Fatcat Nuvo and Fatcat ITE.
- Defines EC_SYNC_IRQ as 0 (not connected) for Fatcat.
- Defines GPIO_PCH_WP as GPP_D02 for Fatcat.
- Leaves EC_SYNC_IRQ and GPIO_PCH_WP as 0 (TODO) for Francka.
TEST=Able to build and boot google/fatcat.
w/o this patch:
```
cros_ec_lpcs GOOG0004:00: couldn't retrieve IRQ number (-22)
cros_ec_lpcs GOOG0004:00: probe with driver cros_ec_lpcs failed with error -22
```
w/ this patch:
```
cros_ec_lpcs GOOG0004:00: Chrome EC device registered
```
Change-Id: I9bd248496f08869c08cf6daafeed6584d0b166b7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
|
|
This patch updates the flash map layout to guarantee that the
RW_SECTION_B section starts at the 16MB boundary.
Additionally, fix typo in flash descriptor comment, where comment
incorrectly referred to "MTL" instead of "PTL".
TEST=Successfully builds google/fatcat.
Change-Id: Ia6dba611fba50f9694a75670d954a4630cde4d70
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84899
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When creating variant, it was copied from teliks, and according to the requirements of telith project, update the override devicetree to use ELAN touchscreen.
BUG=b:373510302
BRANCH=None
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. power on proto board successfully
3. touchscreen is functional
Change-Id: If0da85a38f3a68b6f50cfd096a628174b313fcc9
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84865
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Create the rull variant of the nissa reference board by copying
the template files to a new directory named for the variant.
And based on schematics NB7559_MB_SCH_V1_2024_1010.pdf
update devicetree settings.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0)
BUG=b:374673463
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_RULL
Change-Id: If48273f3e9db69507b41ea0313916d94ecabe309
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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This change enables the integrated GPU (iGPU) display on the Fatcat
board based on the FW_CONFIG setting (specifically the DISPLAY bit).
By conditionally probing the display based on FW_CONFIG, the iGPU
is dynamically enabled or disabled according to the SKU configuration.
TEST=Verified display functionality on Fatcat with the iGPU:
> cbi set 6 0x58A814 4 (DISPLAY_ABSENT):
- lspci does not list the iGPU.
- No display output, but the device boots to the OS (verified via
console).
> cbi set 6 0x5CA814 4 (DISPLAY_PRESENT):
- lspci lists the iGPU.
- Display output is functional, showing firmware and OS UI.
Change-Id: I5762adf5ec8a86a00c16544670cb2f998055bd35
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84877
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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The iGPU device is enabled by default in the Pantherlake chipset
configuration. Remove the redundant device entry in the Fatcat
devicetree.
This change ensures that the iGPU remains enabled without explicit
configuration in the board-specific devicetree.
TEST=Able to build google/fatcat and able to see firmware and OS
display/UI.
Change-Id: I9a2ec9b47acb389f5bb6b30e61352aaefa327328
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84876
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add PCIe domain support.
TEST=Build pass, show pcie init pass log:
mtk_pcie_domain_enable: PCIe link up success (1)
BUG=b:317009620
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I3e06dfaf79924cd5352348afaa526fc7dedbb540
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84700
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a trivial mainboard_needs_pcie_init implementation that always
return true. For now, the storage types of rauru SKUs are still unknown.
TEST=Build pass, show pcie init pass log:
mtk_pcie_domain_enable: PCIe link up success (1)
BUG=b:317009620
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I6b4f08e15f62da18aa37226075894f2827a9e7ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84697
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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