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Foob360 would prefer to use different SAR values. Since Foob360
sku id is 9.
BUG=b:149362272
BRANCH=octopus
TEST=build
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I8cc5d73629990f19d2c1044debdba4990c54d07e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
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Add initial support for waddledee variant board.
BUG=b:151576904
TEST=Build the mainboard and variant board.
Change-Id: I20d41fbbb78c7fd2f964a97ffebbc9c3bbfb1c5c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This is new Elan touch screen IC, which includes touch panel and USI pen.
BUG=b:151514167
TEST=build bios and verify touch screen works fine
Signed-off-by: Tommie Lin <tong.lin@bitland.corp-partner.google.com>
Change-Id: I98801b8c31812637f71d7eaaa0f12b47901dc47a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add Palkia as a variant of Hatch.
BUG=b:150254194
BRANCH=none
TEST=none
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I6a303d9fc2be9ea358ad66cd648738187c974193
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38860
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Volteer uses 4 bits (hardware straps) to indicate what memory
configuration the board is populated with (i.e. which SPD file
to use for the populated memory). This allows for only 16
different SPDs for supporting Volteer and all future variants of
Volteer. Currently, each memory chip needs its own SPD file, so we
can only support 16 different memory chip options for Volteer and
all of its variants.
Generic SPD files are just SPD files that have been stripped down
to contain only fields that are important for the memory controller
(strips out items like vendor info, for example). Using generic SPD
files allows for more than 16 different memory options given it's no
longer a 1-to-1 mapping as similar memory modules from different
vendors can share the same generic SPD file.
BUG=b:147857288
TEST="emerge-volteer coreboot chromeos-bootimage", flash ripto and
verify ripto boots to kernel and "cat /proc/meminfo" reports 8GB
of memory.
Change-Id: I17bd4f4a00b4e3bbaf845d6d321962c11569a186
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39423
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device.
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used
for WLAN - both CNVi and M.2.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Disable the BT module in bootblock and enable it in ramstage. This
allows for loading the BT firmware during reboot.
TEST=Build and boot the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0406a68ffcab2675a1aedb212cb7c8508a5b61fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39446
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable GEO SAR function.
BUG=b:150347463
BRANCH=drallion
TEST=NA
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iace9aa0245840328aa13920512747ca7f60e85dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39467
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Provide settings for configuring the link between HD-Audio controller
and display unit for purposes of HDMI/DP Audio playback.
BUG=b:144708516, b:148385924
TEST=none
Change-Id: I225faac68729b28be65b4d8f1f83769a874f84ff
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39356
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Early ec sync needs to be disabled for EFS2 to function.
BUG=b:151115320
BRANCH=none
TEST=none
Change-Id: I384d072d9614a5cd30837f7cdfb777ad5e4f6b19
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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1. Configure trackpad interrupt GPIO.
2. Set i2c0 configuration.
3. Add trackpad ACPI support.
TEST= Verify trackpad working. Verify I2C SCL frequency below 400Khz
on trackpad operation.
Change-Id: I52c578aef591f5be90fb709bab4c8342ea9729e6
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Create new variant and build for nightfury.
BUG=b:149226871
TEST=FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Limit PcieL1Substate for RP9, RP11 for ES1 NVMe warm reboot workaround.
Reference: #613582 Tiger Lake PCH-LP Sightings Report
issue id #1409566330
BUG=none
BRANCH=none
TEST= boot to OS and check warm reboot with NVMe
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie85bf71c43427e326ef2ba674da4566f8f51495a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Enable USB ACPI driver. Add ACPI configuration for all the USB ports.
Since one of the USB ports is used for Bluetooth configure the
reset_gpio used by that port.
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I3e7b8f00102c96dcc295601359d3ecfbcd1bea00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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BUG=b:150154457
BRANCH=none
TEST=Build dedede, flash and boot to kernel.
Change-Id: I7248861efd1edd5a0df0e17d39a47c168cab100e
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39348
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown
when S0ix is enabled.
BUG=None
BRANCH=None
TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Drallion.
Change-Id: I146068d8019859be1c27e2a8174dfe7909d42d0a
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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Add LPDDR3 4GB 2133MHz SPD file.
BUG=b:149226871
TEST=Build and check cbfs has the spd.bin
Change-Id: I1598774a87eecc76082286540beadaa3c26eda69
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39271
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Optane memory module shows up as 2 NVMe devices in x2 config - NVMe
storage device and NVMe Optane memory. Storage device uses rp9 and
optane memory uses rp11. This patch enables rp11. Please note that
these two share clk related pins.
Configuring pciecontroller3 to be set from 2x2. This will by done by
auto detecting optane memory: enabling HybridStorageMode.
BUG=b:148604250
BRANCH=chromeos
TEST='Build, boot and look for two NVMe devices with lspci on Volteer'
Cq-Depend: chrome-internal:2501837
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: I5430829b496ed275e2e3bda3c0bf21c3d2132628
Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreboot-intel-private/jsl-tgl/+/2424428
Tested-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39420
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable WWAN PCIe to allow WWAN enumerate as USB on Volteer.
BUG=b:146226689
BRANCH=none
TEST=lsusb shows WWAN device
Change-Id: I04e49e3ec989d20ea3469fce06051c475b0ed0c8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This is required to transmit button information from EC to kernel.
BUG=b:150830342
BRANCH=None
TEST=firmware_ECPowerButton test passes on puff
Change-Id: I10ba9d55e8997ce2412deb0613cfcaa8f24f271d
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Change-Id: I6374bc2d397800d574c7a0cc44079c09394a0673
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37984
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=144874778
TEST=Built with Volteer recipe and verified USB functionality
Change-Id: I6cbdbd8a4f65a0fe19e3fb8d7b60b8b849f104e7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add configuration for all the PCIe Root ports and Clock Source.
Configure the Root Ports as disabled and clock sources as not used.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0a1ad7e056907e454a93f51c84e1d99f08b7bdef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39166
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This enables display for use by payload.
TEST=Build and boot the mainboard. Ensure that the screens displayed by
payload are visible.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5fcd70623b15ae39954242605e75b2c5ce02ff14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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BUG=b:150869661
TEST=Build and boot the mainboard. Trigger apreset from EC console.
Trigger reboot from AP console.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0d6dd0b4264c11f7ee0ef436cc819b0bb92974f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39325
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Leave all the GPIOs in not connected state so that they can be
configured depending on the use-case. This is done to park the GPIOs in
a known safe state. This will also help to ensure that the required
GPIOs are configured when the concerned use-cases are enabled.
Below GPIOs are configured in Native Function 1 and are required for
boot-up.
* VCCIN_AUX_VID0
* VCCIN_AUX_VID1
* AP_SLP_S0_L
* PLT_RST_L
* CPU_C10_GATE_L
* GPDs
BUG=None
TEST=Build and boot the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5293536f66a6b08c9c2d2a6281684755a0c0b1b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39114
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:147500717
TEST=none
Change-Id: I32fa27b399127dbf8608e0556c77431d2dad652d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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- declare the FPMCU interrupt to be level-triggered
- change EC_PCH_WAKE_ODL gpio to native function mode
- corrected spelling of a signal name in a comment
BUG=b:144933687, b:148179954
BRANCH=none
TEST=none
Change-Id: I62da900d0b71139e55b52d06ec09ca25106f73cd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Changes allow to use the integrated panel logic (power sequen-
cing and backlight control) for more connectors. The Kconfigs
GFX_GMA_PANEL_1_PORT and GFX_GMA_PANEL_2_PORT can now be set
to any port, e.g.
config GFX_GMA_PANEL_1_PORT
default "DP3"
Now that the panel logic is not tied to the `Internal` port
choice anymore, we can properly split it into `LVDS` and `eDP`.
This also adds Comet Lake PCI IDs which should still work the
same as Kaby and Coffee Lake.
Change-Id: I78b1b458ca00714dcbe7753a7beb4fb05d69986b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38921
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change uses drivers/intel/wifi chip for CNVi device and
adds dynamic SSDT entires for CNVi also export wake gpio for CNVi.
BUG=none
BRANCH=none
TEST=Build and boot volteer
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ia8baf1c7b770db23f31383bda46ae8d090468560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Add samsung K4UBE3D4AA-MGCR SPD as memory sku id 1.
BUG=b:148182234
BRANCH=none
TEST=none
Change-Id: Ie00c45de4d31856109cda13051a75cfa2c2548f7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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wpsw_boot is deprecated in favour of wpsw_cur. As such,
coreboot no longer needs to share "write protect" GPIO
with depthcharge.
BUG=b:124141368, chromium:950273
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I2fcb7f82aa063fd72928171af5cbef0356ba620c
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:2088434
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39318
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This commit creates a nuwani variant for Grunt. The initial settings
override the baseboard was copied from variant treeya.
BUG=b:144890301
TEST=emerge-grunt coreboot
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Id3a7fc890340e5a88ebc4b516dc2c0b085654999
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39316
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a new ripto variant based off of the volteer baseboard design.
BUG=b:148385924, b:150810535
TEST="emerge-volteer coreboot chromeos-bootimage", flash ripto image
and verify ripto boots to the kernel.
Change-Id: If7606588147500a465f16c7846e2c8429ece93ec
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
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Declare variant_early_gpio_table() weak to allow override by variants.
BUG=b:148385924, b:150810535
TEST=none
Change-Id: Ife5e3b75256f71ecd763c4000fd2c7d7c927bb64
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39300
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If the ChromeOS EC uses EC early firmware selection (EFS), the AP vboot
build must also enable EC EFS. Puff EC uses EFS, so enable it in the AP
vboot build.
BUG=b:150742950
TEST=Puff can boot with EC EFS with hardware write protect enabled
BRANCH=none
Signed-off-by: Sam McNally <sammc@chromium.org>
Change-Id: I0877000b7d277106436831f2d69775c25299da9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Internalise smbios_system_sku() strong symbol inwards in the ec_skuid.c
implementation and simply wrap a call to:
google_chromeec_smbios_system_sku().
BUG=b:150735116
BRANCH=none
TEST=none
Change-Id: I05ebfc8126c0fb176ca52c307c658f50611ab6ab
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39146
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Leverage the common sku id space helper encoders.
dedede uses the non-legacy SKU ID space.
squash in,
mainboard/google/dedede: Migrate onto get fw_config helper
BUG=b:149348474
BRANCH=none
TEST=only tested on hatch
Change-Id: I0c21a748fddef0985022cb4e77a8db95d6692f4b
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Leverage the common sku id space helper encoders and
set the sku id max to 0xff for legacy to ensure we
behave the same.
BUG=b:149348474
BRANCH=none
TEST=tested on hatch
Change-Id: I60a37a5f9659b8df4018872956f95e07a3506440
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable read SAR value from cbfs.
BUG=b:150347463
TEST=NA
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5f27b6f7245669728e3e394e9c6a39c11bfda3b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
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Only some mainboard vendors have a prompt for this option. Let's be fair
and give this ability to everyone.
Change-Id: I03eec7c13d18b42e3c56fb1a43dc665d5dbd1145
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Update memory parameters based on memory type supported by dedede
1. Update dq/dqs mappings
2. Update spd data for Micron Memory
3. Add SPD data binary files for supported memory types
4. Update other FSPM UPDs as part of memory initialization
BUG=none
BRANCH=none
TEST=Build dedede, flash and boot to kernel.
Change-Id: I7248861efd1ecd5a0df0e17d39a44c168cab200e
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39136
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:149775711
BRANCH=firmware-hatch-12672.B
TEST=emerge-hatch coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: I856d7b361e70b657966cd4036c79f2fedfabb766
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39126
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.
This follows commit 408d1dac9e23250c0e485bbf934771f769b717c1.
Change-Id: I0c0f4ad8bf743010ebdd2d53fcf297aeab64a662
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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It provides no useful information, so it might as well vanish.
This follows commit 0142d441c63a9bb1a7955ea0ba764a2ddbc38d48.
Change-Id: Iad41d8d39c6712cebfa5245f37bc69061b5ac552
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The VBOOT code can be compiled but it asserts with:
ASSERTION ERROR: file 'src/security/vboot/common.c', line 40
Start VBOOT in bootblock to fix the assertion.
Tested on Lenovo X220:
The assertion is gone, the platform boots again.
Change-Id: I48365e911b4f43aecba3b1f950178b7ceed5b2e9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This is new elan touch screen IC, which includes touch panel and USI pen.
BUG=b:149800883
BRANCH=octopus
TEST=build bios and verify touch screen works fine
Signed-off-by: Tommie Lin <tong.lin@bitland.corp-partner.google.com>
Change-Id: Ibec3d08cc740e398a10a5c845181318724afc70a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
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Disable EPS on the SKUs that do not have it.
Change-Id: I7305097beea3484634933ab856fd084933868a10
Signed-off-by: Rajat Jain <rajatja@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
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Enable the GFX device for Jinlon.
Change-Id: I6ba90bf464e315ec364b6f35e7670924a2aba25a
Signed-off-by: Rajat Jain <rajatja@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
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Leverage the common sku id space helper encoders.
volteer uses the non-legacy SKU ID space.
BUG=b:149348474
BRANCH=none
TEST=only tested on hatch
Change-Id: Ic66908afb7abb34527b4177cfd07f03ad718317c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Leverage in Puff to avoid diskswap variants. Later this could become
part of the baseboard definition and hatch diskswap variants migrated
over to use it as well.
BUG=b:149171631
BRANCH=none
TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and
run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration
on Puff.
Change-Id: Ie87f0823f28457db397d495d9f1629d85cfd5215
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Leverage the common sku id space helper encoders.
BUG=b:149348474
BRANCH=none
TEST=tested on hatch
Change-Id: I96e10010fd375b127f1e10387d6f7a839bc35fdd
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39019
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure GPP_E0 as output for view angle management
Change-Id: Iad640eed855b47e365da55fa994c6a3c4c38caf9
Signed-off-by: Rajat Jain <rajatja@google.com>.
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Configure below ESPI IO decode ranges:
1. 0x200-020F: EC host command range.
2. 0x800-0x8FF: EC host command args and params.
3. 0x900-0x9ff: EC memory map range.
Change-Id: I1e450d6e45242180de715746b9852634de2669c6
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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1. Enable Internal Gfx device.
2. Configure DDI0 for EDP.
3. Configure HPD and DDC suppport for DDI1/DDI2.
4. Configure HPD GPIOs.
TEST=Verify display on EDP panel in OS
Change-Id: Ia53428af549ba01ab539f9474a6e5e79b72dff5c
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39132
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I8c721c7ccba4f87d4acb9dae74213a46151fe2ed
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The indirection of names is exceedingly confusing for ultimately the single
interrupt trace of EC_PCH_WAKE_ODL between the EC gpio#74 to GPD2/LAN_WAKE# on
the PCH side.
This helps folks chase this indirection down through the code.
BUG=b:147026979
BRANCH=none
TEST=builds
Change-Id: I35d746a202dae06d2f6f1edfaa3889864b09f50d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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WWAN wake event is routed to GPP_D0 GPIO and Pen Detect wake event is
routed to GPP_C12 GPIO. Update the GPE configuration accordingly.
BUG=None
TEST=Build the mainboard.
Change-Id: Id36d2c8265a0b7ea241565f6bb723df6b37446fa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39100
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie47265527b2b81748f4f3ad744d35cb81af17b80
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Change-Id: I663678a4c572fe80298f7388870d5cd403122b98
Signed-off-by: Jeff Chase <jnchase@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Change-Id: I77c33c19b56dc9bd54e7555ce59f6a07bde3dbb6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This change creates gfx directory under drivers/ so that all drivers
handling gfx devices can be located in the same place. In follow-up
CLs, we will be adding another driver that handles gfx devices.
This change also updates the names used within the driver from
*generic_gfx* to *gfx_generic*. In addition to that, mainboard
drallion using this driver is updated to match the correct path and
Kconfig name.
TEST=Verified that drallion still builds.
Change-Id: I377743e0f6d770eed143c7b6041dab2a101e6252
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
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Remove MAC address pass through because when MAC address pass through setting
change to "Use dock built-in MAC address", the MAC address always keeps the VPD
value.
BUG=b:149813043
TEST=tested on sarien and the result as below.
(Option) (Result)
- Use pre-assigned MAC address : Pass
- Use Chromebook built-in address : Pass
- Use dock built-in MAC address : Pass
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ia85ef6ed0c4db82301375edd0968cf7dd2f62dc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Follow latest HW schematics to set GPP_G4 and GPP_G6 to NC pin.
This can save 1mW power comsumption.
BUG=b:149289256
TEST=NA
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib3bf8b8f922a350d2b73ef5c9e9cf1b6e2c0f657
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
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Commit 6ae8b50 [chromeec: Depend on events_copy_b to identify wake source]
partially broke resume from suspend on Auron and Slippy variants when
multiple events exist in the EC event queue. In the case of the device
suspending manually and then subsequently having the lid closed, the device
will be stuck in a resume/suspend/resume loop until the device is forcibly
powered down.
Mitigate this by clearing any pending EC events on S3 wakeup.
Test: build/boot several Auron/Slippy variants, test suspend/resume functional
with both single and multiple events in EC event queue.
Change-Id: I7ec9ec575d41c5b7522c4e13fc32b0b7c77d20d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add initial support for waddledoo board.
BUG=None
TEST=Build the mainboard and variant board.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8ab4d52c97b1cfb5549d2fce4b931748a1b1ff1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Turn on EMMC device and enable the HS400 mode. Configure the GPIOs
associated with EMMC.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ic27c68f4622eec5b2930dc38186b82d895d3f67c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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Add USB port configuration in devicetree. Configure USB Over-Current (OC)
GPIOs.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I19f7563013c7d702d52b7f34a207a34abe308621
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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Remove MAC address pass through because when MAC address pass through setting
change to "Use dock built-in MAC address", the MAC address always keeps the VPD
value.
BUG=b:147994020
TEST=tested on drallion and the result as below.
(Option) (Result)
- Use pre-assigned MAC address : Pass
- Use Chromebook built-in address : Pass
- Use dock built-in MAC address : Pass
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I1f58e98187feb4e428ca75f7e82c464567528526
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
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Some Volteer variants might not use SPD files. Allow SPD_SOURCES in
spd/Makefile.inc to be empty.
BUG=None
BRANCH=None
TEST=Build coreboot and see that it builds without error
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I5a8231b999e16503867d3c8df571b11fa0c1f6a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'.
Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change based on google/auron that is similar to peppy.
This will be helpful for the next follow-up commit that will
add ACPI for the ambient light sensor.
Change-Id: Ib2a8356d261d211d5ed5c0b035c94ec56b9c25b3
Signed-off-by: Nicolò Veronese <nicveronese@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Follow thermal table for fine tuning.
1. Update PSV values for sensors.
2. Change PL1 min value from 4W to 5W.
3. Change PL1 max value from 15W to 12W.
4. Change PL2 min value from 15W to 12W.
BUG=b:148627484
TEST=Built and tested on drallion
Change-Id: I957d41e3c14f6dbcec8c3555382895698beabe40
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Proper VR settings will be selected by CPU SKU and cpu_pl2_4_cfg.
BUG=b:148912093
BRANCH=None
TEST=build coreboot and checked IA_TDC from TAT tool.
Change-Id: Ie471dee0c70e1831a822860c0a44455772a2b8be
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
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add SKU ID 3 and 4 for dood DVT
1: Dood WiFi + LTE (evt)
2: Dood WiFi (evt)
3: Dood WiFi + LTE + dual camera (dvt)
4: Dood WiFi + dual camera (dvt)
BUG=b:148988979
TEST=build firmware and verify on the DUT of sku 3 and 4
check LTE module is enabled or not
Change-Id: If86efe2a2f7b2e165ad44220b6dd59e9080b5892
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38730
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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USB3 OC pin is configured for the wrong pin. Follow HW circuit
(schematics) to set it correctly.
BUG=b:147869924
TEST=USB function works well and OC function is corresponds to the
right port.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I61234a2054ab52fa508482d3dd0f94b13f96a5c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38885
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Puff uses the smbus to access the SPD of memory DIMMs.
It will short the SPD reading time if enabling SPD_READ_BY_WORD.
BUG=b:149360051
BRANCH=None
TEST=build puff and boot up OS
ran cbmem -t | grep FspMemoryInit
Without this patch:
950:calling FspMemoryInit 643,199 (257,588)
With this patch:
950:calling FspMemoryInit 477,714 (154,612)
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Change-Id: I161e8eb386ab604b16746f0deeecc3d6c9063c3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Fine tune the video timing of panel-BOE_TV101WUM_N53 to avoid noise. The
parameters are based on BOE NV101WUM-N53 preliminary product spec.
BRANCH=kukui
BUG=b:147378025
TEST=bootup pass
Change-Id: Ia9e2cc90f233e87d712c2dc6f4441ca2e5423162
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38401
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Declare the following panel for Kakadu:
- BOE_TV105WUM_NW0
BUG=b:148997748
TEST=build Kakadu image passed
BRANCH=kukui
Signed-off-by: Casper Chang <casper_chang@bitand.corp-partner.google.com>
Change-Id: I394b8cafa8be40e5fd6bf8ceb81b520df73718a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38822
Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Bipship is a sustaining project of Blooguard.
SAR value follow Blooguard.
BUG=b:149414960
BRANCH=octopus
TEST=build and verify load correct SAR value by sku-id
Change-Id: Ic45ed10fc147401d4278f1811a86cd2b2e4c63ac
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Enable I2C ports that are used. Add GPIO configuration for the I2C
ports. Enable config items that are required for I2C HID & Generic devices.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I12e974530fb5f61fae5d12cadbb3f928e617d73a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Enable UART Port 2 as console UART and configure the concerned GPIOs.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I30a64a3c96226ce3244d55919b6d65fbf0a096e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38776
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Turn on the H1 device in the devicetree. Configure the concerned GPIOs
and enable the required config items.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I37972635454cd0d35608623e7be4110012ace658
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38772
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit a017e5fb3dda5ea6bbc94ee15b2e981eeaa2d918.
Reason for revert: The extra reset in the FSP after the flex ratio is changed causes recovery reasons to be lost. There are some vboot changes that recently landed that could help with this issue, but for now, we are working on a new AU image for Kohaku and this is causing our automated testing to fail.
Change-Id: Ic38b390842e2a533033587b3247b7c8d982b1dff
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Some of the common memory code that was being performed in
mainboard has moved into the soc to reduce redundant code.
This change adapts volteer to use Tiger Lake's new common code.
BUG=b:145642089, b:145238504, b:145564831
BRANCH=none
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer, boot to kernel, "cat /proc/meminfo" and verify it reports
"MemTotal: 8038196 kB".
Change-Id: I32c9b8a040728d44565806eece6cf60b6b6073b6
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change tcc offset from 0 to 15 degree celsius for lick.
BUG=b:147198431
BRANCH=octopus
TEST=Build, and verify test result by thermal team.
Signed-off-by: Hash.Hung <hash1.hung@lcfc.corp-partner.google.com>
Change-Id: Ife6b02321145837e05c82f979998466b83317f86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38506
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add initial configuration for GSPI, I2C and UART ports and leave them in
disabled state.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I1cd7659337e6330a8ece34df247e399a085d21d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I12a63e5776619e5a7684cf1edad78b0fd6fac12c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38739
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure the GPIO groups to be routed to the GPE0 block.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ife4d0179bd9fe1785e971686478f7c76de805e87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add compute and PCH Global device IDs with the concerned devices turned
off.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I6f226abd52d4a27535de6711e93355b5f84a1941
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Created a new Google baseboard named volteer from scratch.
BUG=b:142961277
BRANCH=master
TEST="emerge-volteer coreboot" compiles successfully.
Change-Id: I03a13f3df4e819ab9cf63ad69867c807d2a1b651
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add new SPD files for drallion:
1. Hynix H5AN8G6NDJR-XNC
2. Samung K4AAG165WA-BCWE
3. Samung K4A8G165WC-BCWE
BUG=b:148642500
TEST=Compile successfully and check SPD info in cbmem log.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I0e9b444f6f1e0c7e1da197fbd2e70e686568ab47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38731
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change GPP_C10 from pltrst to deep to meet the warmboot power sequence.
BUG=b:146935222
TEST=measure WWAN power sequence is meet spec
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia1513ed38fbc1c99a10a5fa531a78cc92a3ebfc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
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BUG=b:148410914
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7dffa5c021787dca75786ead42164bd29ba56828
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Since most of Bloog series SKUs need to disable DRRS support.
If Bloog and Unprovisioned SKUs then return vbt.bin to enable DRRS support,
return vbt_blooguard.bin for other SKUs to disable DRRS support.
Bipship follow blooguard to disable DRRS support.
BUG=b:148892903, b:147021309
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
check i915_drrs_status shows DRRS supported NO when SKU ID is bipship.
Change-Id: I61f12d4ddea17a05255751fde2a5ce822dd2e782
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Wait for HPD DP unless HDMI is plugged.
Some Type-C monitors do not immediately assert HPD. If we continue
to boot without HPD asserted, Depthcharge fails to show pictures
on a monitor even if HPD is asserted later.
Similar to that of b:72387533 however our DP&HDMI are beind a MST.
See commit d182b63347c744c on how this was done for mainboard/fizz.
BUG=b:147992492
BRANCH=none
TEST=Verify firmware screen is displayed even when a type-c monitor
does not immediately assert HPD. Verify if HDMI monitor is connected,
AP does not wait (and firmware screen is displayed on HDMI monitor).
Change-Id: I19d40056e58f1737f87fd07d62b07a723a63d610
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Enable acoustic noise mitigation, the slow slew rates are fast time divided by 8
and disable Fast PKG C State Ramp (IA, GT, SA).
BRANCH=hatch
BUG=b:143501884
TEST=build and verify that noise reduce.
Change-Id: I65f47288a7b1da98296fdba87ab5ca0c3a567aaf
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38212
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow HW change to use GPP_D15 as TS_RST. And change GPP_B21 from pltrst
to deep in order to met power off timing.
BUG=b:143733039
TEST=Check touch screen is functional in s0 and resume from s0ix
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ieec7eb78a05e653f271e348ed11f7e31c08bd5dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38665
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Enable PCIe port for dGPU
2. Change WLAN PCIe port from port 14 to port 7
BUG=b:147249494
TEST=Ensure dGPU and WLAN shows up with lspci.
Change-Id: Iea3292be7d8029c35847118228bbb773418632a1
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38399
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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