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2018-06-04mb/google: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I24fd33887152c12b9db9742af475115b02b31ff2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-03mb/google/kahlee: Remove #include <soc/smi.h>Richard Spiegel
Because of struct sci_source table of events that have to generate SCI or SMI, <soc/smi.h> was included to kahlee/grunt gpio.c files. However, new code transfered most of SCI/SMI/interrupt programming (with exception of events not associated to a GPIO pin), and therefore smi.h is now included by gpio.h. It was also added to some other files where they are not needed. Only smihandler.c truly needs it. Remove the includes. BUG=b:78139413 TEST=build and boot grunt. Change-Id: I64cf0796103a5226ddace03d05d94160bf93aa69 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26721 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-03mb/google/poppy/variants/nami: Load vayne VBT binaryIvy Jian
Load vbt-vayne.bin by reading sku-id. BUG=b:80509366 TEST=Boots to OS and display comes up. Check the board specific vbt binary loaded. Change-Id: Ia26ea4a9b7679aeb9d98f19ffaa1b686af828339 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-03intel bd82x6x/lynxpoint systems: Update ACPI thermal zone handlerMartin Roth
Currently the throttle event handler method THRM is defined as an extern on the intel bd82x6x and lynxpoint chipsets, then defined again in the platform with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. This also requires moving the thermal handler, which now includes the define to before the gnvs asl file. TEST=Build before and after, make sure correct code is included. Change-Id: I7af4a346496c1352ec20bda8acb338b5d277d99b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26123 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-01mb/google/nautilus: Add "rotation" controljimlai
The driver only supports streaming images flipped horizontally and vertically. In order to ensure that all current users will be fine if or when support for upright streaming is added, require the presence of the "rotation" control now. BUG=None BRANCH=None TEST=Verified the MIPI and USB camera function on DUT board Change-Id: I7e3abdea9071da1a089c7165f6bb609428090792 Signed-off-by: Lai, Jim <jim.lai@intel.com> Reviewed-on: https://review.coreboot.org/26727 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Andy Yeh <andy.yeh@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-01mb/google/octopus: Enable RT5682 headset codec for BIP boardNaveen Manohar
Patch adds required changes for RT5682 codec enablement for the BIP board. And code clean-up nhlt blob selection method in config. BUG=b:77892150 TEST=build and boot on a BIP PO board. verify headset codec i2cdetects at address 1a. Change-Id: Iee91518c03a0e9e6ed52bc54a60fc607730a0b7d Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/26211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-01mb/google/rambi: Set SMI mask using google_chromeec_events_initFurquan Shaikh
This change updates rambi ec init to perform SMI mask setting using google_chromeec_events_init. Change-Id: I7def3c07b4d7bfbe15b2d1c45381bdc31b7e3476 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-01mb/google/fizz: Add USB port infoEmil Lundmark
This adds all USB ports to the device tree. Additionally, it adds _PS0 and _PS3 ACPI methods for the visible USB A ports, which makes it possible to control the port power (VBUS) of each port individually. Change-Id: I80ba090f323fbf9fc2b333b1c647b7dfb3393ff6 Signed-off-by: Emil Lundmark <lndmrk@chromium.org> Reviewed-on: https://review.coreboot.org/26472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-05-31mainboard/google/kahlee: Add careena variantMartin Roth
Add Careena variant, based on the grunt board. BUG=b:80106042 TEST=Build Careena Change-Id: I87a24f6d8115aacf5b21181f3820cf2718ad252a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-31mb/google/poppy/variants/nocturne: configure the FPMCU interfaceVincent Palatin
The FPMCU is using the standard cros-ec-spi interface on GSPI1. Configure the GPIOs controlling the MCU too. We need to be able to wake from S3 on the MCU interrupt, re-configure GPE0 DW0 to point to GPP_C bank. BRANCH=poppy BUG=b:79666174 TEST=exercise the cros_ec interface, e.g. 'ectool --name=cros_fp version', verify the MKBP events by doing 'ectool --name=cros_fp fpmode fingerup' then 'ectool --name=cros_fp waitevent 5 10000', toggle the other GPIOs with the flash_fp_mcu script. Change-Id: Ib417dcf84cda8e354060785cd16a7b6b812148d5 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/26684 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-30mainboard/google/kahlee: move grunt's chromeos.fmd to baseboardMartin Roth
The chrmoeos.fmd file will be common across variants, so move it out of of grunt directory and into the variants/baseboard directory. BUG=b:80106042 TEST=Build grunt Change-Id: I259d85f60c5e19e00f7d9149542bcfdcc6dfaf4f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-30mainboard/google/kahlee: move SPDs to variants/baseboard/spdMartin Roth
The SPD files will be common to many of the mainboards, so move them out of grunt and into the variants/baseboard directory. BUG=b:80106042 TEST=Build grunt, make sure spd.bin is the same. Change-Id: I53975a46a8c7d7e519bb6f7ef6ccd0b817ac4c92 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-29chromeec platforms: Update ACPI throttle handler callMartin Roth
Currently the throttle event handler method THRT is defined as an extern, then defined again in the platform with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. Change-Id: I6337c52edaf9350843848b31c5d87bbfca403930 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28soc/intel/apollolake: Don't use pulldowns in standby state for 1.8/3.3V pins.Shamile Khan
These pins should not have pull downs configured in standby state as that can cause contention on the termination circuitry and lead to incorrect behavior as per Doc# 572688 Gemini Lake Processor GPIOTermination Configuration. Furthermore, some of these pins were configured with normal termination of None which would as per above mentioned document lead to a standby termination of None anyways. Instead of pull downs, use the IOSSTATE setting for driving low via the Tx mode. BUG=b:79874891, b:79494332, b:79982669 BRANCH=None TEST=Flashed image and booted to OS on Yorp. Touchscreen does not consume power in suspend state. Change-Id: I7dcf3691b969d018b3cfb6af3f7467c9b523fee5 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/26491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-27grunt: Wire up the EC SMI handlerRaul E Rangel
This won't actually get called yet since the GPIO pin has not been configured as SMI. BUG=b:80295434 TEST=grunt: Made sure events could be processed. Change-Id: I189e26196e4543b3e34bff5d9df8566eff07d585 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-27stoneyridge GPIO: Create and use PAD_INT for interrupt pinsRichard Spiegel
The default interrupt control for GPIO pins within stoneyridge is for edge triggered, high. However, sometimes these need to change, or maybe the interrupt needs to be reported or delivered. This was the case of platform grunt, where the interrupt related bits were being changed afterwards. Ideally all the bits should be programmed through the same procedure. Create several PAD_INT definitions (for general configuration, for trigger configuration and for interrupt type configuration) and change function sb_program_gpios() to accept the output from PAD_INT_XX and program all the necessary bits while keeping compatibility with other PAD_XX definitions. BUG=b:72875858 TEST=Add code to report GPIO and interrupt configuration, build grunt and record a baseline. Add new code, rebuild grunt and record a test output. Compare baseline against test, there should be no change in GPIO or interrupt programming. Remove code that reports GPIO/interrupt configuration. Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-25mb/google/poppy/variants/nami: Perform PL2 setting in variant_devtree_udpateFurquan Shaikh
This change moves PL2 override to variant_devtree_update for two reasons: 1. This function was added to basically override devtree settings in variant specific code. So, it would be a good idea to perform all the overrides in a single place. 2. Adding a device for performing nami_enable would require changes to devicetree and special handling for calling this device enable. Thus, nami_enable was never getting called. BUG=b:80148703 Change-Id: Ifa24a7b6e99cad2368b3d656a757f26297373121 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-25mb/google/reef: fix indention in memory.cAaron Durbin
In cbdbf018 (mb/google/reef/variants/: Add new memory ID) a new memory configuration entry was added. However, it was using spaces for indention. Correct that. Change-Id: Iaf788b0ad8a6ef3b001e7f29a6710e6e8f731ecf Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/26513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-25mb/google/poppy/variants/nami: Use GPP_E4 for BT_OFF#Frank Wu
The BT W_DISABLE2# pin is connected to GPP_E4 in the latest schematic. Update GPP_E4 as GPO and set 1 as default. BUG=b:79993692, b:72007632 BRANCH=None TEST=Enable/disable BT/WLAN by following command. Enable: localhost ~ # iotools mmio_write32 0xfdae0590 0x40000201 localhost ~ # iotools mmio_write32 0xfdae05a0 0x40000201 Disable: localhost ~ # iotools mmio_write32 0xfdae0590 0x40000200 localhost ~ # iotools mmio_write32 0xfdae05a0 0x40000200 Change-Id: I9ef1a5314652ab29172d246abd58ee4e1a8a6299 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26502 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-25mb/google/kahlee: Init APU_BIOS_FLASH_WP_L GPIO to reset stageDaniel Kurtz
GPIO APU_BIOS_FLASH_WP_L is first read in ROM stage to determine the state of the BIOS FLASH Write Protect signal at boot. The result of this read accumulated in the vboot state that's passed on to the upper layers of the stack. Therefore this GPIO must be configured as a "reset stage" GPIO, not a "RAM" stage GPIO. BUG=b:79866233 TEST=firmware_WriteProtect Change-Id: I1d96ab4bbfeaf9db9f74cf0c58cbab2104079bf7 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26498 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24mb/google/reef: Remove unused DPTF_CPU_ACTIVE_ACx definesSumeet Pawnikar
ApolloLake based reef platform is fan-less design. We do not need these DPTF_CPU_ACTIVE_ACx defines. Removing these from all reef variants as those are not being used. Change-Id: Id3cb7f7826a5e02cf447c70ab5cdc9b5d86982ca Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/26468 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24src: Remove space after `defined`Elyes HAOUAS
Change-Id: If450a68e98261ffba4afadbce47c156c7e89e7e4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26460 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24mb/google/poppy: Enable SAR config on NamiAmanda Huang
This change enables SAR config on Nami with CHROMEOS option. BUG=b:75077304 BRANCH=master Change-Id: I8217333db2db6c0fd5e1c144dedd3692b1e1e6a3 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-23mb/google/kahlee/dsdt.asl: Add method _SWSRichard Spiegel
_SWS is the recommended method of wake source retrieval. Now that PM1I and GPEI are available at NVS, add the method _SWS to kahlee/grunt ACPI code. BUG=b:76020953 TEST=Build grunt Change-Id: I5930438af40e6f9177462582cafb65401d9c60f4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-23mb/google/poppy/variants/nocturne: enable MKBPNick Vaccaro
BUG=b:79617938 BRANCH=none TEST="emerge-nocturne coreboot chromeos-bootimage", flash nocturne, boot to kernel, run evtest and verify that cros-ec-buttons is present and functional. Change-Id: Id710782e1f4e18eaac2a90c7c0f91af5223dbce3 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/26320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-23mb/google/poppy/variants/nocturne: enable I2C #5 busNick Vaccaro
Enable I2C #5 for rear camera and SAR. BUG=b:79784124 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage' and verify i2c bus #5 is detected. Change-Id: Ic5b754fb97231aeab0278d71f8ced9343c30feda Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/26319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-23mb/google/poppy/variants/nocturne: deassert audio amp resetNick Vaccaro
Drive SPKR_RST_L (GPP_A19) high at boot to take audio amps out of reset. BUG=b:78122599 BRANCH=none TEST="emerge-nocturne coreboot chromeos-bootimage", boot to kernel, and verify sound works via "aplay /dev/random" Change-Id: Ia49931f2dc7802edc8a46114b081e4a96eeee604 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/26317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-23mb/google/poppy/variants/nocturne: add touchscreen register infoNick Vaccaro
- add ACPI register information for touchscreen WCOM digitizer BUG=b:78122599 BRANCH=none TEST="emerge-nocturne coreboot chromeos-bootimage" and verify touchscreen on Nocturne board works. Change-Id: I9790a930e8ed2748d568ce58c931ce34b3e22007 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/26316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-22mb/google/octopus: Re-size flash WP_RO segmentSrinidhi N Kaushik
Update the size in WP_RO segment of the flash to accommodate latest FSP builds with debug. CQ-DEPEND=CL:*627827 Change-Id: Ic0eb9254421e99c8d204d8dbb86e6c6c2ec8719c Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/26186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-22mainboard/google/kahlee: Update RW_LEGACY size in fmapMartin Roth
Add the unused space to the RW_LEGACY area. BUG=b:79433466 TEST=None Change-Id: I897d1dcf75466fe9bdb814c8a9db0fecb5c42af6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-22google/kahlee: Swap UNIFIED_MRC_CACHE and RW_SECTION_A in fwmapDaniel Kurtz
The firmware_Mosys FAFT test does not allow RW_SECTION_A, RW_SECTION_B or RW_SHARED to be 0-sized, nor located at offset 0x00000000. Swap UNIFIED_MRC_CACHE and RW_SECTION_A to pass this test. BUG=b:79865447 TEST=test_that -b grunt ${IP} firmware_Mosys Change-Id: If60919fd998ac786d58a5a258d7b5ded727db64b Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-22rk3399: Enable bootblock compressionJulius Werner
This patch enables the new bootblock compression feature on RK3399, which requires moving MMU initialization into the decompressor stage and linking the decompressor (rather than the bootblock) into the entry point jumped to by the masked ROM. RK3399's masked ROM seems to be using a bitbang SPI driver to load us (very long pauses between clocking in each byte), with an effective data rate of about 1Mbit. Bootblock loading time (as measured on a SPI analyzer) is reduced by almost 100ms (about a third), while the decompression time is trivial (under 1ms). Change-Id: I48967ca5bb51cc4481d69dbacb4ca3c6b96cccea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-21google/kahlee: Reduce UMA memory to 32MBMarshall Dawson
Lower the amount of UMA memory to 32MB at AMD's request. TEST=none BUG=b:79906569 Change-Id: Ib1365dc38850b4b92c944ff95534573addbe4362 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-21google/grunt: Reduce UMA memory to 32MBMarshall Dawson
Lower the amount of UMA memory to 32MB at AMD's request. TEST=boot Grunt, try S3 BUG=b:79906569 Change-Id: I5af038688b38b53c94b8265823eeee0f37980522 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-21mb/google/octopus: Add devicetree for BipJustin TerAvest
Bip should have different devicetree entries than Yorp; it doesn't have a DA7219 audio codec (instead it uses ALC5682). BRANCH=none BUG=b:79771967 TEST=boot, no longer see DA7219 ACPI in console. Change-Id: Ic63bbc51e122afc9fc2e8ec7fb024d18a3815b38 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/26342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-05-19mb/google/octopus: enable xdci controllerJagadish Krishnamoorthy
BUG=b:79343083 BRANCH=NONE TEST=On Yorp board, lspci should list xdci, 00:15.1 USB controller Change-Id: I3a4878389a1b5b7abcaccf6ab16b67848aaaee83 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/26358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-19mb/google/reef/variants/: Add new memory IDren kuo
Add a new RAM ID of memrory PN:K4F6E3S4HM-MGCJ BUG=b:78491470 TEST= emerge-coral coreboot chromeos-bootimage. Change-Id: Ic40e36ab222572945f8588eb3df063e4fe0dbeb5 Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/26365 Reviewed-by: Ren Kuo <ren.kuo@quantatw.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18mb/google/eve: Describe USB devices in devicetreeDuncan Laurie
Describe the USB devices in the devicetree so they can get generated into the SSDT and presented to the OS. This was tested on an eve board and the resulting SSDT was verified to show the expected values in _UPC and _PLD. Change-Id: I292426f588ea74d61a5c4e4b01386bb18834c117 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-18mb/google/poppy/variants/nami: Fix SoC I2C CLK is abnormalChris Zhou
The I2C CLKs of SoC should be 400kHz, but waveform show 460kHz to 470kHz. Add I2C parameters to adjust I2C CLKs which 5% lower than 400kHz. BUG=b:78819970 TEST=The I2C CLKs are 5% lower than 400kHz. Change-Id: I2c3012b5b59c089801cda8fd7b0c433aad9df36d Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26282 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18mb/google/poppy/variants/nocturne: enable pogo pin USB portNick Vaccaro
BUG=b:78122599 BRANCH=none TEST="emerge-nocturne coreboot chromeos-bootimage" and verify pogo pin port is working. Change-Id: Ide7359366821f33c4746284e65cacdf4e240931d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/26315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-18mb/google/octopus: Disable BT before S5 entryHannah Williams
The CNVi wifi/bt module prevents entry into S5 by keeping internal SoC clocks running. Therefore it's necessary to disable BT prior to S5 entry. BUG=b:79606769 TEST= Test if BT device works under following cases: 1. Power-on 2. Press powerbtn before OS entry 3. Power-on from S5 again Change-Id: Ibc14b4080a27de48d197e16d0eed162603482de2 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/26238 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-17mb/google/poppy/variants/nami: Update DPTF tableJohn Su
Update dptf.asl from tuning of the thermal team. BUG=b:72974136 TEST=Match the result from DPTF UI. Change-Id: I21ddc337359c3e11ad9756e61ba174b33dfc3c75 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-05-17mb/google/poppy: Disable one ALS nodeAmanda Huang
Since there are two ALS device nodes on Nami, need to remove one. BUG=b:79227879 BRANCH=master TEST=Verify if only one ALS node is found in /sys/bus/iio/devices Change-Id: I850af06bec833739afa0c8c516d351d81952ce2c Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26271 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-16mb/google/poppy/variants/nami: Load pantheon VBT binaryIvy Jian
Load pantheon.bin by reading sku-id. BUG=b:78663963 TEST=Boots to OS and display comes up. Check the board specific vbt binary loaded. Change-Id: I66cb43d87363b3e8b1a1498cdae8eeeb8b75219d Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-16mb/google/poppy/variants/nami: Enable synaptics touchscreen supportIvy Jian
BUG=b:74595040 BRANCH=master TEST= 1. emerge-nami coreboot chromeos-bootimage 2. Booted on Pantheon with S7817 PCBa connected 3. Check touchscreen device is enabled by evtest /dev/input/event4: SYTS7817:00 06CB:7817 Change-Id: Ic11684d5ed961af5eb704909f7d06eb0898068c2 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-15mb/google/fizz: Add device index for dual LAN skuDavid Wu
Fix dual LAN sku can't inherit correct MAC from VPD setting. BUG=b:77836343 BRANCH=Fizz TEST=Program the mac address to VPD in shell vpd -s ethernet_mac0=<mac address1> vpd -s ethernet_mac1=<mac address2> && reboot the system. Ensure the MAC address was fetched correctly by ifconfig command. Change-Id: Ic357a3f1435d6d08107520e40872f1003ef2edf3 Signed-off-by: David Wu <david_wu@quantatw.com> Reviewed-on: https://review.coreboot.org/25587 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-12mb/google/poppy/variants/nami: Provide implementation of mainboard_vbt_filenameFurquan Shaikh
This change adds board-specific implementation of mainboard_vbt_filename which returns "vbt.bin" by default. This is in preparation to allow multiple vbt binaries to be added to single image. More sku_id specific names will be added in follow-up CLs. BUG=b:79396300 Change-Id: I3821d55bfbe9e5773bd2eb0b0003045a80158d8c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-11mainboard/google/coral: Override VBT selection for epauletteren kuo
Current VBT setting for T8 is only 1ms which is under Innolux N116BCA-EA1 panel's spec. Modify T8 to 100ms. (Innolux's panel's spec requires T8 needs to be greater than 80ms BUG=b:78541692 BRANCH=master TEST=emerge-coral depthcharge coreboot chromeos-bootimage Run on DUT and check panel sequence meets spec. Change-Id: I5f9103aca7871095a828a74cd6a97e1951adb81f Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/26214 Reviewed-by: Ren Kuo <ren.kuo@quantatw.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11mb/google/reef/variants/: Add new memory IDren kuo
Add a new RAM ID of memrory PN:MT53E512M32D2NP BUG=b:78491470 TEST= emerge-coral coreboot chromeos-bootimage. Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Change-Id: I855702c2850887df74941e00da69322124557498 Reviewed-on: https://review.coreboot.org/26213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
2018-05-11mb/google/poppy/variants/atlas: add SPD for new samsung 4GB memoryCaveh Jalali
This adds a new SPD entry for samsung's new 4GB memory and updates atlas to use it instead of the previous gen memory. BUG=b:79444337 TEST=booted on atlas Change-Id: I19567736c45a1321586378c3d964c2cbebe24755 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/26185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-11mb/google/octopus: Ignore standby state for DMIC pinsShamile Khan
This keeps Audio clock and data pins ON in S0ix to support Wake on Voice. BUG=b:77605180 BRANCH=none TEST=Checked that S0ix suspend/resume works. Validation of WoV was done on glkrvp previously. For Yorp, audio topology firmware updates are required for testing WoV. Change-Id: Idafe4e7d24fe16f8e8ff3dd86e299776ea860d03 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/26202 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11mb/google/poppy/variants/nami: add 2-channel LPDDR3 memoryT.H. Lin
hynix/H9CCNNNCLGALAR-NUD nayna/NT6CL256T32CM-H1 BUG=b:79443146 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I3a362080b9e60adecbac14d5cfe193da44bf87c8 Signed-off-by: T.H. Lin <t.h_lin@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-09mainboard/google/.../terra: Fix ACPI external definition errorsMartin Roth
According to ACPI 6.1 spec 19.6.44, External informs compiler that object is external to this TABLE, no necessary for object in same DSDT tables. A name cannot be defined and declared external in the same table (GPID) A name cannot be defined and declared external in the same table (CTOK) Change-Id: Ica80b59ad6a8af865bf1551ac4e014ec5f4e7d08 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26122 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09mb/google/poppy/variants/nocturne: update Audio configurationSathyanarayana Nujella
This patch updates the below: 1) Nocturne board has only Max98373 speaker amp. Update both NHLT and DT entries to include only Max98373 and not include DA7219. 2) I2S2 is used for Boot Beep. So, update GPP_F0 ~ F2 pins accordingly. 3) Include DMIC-4ch configuration. BUG=b:79362472 TEST=None [Waiting for HW to verify] Change-Id: I0e9b3a564c22de6e84e96e5e937a3aca4ae73d75 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/26143 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09drivers/intel/gma, soc/intel/common: improve cooperationPatrick Georgi
Instead of both featuring their own VBT loaders, use a single one. It's the compression-enabled one from soc/intel/common, but moved to drivers/intel/gma. The rationale (besides making all the Kconfig fluff easier) is that drivers/intel/gma is used in some capacity on all platforms that load a VBT, while soc/intel/common's VBT code is for use with FSP. BUG=b:79365806 TEST=GOOGLE_FALCO and GOOGLE_CHELL both build, exercising both affected code paths. Change-Id: I8d149c8b480e457a4f3e947f46d49ab45c65ccdc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/26039 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09src/mainboard: Serialize methods with named objects insideMartin Roth
Change-Id: I90e1d8b9f8e37bec8fc2796637b4548ea17e076b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-09mainboard/google/eve: Add subsystem_idHarsha Priya
This patch adds subsystem_id for eve as 0x006B. The value is set in nhlt structure which will be used by endpoints as well. Change-Id: Id6910678c4d6e92ed45c776f174855efd26f9e27 Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/26139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-09mb/google/poppy/variants/nami: Add support for getting OEM name from CBFSFurquan Shaikh
This change: 1. Allows mainboard to add OEM table to CBFS 2. Provides mainboard specific smbios_mainboard_manufacturer that reads OEM ID from EC using CBI and compares it against the OEM ID in CBFS table to identify the right OEM string. BUG=b:74617340 Change-Id: Iff54b12745de3efa7be0801c9a3a9f2a57767dde Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08mb/google: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I8e549e4222ae2ed6b9c46f81c5b5253e8b227ee8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08mb/superio: Rename global control devices as SUPERIO_DEVElyes HAOUAS
Use SUPERIO_DEV for global control device instead of DUMMY_DEV. Change-Id: If3555906d359695b2eae51209cd97fbaaace7e61 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25852 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08mb/google/poppy/variants/atlas: update DMIC NHLT configurationSathyanarayana Nujella
From coreboot side, include DMIC 4ch NHLT configuration and its DMIC blob. In OS side, cras picks the needed channels using UCM's channel map configuration. So, this patch updates to include DMIC 4ch config. BUG=b:79158926 TEST=Verified 4-ch record with arecord TEST=Also verified internal mic record with cras using 'cras_test_client --capture_file dmic.raw --rate 48000 --num_channels 2 --duration 10' Change-Id: Ic6df00c2f26ad9cdf54152ab021c2b10499c429c Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/26019 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08mb/google/eve: Change rt5663 audio codec's irq as ExclusiveAndWakeHarsha Priya
This patch uses GPIO macro to define rt5663 headset codec's irq as ExclusiveAndWake. This change allows jack detection even when device is in D3 state. TEST=Plug in/out jack when the system is in deep sleep and wake up the system to ensure that jack insertion/removal is detected. Change-Id: Icb72337025a8408ed7ea9b6e60e938dcb88eae76 Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/26016 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08src/mainboard: Set ACPI OEM ID values to 6 characters longMartin Roth
Change OEM ID values to 6 characters to fix error compiling with IASL version 20180427. Also update table creator to 8 characters from 7. Change-Id: Id6c9a7b08dc4a9efeb69011393e29aa5a6bc54c4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-07mb/google/poppy/variants/nami: Invert polarity of EMR_GARAGE_DET#Shelley Chen
This gpio should be active low, but is not currently configured that way. Changing gpio configuration to reflect that. BUG=b:73121017, b:77941823 BRANCH=None TEST=iotools mmio_read32 0xfdae0588 (GPP_E1) Make sure that when pen is ejected, gpio is low and when pen is inserted, gpio is high. Also tested that wake upon pen eject is working. Change-Id: Ic49eea6412c3378dca39a3338b43df12bc27037d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/26017 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-04mainboard/google/kahlee: Pass oscout system clk to da7219Akshu Agrawal
Using da7219 mclk-name property, oscout system clock is linked to da7219 mclk. da7219 then handles enabling/disabling of the clk. BUG=b:74570989 TEST=Tested clock enable/disable in kernel driver Change-Id: I298b0ce5d2c40daadeb5d68f9cb595a965272021 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/25920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04google/kahlee: Revert "Resume on AC insertion"Martin Roth
This reverts commit edf2f59b1d93a1bc9161a67d3c00a9a05fa8519a. (google/kahlee: Resume on AC insertion) The requirement to wake on AC insert is just to wake enough to charge, not to wake the entire system. BUG=b:77602394 TEST=None Change-Id: I0ee709183b1605c1efc0fce673db512fac66adfa Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26014 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-04mainboard/google: Comment variant names in KconfigMartin Roth
It's very confusing trying to find the google platform names, because they seem all unsorted in Kconfig. They're actually sorted according to the variant name, but previously, that was impossible to tell. - Add a comment to the top of variants in Kconfig.name - Inset each variant name. If you start a prompt with whitespace, it gets ignored, so after trying various ways to indent, the arrow was the option I thought looked the best. It now looks like this: *** Beltino *** -> Mccloud (Acer Chromebox CXI) -> Monroe (LG Chromebase 22CV241 & 22CB25S) -> Panther (ASUS Chromebox CN60) -> Tricky (Dell Chromebox 3010) -> Zako (HP Chromebox G1) Butterfly (HP Pavilion Chromebook 14) Chell (HP Chromebook 13 G1) Cheza *** Cyan *** Change-Id: I35cb16b040651cd1bd0c4aef98494368ef5ca512 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-03mainboard/google/kahlee: Update grunt touchscreen in devicetreeMartin Roth
- Add raydium controller - Update elan controller with reset and enable GPIOs. - Enable 'probed' so Linux will check which controller is being used. BUG=b:78929054 TEST=Both elan and raydium touchscreen controllers work Change-Id: I3bd9912a4b1edc7bf1075cb649afa3eab5dca458 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25998 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-03mainboard/google/reef: Remove tablet mode switch supportMartin Roth
The _SB.DPTF.TPET ACPI code attached to EC_ENABLE_TABLET_EVENT doesn't exist in the apollo lake code. Remove it from reef as part of the cleanup to update to the new version of IASL. This was in commit 4f803ac28f4 (mainboards/google/reef: Add support for tablet mode switch.) Change-Id: Ic10c418ddc708c1aed87ad4a9861f04d32445116 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25982 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-02google/kahlee: Set SPI 100 MHz and SPI Dual Read IO modeMarc Jones
Set SPI Fast Read to 100MHz and Dual Read IO mode to speed up the boot process by over a half second. Also, increase the Normal Read speed to 33MHz as supported by the W25Q128FW. BUG=b:70558952 TEST=Run cbmem -t to get boot times. Change-Id: I616a96526ed90bb4ab0c9c6b78787799faa02633 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-02mb/google/kahlee/variants/grunt: Enable BayHub720 driverSimon Glass
Enable this driver along with power saving. BUG=b:73726008 BRANCH=none TEST=boot and see this message: BayHub BH720: Power-saving enabled 110103 From linux: $ iotools pci_read32 2 0 0 0x90 0x00110103 Change-Id: I850e923f73e01fe629d66ad61b65afa58035845c Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/25967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-02mb/google/poppy/variants/nami: Enable touchscreen through ACPIShelley Chen
Currently, we've set TOUCHSCREEN_DIS gpio to disabled. Enabling through ACPI. Set reset/enable/stop_off_ms variables to get timings of power off sequence correct. BUG=b:78311818 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: Ib1543f41f24cbe8c33aeb02e6aa43fd3dd977ed4 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/25754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-05-02mb/google/octopus: Configure pins to reflect delta w.r.t yorpShamile Khan
Changes in pin usage between yorp and bip - LTE_OFF_ODL pin moved from GPIO_161 to GPIO_66 - I2S0 interface is not used in bip. It was used in yorp for DMIC Wake on Voice through Nuvoton EC. Also fix both bip and yorp pin settings for LTE_OFF_ODL (Enable LTE and add an internal pull up). Internal pull up can be removed later when sub-board (which will have an external pull up for this signal) is available. BUG=b:77869623 BRANCH=none TEST=Build coreboot for octopus. Change-Id: I8907bd63a43c4bc51ca991c3ec7c1cae9e39e2d1 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-01mb/google/poppy: Add variant for nocturneNick Vaccaro
Add a new variant of poppy for the nocturne board. Key differences from baseboard include: - GPIO changes - devicetree.cb changes - memory stuffing option changes BUG=b:78122599 BRANCH=none TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: I11c7829041b3c45407c17f71b08cc7fc17f717e8 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/25803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-01mb/google/poppy/variants/nami: Enable Synaptics touchpadivy_jian
BUG=b:74595037 TEST= 1. emerge-nami coreboot chromeos-bootimage 2. check touchpad function 3. evtest /dev/input/event5: PNP0C50:00 06CB:CD84 Change-Id: I47cb1b13881f0d52860f0afe4bbca7483409de54 Signed-off-by: ivy_jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25913 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-01chromeec platforms: Update ACPI thermal event handler callMartin Roth
Currently the thermal event handler method TEVT is defined as an extern, then defined again in platforms with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. Change-Id: I64dcd2918d14f75ad3c356b321250bfa9d92c8a5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-30google/poppy: enable trackpad as wake sourceCaveh Jalali
This configures GPP_A23 as a wake source for the trackpad. We also need to set up GPP_A GPE0_DW0, thus evicting GPP_B. We don't have any interesting signals in GPP_B, so we won't be missing it. I don't have hardware with A23 wired up, so i just tested the wake source using A19 which is essentially identical to A23. BUG=b:78541883 TEST=verified we can trackpad can wake system from suspend Change-Id: If800464c8b2319d758b1823850571919f85bdc6c Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/25850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-30mb/google/octopus: Create phaser variantJustin TerAvest
This creates a phaser variant for octopus. Nothing is set in the variant files here; everything is picked up from baseboard. BUG=b:78572180 TEST=None Change-Id: Ia03e8af91741f1f7aa3a42ac28688b8b6a708932 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-30mb/google/octopus: save dimm info as SMBIOS Table-17Ravi Sarawadi
Save FSP provided memory HOB info as SMBIOS Table-17 format. Firmware tools such as mosys, dmidecode uses SMBIOS Table-17 to report memory metadata. BUG=b:78651920 TEST=Build for Octopus and check 'dmidecode -t17' and 'mosys memory spd print all' to verify dimm info. Change-Id: I9b032b766a2927725b2378f7f720644d4459f602 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/25881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-30mb/google/octopus: Fix crossystem wpsw_cur errorHannah Williams
With only one entry for Write Protect gpio in the OIPG package, the sysfs entry /sys/devices/platform/chromeos_acpi/GPIO.x is created as "GPIO" instead of "GPIO.x". This was causing crossytem to return error for wpsw_cur. BUG=b:78009842 Change-Id: Ica60f342420d95d09a45580f2f940443c03601de Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-28mb/google/octopus: Enable pull on ESPI_IO1 lineFurquan Shaikh
This change configures a weak internal pull-up on ESPI_IO1 line for octopus baseboard and variant bip. ESPI_IO1 is used as ALERT# line and is expected to be open-drain. However, there is no external pull on this line and so an internal pull-up is required to ensure proper eSPI communication. BUG=b:78497502 TEST=Verified that there is no eSPI communication failure between AP and EC during boot-up and on suspend/resume. Change-Id: Ic494aa7397b94bfd233ce10da8287660997b3377 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com>
2018-04-27google/kahlee: Remove VBOOT_VBNV_CMOSMarc Jones
Remove VBOOT_VBNV_CMOS from the mainboard. It is selected in the stoneyridge Kconfig. BUG=b:77347873 TEST=Manually clear CMOS and check coreboot restores VBNV from flash. Change-Id: I30e517e06ab9d8f7d4a93bf82f12726756c44966 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-27google/kahlee: Add RW_NVRAM to FMAPMarc Jones
Add RW_NVRAM area to FMAP for VBOOT_VBNV_CMOS_BACKUP_TO_FLASH support. BUG=b:77347873 TEST=Manually clear CMOS and check coreboot restores VBNV from flash. Change-Id: Id8c6f54634b94bf6ae3755a827e80d0862a42dd2 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-27mb/google/poppy,soraka,nautilus: Enable xDCIFurquan Shaikh
This change enables xDCI controller on poppy, nautilus and soraka. BUG=b:78577893 BRANCH=poppy Change-Id: I9b0f81bda889b822479ead4d1acc2b613151a304 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25849 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26mainboard/google/kahlee: Set SPI speed in bootblockMarc Jones
Set the SPI speed for Normal, Fast, AltIO, and TPM in bootblock. This setup is needed when moving AGESA out of the bootblock. It sets the SPI bus speed of the TPM access in verstage. BUG=b:70558952 TEST=Boot with AGESA moved out of the bootblock. Change-Id: Ida77d78eb1f290e46b57a46298400ed6c8015e2c Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-26mb/google/octopus: Add dptf.asl in dsdt.aslSumeet Pawnikar
This patch enables dptf for Octopus by adding dptf.asl in dsdt.asl. BUG=b:74263914 BRANCH=None TEST=None Change-Id: I7194cdd2af88ff062ebcc92cc97b3cdc3d21ecd6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/25809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-26mb/google/grunt: Add grunt touchpad wake GPE to devicestreeDaniel Kurtz
The grunt touchpad interrupt can be used as a wake source. For grunt, the touchpad interrupt uses GPIO5 which corresponds to GEVENT7. BUG=b:77602771 TEST=In OS: # cat /proc/acpi/wakeup => D015 S3 *enabled i2c:i2c-ELAN0000:00 TEST=powerd_dbus_suspend, touching touchpad (> 1 sec) wakes from S3. Change-Id: I510642108a1257f6601f18c77cf3107573427f39 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25827 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26mainboard/google/kahlee: Enable EC wake on GPIO24Daniel Kurtz
The grunt EC uses GPIO24 (EC_PCH_WAKE_L) to signal wake-up events to the AP. On Stoney, GPIO24 maps to GEVENT (GPE) 15. The kahlee EC uses GPIO2 (EC_PCH_WAKE_L) to signal wake-up events to the AP. On Stoney, GPIO2 maps to GEVENT (GPE) 8. BUG=b:78461678 TEST=powerd_dbus_suspend, tap any key on keyboard wakes from S3. TEST=sign in, EC: lidclose, EC: lidopen => system wakes from S3. Change-Id: Ib1809740837e686992ff70b81933159a5dff7595 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-04-26mainboard/google/kahlee: Fix EC_SMI_GPIDaniel Kurtz
On the kahlee variant, EC_SMI_ODL is connected to GPIO6, which uses GEVENT 10 (GPE10). Fix this up, and also clean up the EC_*_GPI definition format a bit to match the format in the baseboard/gpio.h. BUG=b:78461678 TEST=build coreboot for kahlee Change-Id: I9445efbc02559c2a7c90f67bcb0154b04b03a1aa Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-04-25mb/google/octopus: Disable PCIE NPK deviceShaunak Saha
This patch sets the NPK device off for octopus. BUG=b:76115112 TEST=Build for Octopus and check that the logs do not report "PCI: 00:00.2 not found, disabling it". Change-Id: I3ac01f90cf946b019a6604a38dd1d6782f8d5759 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25801 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-24mb/google/kahlee/variants/baseboard/gpio.c: move all non-critical gpiosRichard Spiegel
When GPIO tables were created, there was no study on which pins had to be programmed ASAP and which could be programmed later. Execute such study and move all non-critical gpios from reset to late. BUG=b:76097508 TEST=Build and boot grunt to OS, test OS for lost functionality (WIFI, video playback, track pad, keyboard). Change-Id: Icbc9370050d619800026035caaac3e89536a460a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-24mb/google/cyan/spd/spd.c: Fix module part number transferRichard Spiegel
With the increase of dimm->module_part_number size from 19 to 21 (commit 35b273eea3) "include/memory_info.h: Change part number field from 19 bytes to 21", this code is now advancing outside DDR3 SPD designated space. The correct size is already defined as LPDDR3_SPD_PART_LEN, use it. Also make sure to 0 terminate the string. BUG=b:77943312 TEST=Build cyan. Change-Id: Iba0ef4149acfc09b7672fce079df06bf1a01dff6 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-24mb/google/poppy/variants/nami: Add keyboard backlight supportZhuohao Lee
This change adds keyboard backlight feature for Nami platform BUG=b:78360907 BRANCH=none TEST=keyboard backlight works when EC reports correct info. Change-Id: I3fceb83e155032b6e9f1763c4e2a29e7521269d2 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/25782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-23mb/google/poppy/atlas: Enable trackpadCaveh Jalali
This enables the i2c trackpad on atlas. BUG=b:75454415 TEST=able to move pointer using trackpad Change-Id: If4a82aa605ec68fd38e52c13406eaf803f9e86cc Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/25759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-21mb/google/bip: Add GPIO configuration settingsShamile Khan
These settings are identical to yorp settings except overrides are not provided for sleep_gpio[] table which is currently empty for yorp and cros_gpios[] table which is not expected to change for bip. BUG=b:77869623 BRANCH=none TEST=Build coreboot for bip. Change-Id: Icc205f576691427d78c9159dfdbced87e41a0517 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-20pci: Move inline PCI functions to pci_ops.hPatrick Rudolph
Move inline function where they belong to. Fixes compilation on non x86 platforms. Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25720 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-20soc/amd/stoneyridge/include/soc/southbridge.c: Rename gpio structureRichard Spiegel
The GPIO definition structure has evolved to a point where it's no longer specific to stoneyridge, though probably still specific to AMD. Therefore, rename the GPIO declaration structure removing stoneyridge from it. BUG=b:72875858 TEST=Build kahlee, grunt, gardenia. Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25726 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-19mb/google/octopus: Select DRIVERS_I2C_HIDFurquan Shaikh
This change selects DRIVERS_I2C_HID which is required for adding SSDT node for digitizer. BUG=b:78099046 Change-Id: I526c0ac7b88dec7b2b22d022d911840555f15cde Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-18soc/amd/stoneyridge/include/soc/gpio.h: Remove vendor code referenceRichard Spiegel
With the exception of code that deals directly or indirectly with AGESA, all other code should be independent of vendor code reference. Therefore, remove vendor code reference from any GPIO code. BUG=b:77999987 TEST=Build and boot grunt. Change-Id: I9ba78767a269ad6b9b06fa11993d8a12350e4bad Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25695 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-03 14:16:12 +0000