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2017-01-04google/auron: Fix omitted ACPI KB backlight for variantsMatt DeVillier
Restores KB backlight functionality for auron variants gandof, lulu, and samus. TEST: boot Lulu and observe KB backlight functional Change-Id: Iaa852f9327ff1690111db610b4cc5266cd7925b4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17960 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03Revert "google/oak: increase the driving strength for 4GB DRAMs"Nicolas Boichat
This reverts commit 34a6537512d412363bf56428b7ae284e6dd80fb3, which appears to cause random stability issues on some elm units. BRANCH=oak BUG=chrome-os-partner:60869 BUG=chromium:673349 TEST=None Change-Id: I5ce9e2673db1bc7a1f487a3c3bcce4651a5e3567 Reviewed-on: https://chromium-review.googlesource.com/419862 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18005 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03google/snappy: Update DPTF settingsWisley Chen
1. Update DPTF TSR1/TSR2 passive/critial trigger points. TSR1 passive point:53, critial point:80 TSR2 passive point:90, critial point:100 2. Update PL1 Min to 4W and PL1 Max to 12W 3. Update thermal relationship table (TRT) setting. BUG=none BRANCH=master TEST=build, boot on snappy dut and verified by thermal team member. Change-Id: I8b4fb178daa7c2e4091a14779a125bd5e943d023 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17955 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-03mainboard/google/reef: Update DPTF parameters EVT1_v0.3Tim Chen
Update the DPTF parameters based on thermal test result. (ZHT_DPTF_EVT1_v0.3_20161227.xlsx) 1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points. CPU critical point:103 TSR1 passive point:45 TSR2 passive point:55, critical point:90 2. Change thermal relationship table (TRT) setting. Change CPU Throttle Effect on CPU sample rate to 3secs Change Charger Effect on Temp Sensor 2 sample rate to 60secs Change CPU Effect on Temp Sensor 1 sample rate to 8secs BUG=chrome-os-partner:60038 BRANCH=master TEST=build and boot on electro dut Change-Id: I3746750f7ea4a2e01153a36c28a5c33140c9e38c Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17975 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-26google/eve: Enable internal pull-up on PWRBTN#Duncan Laurie
Enable an internal pull-up on the power button input as a quick press is resulting in power button override being asserted. BUG=chrome-os-partner:61312 TEST=tested on eve P0b to ensure quick power button press does not result in a shutdown due to power button override. Change-Id: I3028cf7faef309cf4d60c3585b48adab6e1549d4 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17962 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-26mainboard/google/chell: Set TCC activation offset to 10 degree CSumeet Pawnikar
With the default TCC activation offset value as 0 and Tjmax temperature value as 100 degree C, Pcode firmware starts taking prochot action at 100 degree C [Tjmax-Offset]. But before Pcode firmware starts prochot action at 100 degree C, device is getting shutdown at 99 degree C due to DPTF critical CPU temperature. This patch sets TCC activation offset value to 10 degree C for thermal throttle action to prevent this kind of shutdown. BUG=chrome-os-partner:59397 BRANCH=None. TEST=Built, booted on skylake and verified target offset value. Change-Id: I0811ef481a4b3ce4bd6ef24f2aa8160f44f9c990 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17921 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-23spi: Get rid of SPI_ATOMIC_SEQUENCINGFurquan Shaikh
SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with the ability to perform tx and rx of flash command and response at the same time. Instead of introducing this notion at SPI flash driver layer, clean up the interface to SPI used by flash. Flash uses a command-response kind of communication. Thus, even though SPI is duplex, flash command needs to be sent out on SPI bus and then flash response should be received on the bus. Some specialized x86 flash controllers are capable of handling command and response in a single transaction. In order to support all the varied cases: 1. Add spi_xfer_vector that takes as input a vector of SPI operations and calls back into SPI controller driver to process these operations. 2. In order to accomodate flash command-response model, use two vectors while calling into spi_xfer_vector -- one with dout set to non-NULL(command) and other with din set to non-NULL(response). 3. For specialized SPI flash controllers combine two successive vectors if the transactions look like a command-response pair. 4. Provide helper functions for common cases like supporting only 2 vectors at a time, supporting n vectors at a time, default vector operation to cycle through all SPI op vectors one by one. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17681 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-22Add/Combine Broadwell Chromebooks using variant board schemeMatt DeVillier
Combine existing boards google/auron_paine and google/samus with new ChromeOS devices auron_yuna, gandof and lulu, using their common reference board (auron) as a base. Chromium sources used: firmware-yuna-6301.59.B 6ed8b9d [CHERRY-PICK: broadwell: Update to...] firmware-gandof-6301.155.B 666f34f [gandof: modify power limiting for...] firmware-lulu-6301.136.B 8811714 [lulu: update RAMID table] Additionally, some minor cleanup/changes were made: - I2C devices set to use level (vs edge) interrupt triggering - HDA verb entries use simplified macro entry format - correct FADT table header version - remove unused ACPI device entries / .asl file(s) - clean up ACPI code (e.g., trackpad on Lulu) - adjust _CID for trackpad on Lulu in order to not load non-functional Windows driver (does not affect Linux) - remove unused header includes (multiple/various) - correct I2C addresses used for SMBIOS device entries - correct misc typos etc The existing auron_paine samus boards are removed. Variant setup modeled after google/slippy Change-Id: I53436878d141715eb18b8ea5043d71e6e8728fe8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17917 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-22Combine Broadwell Chromeboxes using variant board schemeMatt DeVillier
Combine existing boards google/guado, rikku, and tidus using their common reference board google/jecht as a base. Additional changes besides simple consolidation include: - simplify power LED functions - simplify HDA verb definitions using azelia macros - use common SoC functions to generate FADT table - correct FADT table header version - remove unused haswell_pci_irqs.asl - remove unused header includes (various) - set sane default fan speed (0x4d) for all variants Variant setup modeled after google/beltino Change-Id: I77a2dffe9601734916a33fd04ead98016ad0bc4b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17913 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-20mb/google/slippy: Hook up libgfxinitArthur Heymans
Both HDMI and eDP work (simultaneously). TESTED on Acer C720 (peppy). Change-Id: Ifc4e3c187bcabd8965d9586237a52b440bfa7f20 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17916 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-12-20google/eve: Fix configuration of some GPIOsDuncan Laurie
GPP_D12 needs an internal pull-up to get this rail working on current boards. GPP_D0-GPP_D3 were changed from SPI interface and I just missed this change earlier. BUG=chrome-os-partner:58666 TEST=test camera and touchpad on eve Change-Id: Idfa186f2930afbe5651f4e0fc11a19cd0dd4295f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17922 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19google/poppy: Add new boardFurquan Shaikh
Add poppy board files using kabylake and FSP 2.0. BUG=chrome-os-partner:60713 BRANCH=None TEST=Compiles successfully Change-Id: Ic9aa5093b319690ae893a21cab98d9b843000e6c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17866 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-17google/reef: Use exported GPIOs and ACPI regulator for touchscreenFurquan Shaikh
ELAN touchscreen device expects firmware to export GPIOs and ACPI regulators for managing power to the device. Thus, provide the required ACPI elements for OS driver to properly manage this device. BUG=chrome-os-partner:60194 BRANCH=None TEST=Verified that touchscreen works properly on boot-up and after suspend/resume. Change-Id: I298ca5de9c0ae302309d87e3dffb65f9be1e882e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17799 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-16google/eve: Set throttle offset to 10 degreesDuncan Laurie
Set the thermal throttle (prochot) activation to be 10 degrees below TJmax so PROCHOT# kicks in at 90C instead of 100C. BUG=chrome-os-partner:58666 TEST=boot on eve, check msr value before and after resume: > iotools rdmsr 1 0x1a2 0x000000000a6400e6 > echo mem > /sys/power/state > iotools rdmsr 1 0x1a2 0x000000000a6400e6 Change-Id: I3ab3a050a1e27c18a940bd7519eabaf015ef93eb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17901 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-16drivers/i2c/generic: Allow mainboards to export reset and enable GPIOsFurquan Shaikh
Add power management type config option that allows mainboards to either: 1. Define a power resource that uses the reset and enable gpios to power on and off the device using _ON and _OFF methods, or 2. Export reset and enable GPIOs in _CRS and _DSD so that the OS can directly toggle the GPIOs as required. GPIO type needs to be updated in drivers_i2c_generic_config to use acpi_gpio type so that it can be used for both the above cases. BUG=chrome-os-partner:60194 BRANCH=None TEST=Verified that elan touchscreen works fine on reef using exported GPIOs. Change-Id: I4d76f193f615cfc4520869dedc55505c109042f6 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17797 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-16google/eve: Enable touch devicesDuncan Laurie
Enable the actual touch devices to be probed by the kernel and remove the placeholder devices that I put in before and were used for initial bringup. BUG=chrome-os-partner:58666 TEST=tested on eve Change-Id: I7fc6f9da83b1abbae6dd069f759b220d59153d1c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17896 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-16google/eve: Enable native mode for UART pins in bootblockDuncan Laurie
Put the UART pins into native mode in bootblock so they are not floating when we try to communicate with H1 over I2C. Without a serial console enabled BIOS these pins were not configured until ramstage. BUG=chrome-os-partner:60935 TEST=Boot Eve board without serial console and H1 TPM enabled Change-Id: I30f3bf0bacc1bbd776b351a9c09748b0601c39bc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-15mainboard/google/reef: clear normal MRC cache on recovery retrainAaron Durbin
For Chrome OS the normal MRC cache should be cleared when a hardware retrain recovery request is observed. The reason is that since there are 2 different MRC cache slots there needs to be a mechanism which allows an end user make a system bootable again if the MRC settings happen to not allow the system to boot any longer. Therefore, one just needs to enter recovery with the hardware retrain flag and the system normal MRC cache slot will be invalidated. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: I6ad32ed0dd217d66404b77467a88689a06044544 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17871 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-15google/reef: Remove VARIANT_DIR definitionMartin Roth
VARIANT_DIR is defined in coreboot/Makefile.inc, so doesn't need to be defined in each mainboard. Change-Id: Ic93957b710e4a9863774de7fcf3bd006696b6aa1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17841 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-14google/eve: Configure I2C3 pins as GPIO inputsDuncan Laurie
On this board i2c3 bus is connected to the display TCON, but it is acting as the master when it has power so it can read from its own EEPROM on the bus. In order to prevent any possible issues in S0 make these pins input on the SOC. BUG=chrome-os-partner:58666 TEST=tested on eve board, but this bus was not used before so there is no visible change in behavior. Change-Id: Ide32f45ee33ca986fd3249a5161e01edf99d6e22 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17800 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13mainboard/google/reef: implement phase enforcement pinAaron Durbin
On upcoming boards an optional pull up is applied on GPIO_10 to indicate if the board should have security features locked down for a shipping system. Provide a weak pull down so that all boards will indicate a logic 0 until the stronger pull up resistor is stuffed. BUG=chrome-os-partner:59951 BRANCH=reef Change-Id: I6f514a69bccd05ca02480f3c30d0ad503a955b1e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17803 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-13vendorcode/google/chromeos: Fill in firmware ID regionsPatrick Georgi
Chrome OS images have three firmware ID regions, to store version information for the read-only and the two read-write areas. Fill them with a suitable default and allow configuring a different scheme. There's already an override in google/foster and google/rotor to match the naming scheme used so far (in depthcharge). BUG=chromium:595715 BRANCH=none TEST=/build/$board/firmware/coreboot.rom has the expected values in the regions. Change-Id: I5fade5971135fa0347d6e13ec72909db83818959 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d2e3be81faa8d21f92325294530714a4b18a1b3e Original-Change-Id: I2fa2d51eacd832db6864fb67b6481b4d27889f52 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/417320 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://review.coreboot.org/17788 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-12google/pyro: Set PL2 override to 15000mWKevin Chiu
This patch sets PL2 override value to 15W in RAPL registers and sets DPTF PL2 Max to 15W BUG=none BRANCH=reef TEST=emerge-pyro coreboot Change-Id: Ibadf0fa442f556d018c249b1cf88e29c4d57c97f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17779 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09mainboard/google/reef: fill in NHLT ACPI OEM header fieldsAaron Durbin
Fill in the NHLT ACPI OEM header fields to differentiate different audio solutions on a per board basis. This handles boards that share a firmware that are differentiated by the SKU id and boards that have their own firmware. For the latter, the Oem Table ID uses the VARIANT_DIR to differentiate. "reef" is always used for Oem ID which is treated as more of family in this case. iasl -d shows the following on reef: [00Ah 0010 6] Oem ID : "reef" [010h 0016 8] Oem Table ID : "reef" [018h 0024 4] Oem Revision : 00000008 BUG=chrome-os-partner:60494 BRANCH=reef Change-Id: I5daa6f0306bc05e812a8737ce61ee37177a36b76 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17772 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-09mainboard/google/reef: add board SKU'ing supportAaron Durbin
There are 2 gpios on reef-like boards that can be composed into a SKU. Add support for identifying the SKU value using the base 3 gpio logic. Also export the SKU information to the SMBIOS type 1 table. BUG=chrome-os-partner:59887,chrome-os-partner:60494 BRANCH=reef Change-Id: I8bb94207b0b7833d758054a817b655e248f1b239 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17771 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-08google/eve: Add ASL code to describe SPI FPC1020 controllerDuncan Laurie
There is ongoing work to link SPI bus and devices in to the devicetree so this can be generated, but for now put in the raw ASL code to describe this controller so it can be used by the factory. BUG=chrome-os-partner:55538 TEST=successfully load fpc1020 kernel module on eve board Change-Id: I6641664e60fcf2c0bad4b3506c77513b26d7be2e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17776 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08mainboard/google/reef: Set PL2 override to 15000mWSumeet Pawnikar
This patch sets PL2 override value to 15W in RAPL registers. BUG=chrome-os-partner:60535 TEST=Built, booted on reef and verified PL2 value. Change-Id: I4ff6a5e7b8686d97134846ee80cdac10916d58ef Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17730 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08google/beltino, tidus: simplify led_power_on() functionMatt DeVillier
Simplify set_power_led() by consolidating switch and setting values as needed inline based on LED state. Remove unnecesary function param, includes for Tidus. Change-Id: I28e6fac5f8d7e2ff419002db714ce88697895faf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17744 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-07google/beltino: fix LED, simplify function for Tricky variantMatt DeVillier
Simplify set_power_led() by consolidating switch and setting values as needed inline based on LED state. Fix non-off LED polarity for Tricky using correct value from Chromium source TEST: power on Tricky, observe LED lit / solid Change-Id: I8bc7c4ae3f83d3f37b76fd5c90a4faed7057ebee Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17719 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-07PCI ops: MMCONF_SUPPORT_DEFAULT is requiredKyösti Mälkki
Doing PCI config operations via MMIO window by default is a requirement, if supported by the platform. This means chipset or CPU code must enable MMCONF operations early in bootblock already, or before platform-specific romstage entry. Platforms are allowed to have NO_MMCONF_SUPPORT only in the case it is actually not implemented in the silicon. Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07mainboard/google/reef: adjust chromeos.fmd regionsAaron Durbin
- Drastically reduced RW_MRC_CACHE size to hold one update. Now that this area isn't changing after every S5 entry there's no need make it so large. - ELOG area reduced by 4KiB for subsequent area alignment. In practice this doesn't matter because the elog library only uses 4KiB bytes. 16KiB->12KiB is a nop. - Moved RW_NVRAM for subsequent alignment. - Most importantly, RW_SECTION_(A|B) are aligned to 64KiB boundaries and sized to 64KiB multiples. This ensures updates don't need a read-modify-write that could force a system into recovery if an inopportune power event occurred. BUG=chrome-os-partner:60492 BRANCH=reef Change-Id: I2a2e2797897c934db1a3f9627c6c13a9b2aad540 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17727 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-06Bob: Update the memory ramid of bobShasha Zhao
Update the memory ramid. Move to one CA training pattern. BUG=chrome-os-partner:59454 BRANCH=firmware-gru-8785.B TEST=Build firmware passed Change-Id: Ic05cbc1700a13e372f63d5202459add0e984f9d8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1030a78af3d489d13508f17a79df1e65bd5afa3b Original-Change-Id: Ibe8acb5b698cec1adcdddbb13d35a5e20a5b8c0d Original-Reviewed-on: https://chromium-review.googlesource.com/414664 Original-Commit-Ready: Shasha Zhao <Sarah_Zhao@asus.com> Original-Tested-by: Shasha Zhao <Sarah_Zhao@asus.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Change-Id: I0ae46e496cd18492a2b6c7167081798c2f2479b1 Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/411645 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17679 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06Bob: add bob in corebootShasha Zhao
Add bob in coreboot and update as necessary. 1. Add bob HWID 2. Add supported memory source BUG=chrome-os-partner:59454 BRANCH=firmware-gru-8785.B TEST=Build firmware passed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Change-Id: Iad03a293bdbbb89450f0fea0822e34a4be7064bf Original-Commit-Id: bff788c71a43403bff2c23b38e69cc27fb869559 Original-Change-Id: I0dcf47eb911337b176f73759a2c70a9dbf4dc68b Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/411083 Original-Reviewed-by: Philip Chen <philipchen@chromium.org> Original-(cherry picked from commit c5925dfcf59ac755a26182744b2bde59e41a37cf) Original-Reviewed-on: https://chromium-review.googlesource.com/413744 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17678 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06rockchip/rk3399: sdram: use register to calculate sdram sizesLin Huang
We may support different sdram sizes on one board in future, so we need to calculate sdram sizes from sdram drvier. BRANCH=None BUG=None TEST=boot kevin Change-Id: I43e8f164ecdb768c051464b4dbc7d890df8055d0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3c4d8b3cb647b2f9cebc416c298817c16d49330e Original-Change-Id: I95d5ef34de9d79ebca3600dc7a4b9e14449606ff Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/411600 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17629 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06google/gru: Power-cycle USB ports in developer/recovery modesJulius Werner
Gru only uses USB 2.0 in firmware to avoid all the madness associated with Type-C port orientation and USB 3.0 tuning. We do this by isolating the SuperSpeed lines in the Type-C PHY so it looks like they aren't connected to the device. Unfortunately, some devices seem to already get "locked" into SuperSpeed mode as soon as they detect Rx terminations once, and can never snap out again on their own. Since the terminations are already connected during power-on reset we cannot disable them fast enough to prevent this, and the only solution we found to date is to power-cycle the whole USB port. Now, Gru's USB port power is controlled by the EC, and unfortunately we have no direct host command to control it. We do however have a command to force a certain USB PD "role", and forcing our host into "sink" mode makes it stop sourcing power to the port. So for lack of a saner solution we'll use this to work around our problem. BRANCH=gru BUG=chrome-os-partner:59346 TEST=Booted Kevin in recovery mode, confirmed that my "problem stick" gets detected immediately (whereas previously I had to unplug/replug it). Booted Kevin to OS in both developer and normal mode and confirmed that USB still seems to work. Change-Id: Ib3cceba9baa170b13f01bd5c01bd413be5b441ba Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cd695eda33299e50362f1096c46f2f5260c49036 Original-Change-Id: I2db3d6d3710d18a8b8030e94eb1ac2e931f22638 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/413031 Reviewed-on: https://review.coreboot.org/17628 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06cpu/x86/msr.h: Drop excessive includesKyösti Mälkki
Change-Id: Ic22beaa47476d8c600e4081fc5ad7bc171e0f903 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17735 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06cpu/cpu.h: Drop excessive includesKyösti Mälkki
Change-Id: Ifeef04b68760522ce7f230a51f5df354e6da6607 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17734 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05mainboard & southbridge: Clear files that are just headersMartin Roth
These headers & comments indicating a lack of functionality don't help anything. We discourage copyrights and licenses on empty files, so just clear these. Change-Id: Id2ab060a2726cac6ab047d49a6e6b153f52ffe6d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17657 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-05Add/Combine Haswell Chromebooks using variant board schemeMatt DeVillier
Combine existing boards google/falco and google/peppy with new ChromeOS devices leon and wolf, using their common reference board (slippy) as a base. Chromium sources used: firmware-falco_peppy-4389.81.B d7703cac [falco: Add support for Samsung...] firmware-leon-4389.61.B ea1bf55 [haswell: Enable 2x Refresh Mode] firmware-wolf-4389.24.B 7c5a9c2 [Wolf: haswell: Add small delay before...] Additionally, some minor cleanup/changes were made: - I2C devices set to use ACPI (vs PCI) mode - I2C device ACPI entries adjusted as per above - I2C devices set to use level (vs edge) interrupt triggering - XHCI finalization enabled in devicetree - HDA verb entries use simplified macro entry format Existing google/falco and google/peppy boards will be removed in a subsequent commit. Variant setup modeled after google/beltino Change-Id: I087df5f98c1bb4ddd0ab24ee9ff786a9d38d87be Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17621 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-05Remove boards google/falco and google/peppyMatt DeVillier
No need for these boards to exist separately once included as variants under google/slippy Change-Id: I52a476ceaadf50487d6fe21e796d7844f946d8b3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17622 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-02google/pyro: set i2c bus timings by rise/fall timesKevin Chiu
Provide the rise and fall times for the i2c buses and let the library perform the necessary calculations for the i2c controller registers instead of manually tuning the values. BUG=chrome-os-partner:58112 BRANCH=master TEST=emerge-pyro coreboot Change-Id: I68be9b96dc731eb0084ee5e15921866818637e73 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17652 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-02mainboard/google/reef: Add all DMIC endpointsSathyanarayana Nujella
Independent of Board DMIC configuration, add all DMIC points i.e. add DMIC-1ch, DMIC-2ch, DMIC-4ch endpoints. This allows flexibility to userspace to open capture devices as needed. This is a temporary fix; once upper layers support choosing particular channels from 4-ch PCM stream, we will limit exposing only DMIC-4ch endpoint. BUG=chrome-os-partner:60444 BRANCH=none TEST=Verify All DMIC blobs are included Change-Id: I9729a3570c0668f3da4e7986291ebad6fe1de47a Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/17660 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01mainboard/google/reef: allow variants to modify nhlt oem revisionAaron Durbin
In order to mirror the full flexibility of the NHLT library that allows a caller to set the OEM revision field in the ACPI header modify the variant callback to override the value. Change-Id: I16e539b350a50e3c163be1439c8637b82e53a759 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17651 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-12-01lib/nhlt: add support for setting the oem_revisionAaron Durbin
In the ACPI header there's an OEM revision field that was previously just being implicitly set to 0. Allow for a board to provide a non-zero value for this field. Change-Id: Icd40c1c162c2645b3990a6f3361c592706251f82 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17650 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01lib: put romstage_handoff implementation in own compilation unitAaron Durbin
Instead of putting all the functions inline just put the current implementation into a C file. That way all the implementation innards are not exposed. Lastly, fix up the fallout of compilation units not including the headers they actually use. Change-Id: I01fd25d158c0d5016405b73a4d4df3721c281b04 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17648 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-30mainboard/google/snappy: Tune i2c frequency to 400 KhzWisley Chen
tune i2c devices clk for snappy: I2C0: audio I2C2: TPM H1 I2C3: elan touchscreen I2C4: elan touchpad I2C5: wacom digitizer BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage, and measured on EVT. audio: Freq. 393.7kHz Rise Time 58.8ns Fall time 12.11ns TPM H1: Freq. 398.8kHz Rise Time 31.71ns Fall time 13.28ns elan touchscreen: Freq. 390.5kHz Rise Time 235.7ns Fall time 37.64ns elan touchpad: Freq. 393.7kHz Rise Time 288.8ns Fall time 51.67ns wacom digitizer: Freq. 388.8kHz Rise Time 124.1ns Fall time 21.10ns Change-Id: Ib2be9e1575d4962476423eafa80f9bb10ba40e17 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17634 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-30mainboard/reef: Add RW_VAR_MRC_CACHEAndrey Petrov
Chop off 4kb block from RW_MRC_CACHE to store variable MRC cache. BUG=chrome-os-partner:57515 TEST=with patch series applied: cold reboot, make sure MRC is not updated. Do S3 suspend/resume cycle. Change-Id: I3e19fff9c9b20d6c73cbb13bfeec49e9a274bb72 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17235 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30mb/google/oak: replace symbolic linksMartin Roth
These three files were added as symbolic links to the other files in the same directory. Delete the links, and copy the real files into their places. Because of the varied environments that coreboot is built in, we don't want to have symbolic links in the tree. These three files were the only cases of symbolic links. Change-Id: If69f40c2c4cdcabc4fdfc1d6026a91c0791756da Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17632 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-29google/gru: Tune USB 2.0 PHY to increase compatibilityWilliam wu
When testing USB 2.0 compatibility with different kinds of USB 2.0 devices on Kevin board, we find that some USB HDDs (e.g. seagate SRD00F1 1TB HDD) and some smart phones (e.g. galaxy A5 smart phone) can't be detected. And according to the error log, this issue is related to USB 2.0 PHY signal problem. For the USB HDD, error log is: [ 592.557724] usb 5-1: new high-speed USB device number 2 using xhci-hcd [ 592.847735] usb 5-1: new high-speed USB device number 3 using xhci-hcd [ 593.473720] usb 5-1: new high-speed USB device number 6 using xhci-hcd [ 594.187717] usb 5-1: new high-speed USB device number 9 using xhci-hcd [ 595.020717] usb 5-1: new high-speed USB device number 13 using xhci-hcd [ 595.284730] usb 5-1: new high-speed USB device number 14 using xhci-hcd [ 595.574816] usb 5-1: new high-speed USB device number 15 using xhci-hcd The log shows that HDD failed to high-speed handshake. For the smart phone, error log is: [ 1145.661625] usb 5-1: new high-speed USB device number 2 using xhci-hcd [ 1145.771674] usb 5-1: device descriptor read/64, error -71 [ 1145.979752] usb 5-1: device descriptor read/64, error -71 [ 1146.187721] usb 5-1: new high-speed USB device number 3 using xhci-hcd [ 1146.301754] usb 5-1: device descriptor read/64, error -71 [ 1146.509750] usb 5-1: device descriptor read/64, error -71 [ 1146.717722] usb 5-1: new high-speed USB device number 4 using xhci-hcd [ 1146.724393] usb 5-1: Device not responding to setup address. [ 1146.930795] usb 5-1: Device not responding to setup address. [ 1147.137720] usb 5-1: device not accepting address 4, error -71 [ 1147.246644] usb 5-1: new high-speed USB device number 5 using xhci-hcd [ 1147.253336] usb 5-1: Device not responding to setup address. [ 1147.459786] usb 5-1: Device not responding to setup address. [ 1147.665712] usb 5-1: device not accepting address 5, error -71 [ 1147.671789] usb usb5-port1: unable to enumerate USB device The log shows that smart phone failed to read device descriptor, error -71 may be caused by PHY signal problem. This patch aims to tune USB 2.0 PHY with the following parameters to support USB HDD, smart phone and some other potential USB 2.0 devices. 1. Disable the pre-emphasize in chirp state to avoid high-speed handshake failure. 2. Bypass ODT auto compensation to enable set max driver strength manually. (Bit[42] of usbphy_ctrl register is 1'b1 for bypass, and Bit[41:37] of usbphy_ctrl register is 5'b10000 for max driver strength). 3. Bypass ODT auto refresh, and set the max bias current tuning reference. (Bit[57] of usbphy_ctrl register is 1'b1 for bypass, and Bit[52:50] of usbphy_ctrl register is 3b'100 for max bias current tuning reference). We have done the USB 2.0 compliance test and compatibility test with this patch, it works well. BRANCH=gru BUG=chrome-os-partner:59623 TEST=plug/unplug USB HDD or smart phone in Type-C port, check if they can be detected successfully. Change-Id: I275c2236b8e469bfd04e9184d007eb095657225e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7735c514d4136978133c2299f2f58da8320bb89f Original-Change-Id: I4e6c10faa1c03af9880a89afe4731a7065eb1e4e Original-Signed-off-by: William wu <wulf@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/409856 Original-Commit-Ready: Eddie Cai <eddie.cai.rk@gmail.com> Original-Tested-by: Cindy Han <cindy.han@samsung.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17566 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-29google/pyro: disable unused devicesKevin Chiu
The following devices i2c5, i2c6, i2c7, spi1, spi2, uart3 are not used. BUG=none BRANCH=master TEST=emerge-pyro coreboot Change-Id: I3b7b96e72b82af1885926800ee99beff07755bbc Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17589 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-29mainboard/google/snappy: Add digitizer device to devicetreeWisley Chen
BUG=chrome-os-partner:59034 BRANCH=none TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: Ib99ae5357274ad0824d0989888dfddcb32ace7e2 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17618 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-29mainboard/google/reef: Set DPTF CPU passive temperature trip point to 95CSumeet Pawnikar
This pach sets the DPTF passive temperature trip point for CPU back to 95 degree celsius from 61 degree celsius as per previous thermal optimizations (https://review.coreboot.org/#/c/16766/). BUG=chrome-os-partner:60038 BRANCH=master TEST=built, booted on Reef and verified the passive trip point funtionality. Change-Id: I83ce69b19a94e4ea8ebedfc06f259579ed6dd5d3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17598 Tested-by: build bot (Jenkins) Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-29google/oak: Add DRAM configuration for Samsung K4E8E324EBPH Hsu
Add the configuration for Samsung K4E8E324EB and assign it to RAM_CODE 5. BUG=chrome-os-partner:58983 TEST=verified on Hana EVT. Change-Id: Iea55eb393b21e37f36d454706531f588101ee651 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 38d34ed0a0b420e1ab300a47b99035153be5b5d0 Original-Change-Id: I28724c1cf5cf12f47911a571c20280ddab4500d5 Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/410926 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17567 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-28soc/intel/skylake: Add USB Port Over Current (OC) Pin programmingSubrata Banik
Program USB Overcurrent pins as per board schematics definition. BUG=none BRANCH=none TEST=Build and boot kunimitsu from USB device. Change-Id: I6aeb65953c753e09ad639469de7d866a54f42f11 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-28mainboard/google/reef: Set PL1 MAX power limit value to 12WTim Chen
Set PL1 maximum power limit value back to 12W (https://review.coreboot.org/#/c/16596/) from 6W due to Intel's and thermal team's suggestion. BUG=chrome-os-partner:60038 BRANCH=master TEST=build, boot on electro dut and verify by thermal team member Change-Id: I57ae29180962724fde72d522caa542f0f21d5922 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17574 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-25google/parrot: Fix keyboard interrupts, DSDTPrabal Saha
Commit 967cd9a [ChromeOS: fix Kconfig dependencies] broke keyboard interrupts on parrot by making SERIRQ_CONTINUOUS_MODE conditional on CONFIG_CHROMEOS, which it should not be; fix by moving back under main board specific options config. Additionally, Windows [8/8.1/10] fails to enumerate the keyboard when its ACPI entry is located under the SIO device since it is missing an _HID entry, so add the appropriate value per ACPI spec 5 ch. 9.7 Change-Id: Ia69e9b326001d2026b15b4ec03c94f7d03c8a700 Signed-off-by: Prabal Saha <coolstarorganization@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17017 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-24Add Haswell Chromeboxes/Chromebase using variant board schemeMatt DeVillier
Combine existing board google/panther with new ChromeOS devices mccloud, monroe, tricky, and zako, using their common reference board (beltino) as a base. Chromium sources used: firmware-mccloud-5827.B 65bfee7 [haswell: No need pre-graphics delay...] firmware-monroe-4921.B 1ac749d [Monroe: Disable KB/MS in ITE8772.] firmware-tricky-5829.B 2db5322 [haswell: No need pre-graphics delay...] firmware-zako-5219.B eacedef [haswell: No need pre-graphics delay...] Existing google/panther board will be removed in a subsequent commit. Variant setup modeled after google/reef Change-Id: I5d7e0c2551e8b0707841032460c35615cefb2886 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17329 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-24Remove board google/pantherMatt DeVillier
Once #17329 is committed, no reason to have google/panther exist as a separate board anymore. Change-Id: I9a11273c39423d5ff33a7d1f91c8d8cffef97ec1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17538 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-11-23google/pyro: Update DPTF settingsKevin Chiu
1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points. CPU passive point:57, critical point:90 TSR1 passive point:55, critial point:70 TSR2 passive point:65, critial point:80 2. Update DPTF TRT Sample Period. CPU: 5s TSR0: 50s TSR1: 55s TSR2: 120s BUG=none BRANCH=master TEST=emerge-pyro coreboot Change-Id: Ib1b4b31a49d9396b1c5c9dd8d0b9b9998d01744f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17552 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-23veyron_*: Remove obsolete ChromeboxesDavid Hendricks
This removes brain, danger, emile, and romy from the tree. This was cherry-picked from the chromeos-2016.02 branch (CL:345574), but conflicts showed up in many files that were to be deleted anyway possibly due to some widespread refactoring that was done between then and now. BUG=chromium:612660 BRANCH=none TEST=none Change-Id: Ie37140a9a4bb9d820a3fcbad6674b2fa737e1249 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1ebe5038a82162f6345e319de7578f26ccd68b73 Original-Change-Id: I11f7e0870916871d8f146a6871370ace76ddec49 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/412424 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17569 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-11-22Remove explicit select MMCONF_SUPPORTKyösti Mälkki
Make MMCONF_SUPPORT selected with MMCONF_SUPPORT_DEFAULT. Platforms that remain to have explicit MMCONF_SUPPORT are ones that should be converted. Change-Id: Iba8824f46842607fb1508aa7d057f8cbf1cd6397 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17527 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-20intel sandy/ivy: Improve DIMM replacement detectionKyösti Mälkki
When MRC cache is available, first read only the SPD unique identifier bytes required to detect possible DIMM replacement. As this is 11 vs 256 bytes with slow SMBus operations, we save about 70ms for every installed DIMM on normal boot path. In the DIMM replacement case this adds some 10ms per installed DIMM as some SPD gets read twice, but we are on slow RAM training boot path anyways. Change-Id: I294a56e7b7562c3dea322c644b21a15abb033870 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17491 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-11-20mainboard/google/reef: Update DPTF parameters provided from thermal teamTim Chen
Update the DPTF parameters based on thermal test result. 1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points. CPU passive point:61 TSR0 passive point:120, critial point:125 TSR1 passive point:46, critial point:75 TSR2 passive point:100, critial point:125 2. Update PL1/PL2 Min Power Limit/Max Power Limit Set PL1 min to 3W, and max to 6W Set PL2 min to 8W 3. Change thermal relationship table (TRT) setting. Change CPU Throttle Effect on CPU sample rate to 80secs Change CPU Effect on Temp Sensor 0 sample rate to 120secs The TRT of TCHG is TSR1, but real sensor is TSR2. Change Charger Effect on Temp Sensor 2 sample rate to 120secs Change CPU Effect on Temp Sensor 2 sample rate to 120secs BUG=chrome-os-partner:60038 BRANCH=master TEST=build and boot on electro dut Change-Id: I7a701812cb45f51828a3cbb3343e03817645110e Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17466 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-18google/chromeec: Add common infrastructure for boot-mode switchesFurquan Shaikh
Instead of defining the same functions for reading/clearing boot-mode switches from EC in every mainboard, add a common infrastructure to enable common functions for handling boot-mode switches if GOOGLE_CHROMEEC is being used. Only boards that were not moved to this new infrastructure are those that do not use GOOGLE_CHROMEEC or which rely on some mainboard specific mechanism for reading boot-mode switches. BUG=None BRANCH=None TEST=abuild compiles all boards successfully with and without ChromeOS option. Change-Id: I267aadea9e616464563df04b51a668b877f0d578 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17449 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-11-17google/snappy: Update DPTF settingsWisley Chen
1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points. CPU passive point:100, critical point:105 TSR1 passive point:48, critial point:65 TSR2 passive point:85, critial point:100 2. Update PL1/PL2 Min Power Limit/Max Power Limit Set PL1 min to 3W, and max to 6W Set PL2 min and max to 8W 3. Change thermal relationship table (TRT) setting. The TRT of TCHG is TSR1, but real sensor is TSR2. BRANCH=master BUG=none TEST= Compiled, verified by thermal team. Change-Id: Ib197c36eca88e3d05f632025cf3c238e1a2eae23 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17426 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-17mainboard/google/reef: disable unused devicesJagadish Krishnamoorthy
The following devices i2c6, i2c7, spi1, spi2, uart3 are not used. BUG=chrome-os-partner:59880 TEST=Boot to OS and lspci command should not list the above disabled devices. Change-Id: I819cdb34709703e6431b49446417ed9d6b3543cd Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/17441 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-17mainboard/google/reef: set i2c bus timings by rise/fall timesAaron Durbin
Provide the rise and fall times for the i2c buses and let the library perform the necessary calculations for the i2c controller registers instead of manually tuning the values. BUG=chrome-os-partner:58889,chrome-os-partner:59565 Change-Id: I0c84658471d90309cdbb850e3128ae01780633af Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17397 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-11-17google/gru: Move to one CA training patternDerek Basehore
This changes memory to only do CA training with one pattern, 0xfffff/0x00000 and to also make sure CA training waits for all of the captures during training. BRANCH=none BUG=chrome-os-partner:56940 TEST=boot kevin and run stressapptest -M 1500 -s 1000 Change-Id: I0982674b4f4415f4d7865923ced93fa09bdd877e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 75cdd911cea9c4e5744fd04505b260fa5755513c Original-Change-Id: I3b86e6d4662c6fbbf9ddef274fce191a367904e5 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/410320 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/17383 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-17google/gru: Add new CA training patternDerek Basehore
This adds a new CA training pattern for all of the supported frequencies. This pattern increases the hold time on CA. BRANCH=none BUG=chrome-os-partner:57845 TEST=boot kevin and run: while true; do sleep 0.1; memtester 500K 1 > /dev/null; done for several hours Change-Id: Ie5958cf67c16247ef90ee261da9faef4ffa5b339 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8babeafe75bffcb2dab17eb007b4f5bb0eb42606 Original-Change-Id: I7f7652f88e43dc9b2f6069e60514931bf7582ed1 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/403547 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/17382 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-17google/oak: Add more DRAM modules supportPH Hsu
Add support for following 3 modules. - Micro MT52L256M32D1PF / MT52L512M32D2PF - Hynix H9CCNNNBJTALAR Hana EVT was planed to add 4 DRAM modules but RAM_CODE=5 is not used in the end. This patch also unifies the naming of the RAM configurations. BUG=chrome-os-partner:58983 TEST=verified on Hana EVT. Change-Id: I7dd44525de8e9dde01f210f4730fa8ccd4baef21 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5dccd68149bcfd6fd0a83e310d43063bab645691 Original-Change-Id: I7c245c8c24be159e152f4f3cca25bf970b58425c Original-Signed-off-by: Milton Chiang <milton.chiang@mediatek.com> Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com> Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/402888 Original-Reviewed-by: Pin-Huan Hsu <ph.hsu@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Paris Yeh <pyeh@chromium.org> Reviewed-on: https://review.coreboot.org/17381 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-16mainboard/google/reef: Add proper DMIC endpoints based on DMIC config pinSathyanarayana Nujella
Reef board uses GPIO_17 as DMIC config pin. This pin distinguishes board with Quad DMIC's or Mono DMIC. This patch adds necessary DMIC endpoints to support either of those configurations. CQ-DEPEND=CL:*304339,CL:409774 BUG=chrome-os-partner:56918 BRANCH=none TEST=Verify Mono and Quad Channel DMIC record Change-Id: I5b2825b5f39f8962985a129f8ec65265fb18f0b2 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/17158 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-16google/eve: Fill out memory ID tableDuncan Laurie
Add the DIMM SPD data for memory types that are not used yet but are on the matrix and may be used in future builds. Also fix a typo in the part number string for one type. BUG=chrome-os-partner:58666 TEST=build and boot on eve p0 Change-Id: I20401d7afb69f1c3ae1a3b0d6e3ec9097f54ef96 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17437 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-15google/link/i915.c: Fix build error when native gfx init enabledIru Cai
- Move members of struct edid to struct edid_mode - Change `u32 pmmio` to `u8 *pmmio` in i915_lightup_sandy Change-Id: Id64daf5eae1d4d8265105067b2e6ae55786a5638 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/17332 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-14google/chell : update DPTF policy settingsSumeet Pawnikar
Fine tuned DPTF policy values for chell device as below, 1. Increase Passive temperature value to 52 degree Celsius for TSR2. 2. Remove charger effect for TSR2. 3. Increase Minimum PowerLimit1 to 3W. 4. Reduce Maximum PowerLimit1 to 6W. BUG=chrome-os-partner:54718 BRANCH=None. TEST=Built for chell device. Change-Id: I46f69e3cd527ea3d28bdd7daa29d91f76770c277 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17376 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-11mainboard/google/snappy: Configure PERST pinWisley Chen
Configure GPIO 122 as PERST. This is to assert WiFi PERST during s0ix entry. BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: If2528632fe65c3ed1af19b2ce6f99e8be0cd1ad9 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17356 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11google/snappy: update timing of sdmode togglingWisley Chen
Maxim98357a speaker amp requires BCLK & SFRM to be active and stable before it is unmuted. If there is a BLCK and no SFRM, it results in a pop sound. sdmode_delay property already exists which facilitates this configuration. This patch updates "sdmode_delay" to avoid pop sound. BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: Ic9095ae6812ba822c760229e69f5b27c6c244cdf Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17361 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11mainboard/google/snappy: Set PL1 override to 12000mWWisley Chen
Snappy is using APL SoC SKU's with 6W TDP max. As Reef, the energy calculation is wrong with the current VR solution. Experiments show that SoC TDP max (6W) can be reached when RAPL PL1 is set to 12W. Therefore, we've inserted 12W override after reading the fused value (6W) so that the system can reach the right performance level. BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: Idd702077cd05e2b43823542cb804b2d4b42f7116 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17362 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11soc/intel/skylake: move i2c voltage config to own variableAaron Durbin
In preparation of merging the lpss i2c config structures on apollolake and skylake move the i2c voltage variable to its own field. It makes refactoring things easier, and then there's no reason for a separate SoC specific i2c config structure. BUG=chrome-os-partner:58889 Change-Id: Ibcc3cba9bac3b5779351b673bc0cc7671d127f24 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17347 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-10mainboard/google/reef: Add digitizer device to devicetreeFurquan Shaikh
BUG=chrome-os-partner:56246 BRANCH=None TEST=Verified kernel is able to talk to the device. Even without the digitizer, no issues observed with the kernel. Change-Id: I894a5f4cd8f6a51e641a2c8f7b1f682ab76712ae Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17343 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-10mainboard/google/reef: Tune digitizer I2C frequency to 400kHzFurquan Shaikh
This brings the I2C frequency down to 400kHz which is spec for fast I2C. BUG=chrome-os-partner:56246 BRANCH=None TEST=Verified frequency in kernel. Change-Id: Ib83c57eec8644903cb9c4b2ab50c94038eb690c1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17342 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10drivers/i2c/wacom: Make the driver more genericFurquan Shaikh
Wacom I2C driver can be used by devices other than touchscreen. e.g. digitizer. So there is no need to name the driver with touchscreen specific attributes. Only a separate descriptor name is required that needs to be set by mainboard correctly. BUG=chrome-os-partner:56246 BRANCH=None TEST=Compiles successfully. Change-Id: I0d32a4adae477373b3f4c5f3abbe188860701194 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17341 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10mainboard/google/pyro: Set PL1 override to 12000mWKevin Chiu
Pyro is using APL SoC SKU's with 6W TDP max. As Reef, the energy calculation is wrong with the current VR solution. Experiments show that SoC TDP max (6W) can be reached when RAPL PL1 is set to 12W. Therefore, we've inserted 12W override after reading the fused value (6W) so that the system can reach the right performance level. BUG=chrome-os-partner:58112 BRANCH=master TEST=emerge-pyro coreboot chromeos-bootimage Change-Id: I6de22d7b2d107f3d26ecfadd4e0904e68318e656 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17335 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10google/pyro: Tune i2c frequency to 400 KhzKevin Chiu
tune i2c devices clk for pyro: I2C0: audio da7219 I2C2: TPM H1 I2C3: wacom touchscreen I2C4: elan touchpad BUG=chrome-os-partner:58881 BRANCH=master TEST=emerge-pyro coreboot chromeos-bootimage Change-Id: If3c92ed260277c27a94d2fcf7883e9441519e40e Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17331 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10google/pyro: update timing of sdmode togglingKevin Chiu
Maxim98357a speaker amp requires BCLK & SFRM to be active and stable before it is unmuted. If there is a BLCK and no SFRM, it results in a pop sound. sdmode_delay property already exists which facilitates this configuration. This patch updates "sdmode_delay" to avoid pop sound. BUG=chrome-os-partner:58112 BRANCH=master TEST=emerge-pyro coreboot chromeos-bootimage Change-Id: I5aee41957c9de7a05f962d3ede74efc6998a78fc Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17336 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10mainboard/google/pyro: Configure PERST pinKevin Chiu
Configure GPIO 122 as PERST. This is to assert WiFi PERST during s0ix entry. BUG=chrome-os-partner:58112 BRANCH=master TEST=emerge-pyro coreboot chromeos-bootimage Change-Id: Id760251a1b037feb62ec43199a145e407b074769 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17334 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10mainboard/google/reef: Add support for RECOVERY_MRC_CACHEFurquan Shaikh
1. Add RECOVERY_MRC_CACHE region to reef FMAP. 2. Implement helper function for getting event for recovery mode with memory retraining. 3. Select HAS_RECOVERY_MRC_CACHE. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified recovery mode behavior with and without memory training request on reef. Change-Id: I91abc9f8122f1aa3980c6372ab557e56a7a92730 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17243 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09mainboard/google/reef: use common google smbios mainboard versionAaron Durbin
BUG=chromium:663243 Change-Id: Ic78a6aac11a8e842911245c59e8ced7ed2c4e27a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17291 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-09google/pyro: Update WACOM touchscreen ACPI _HIDJanice Li
WACOM request to add a new identifier `WCOMNTN2`, and use that for the board Pyro with all LCD combinations. BRANCH=master BUG=chrome-os-partner:58093 TEST=emerge-pyro vboot_reference coreboot chromeos-bootimage Signed-off-by: Janice Li <janice.li@quantatw.com> Change-Id: I95cf357efba958d7e864d2736d324e0aad70e307 Reviewed-on: https://review.coreboot.org/17257 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-07google/lars: Update DPTF settingsSumeet Pawnikar
After tuning the temperature values for optimal performance, this patch updates few DPTF settings for lars boards. BUG=chrome-os-partner:51025 BRANCH=firmware-glados-7820.B TEST=Built and booted on lars DVT boards. Verified these updated DPTF settings with different workloads. Change-Id: I4c040526c31c3263ed3a9b4cccff3b7a021cfcdb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://chromium-review.googlesource.com/338877 Reviewed-on: https://review.coreboot.org/17068 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-07mainboard/google/reef: update DMIC related pins configurationSathyanarayana Nujella
CLK_B1(GPIO_80) and DATA_2(GPIO_83) pins needs to be configured as native mode to use them for DMIC record on other potential DMIC's. DMIC blobs configure the clocks. For stereo & quad channel record, both CLK_A1 and CLK_B1 are enabled. For mono channel record, only CLK_A1 is enabled. BUG=chrome-os-partner:56918 BRANCH=None TEST=During DMIC record, check CLK_B1 and DATA_2 lines Change-Id: I838009b85190de5360d593238e48c9593c1dc43a Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/17199 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-04reef: tune trackpad i2c frequency to 400kHzAaron Durbin
This brings the frequency down to 400kHz which is spec for fast i2c. BUG=chrome-os-partner:58889 Change-Id: Ibc5f152e55ed618f18ac6425264f086b1f2d1ffa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17215 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-04reef: tune tpm i2c frequency to 400kHzAaron Durbin
This brings the frequency down to 400kHz which is spec for fast i2c. BUG=chrome-os-partner:58889 Change-Id: I8689a062b5457aa431eaa7fb688a7170dad83fcf Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17214 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-03google/veyron*: change .ddrconfig from 14 to 3ZhengShunQian
There are two configs, sdram-lpddr3-hynix-2GB.inc and sdram-lpddr3-samsung-2GB-24EB.inc that use .ddrconfig = 14. Changing .ddrconfig from 14 to 3 improves performance especially on contiguous memory accesses. Comparing the .ddrconfig: - if .ddrconfig = 3, C RDRR RRRR RRRR RRRR RBBB CCCC CCCC C--- - if .ddrconfig = 14, C DRBB BRRR RRRR RRRR RRRR CCCC CCCC C--- where - R: indicates Row bits - B: indicates Bank bits - C: indicates Column bits - D: indicates Chip selects bits .ddrconfig = 3 has multiple banks switching which improves DDR timing. BUG=chrome-os-partner:57321 TEST=Boot from fievel and play video BRANCH=veyron Change-Id: Ifdcedc28e84429b8b79c7553b38b667631d29c09 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 93882e4f2000d93c9dae5e6d4b2e1f4b7bc9489e Original-Change-Id: Ic98ebae48609a7604ec678b6bd14dd2b29b669c4 Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/404691 Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17210 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-03google/veyron*: add DDR configs for new samsung DDRZhengShunQian
Add the new samsung DDR configs for all veyron except veyron_rialto: * K4E6E304EB-EGCE, ramid = 0010, 4GB * K4E8E324EB-EGCF, ramid = 1100, 2GB BRANCH=veyron BUG=none TEST=boot fievel board Change-Id: I747aa86f8c93174651a28face63b3386e22b23b3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5f55462e71bd481eda85af3d582cfe5b9873cc9c Original-Change-Id: I19123634c994f685683323f7d85cc4d35814e2ab Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/345748 Original-Commit-Queue: Ren Kuo <ren.kuo@quantatw.com> Original-Reviewed-by: Philip Chen <philipchen@chromium.org> Original-(cherry-pick from cc990f27024255a326fd9fa9644deb28b01a31a7) Original-Reviewed-on: https://chromium-review.googlesource.com/404690 Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17209 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02rockchip/rk3399: display: Do not allocate framebuffer in corebootLin Huang
framebuffer address is dynamically chosen by libpayload now, so there's no need to configure it in coreboot. CQ-DEPEND=CL:401402 BUG=chrome-os-partner:58675 BRANCH=none TEST=Boot from kevin, dev screen is visible Change-Id: I9f1e581d5c63b3579b26be22ce5c8d1e71679f6f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b3b6675420592c30e1e0abc8f8e9dd6ed5abd04c Original-Change-Id: I7e3162f24a4dc426fe4e10d74865cf0042c80db5 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/401401 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17109 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02rockchip/rk3399: sdram: also prepare the index1 configurationLin Huang
To enable DDR Dynamic Voltage and Frequency Scaling (DVFS) we need to train alternative configurations first, so do the training and store the values. BUG=None BRANCH=None TEST=Boot from kevin Change-Id: I944a4b297a4ed6966893aa09553da88171307a42 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 94533ff3ba21bcb0ace00bedcf0cebb89a341be2 Original-Change-Id: I4a98bc0db5553d154fedb657e35b926a92aa80c7 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/386596 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17104 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-01google/eve: Add new boardDuncan Laurie
Add the eve board files using kabylake and FSP 2.0. BUG=chrome-os-partner:58666 TEST=build and boot on eve board Change-Id: I7ca71fe052608d710ee65d078df7af7b55d382bc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17177 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-10-28lars/kunimitsu: Add other sensor in _ART for fan controlSumeet Pawnikar
This patch updates the _ART table with other external sensor TSR0 for Fan speed control on Skylake-U based Kunimitsu and Lars boards. Also, updates the temperature values in DPTF policy for better performance. BUG=chrome-os-partner:51025 BRANCH=firmware-glados-7820.B TEST=Built and booted on kunimitsu and lars EVT boards. Verified this updated _ART table on these boards with different workloads. Change-Id: Ib195910c5eb00e004e8b9bd50e266ade3c175be2 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://chromium-review.googlesource.com/332349 Reviewed-on: https://review.coreboot.org/17066 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-28mainboard/google/reef: allow variants to override NHLT OEM stringsAaron Durbin
In certain cases a board variant may need to override the NHLT OEM strings in the main NHLT table. Therefore, provide that path. BUG=chrome-os-partner:56918 Change-Id: I57cc4fd3665698e41ceebb1949180f86bb60b61f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17167 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2016-10-28mainboard/google/reef: update comment for DMIC config usageAaron Durbin
Going forward GPIO_17 is used to determine the configuration of the board w.r.t. the number of DMICs on the board. BUG=chrome-os-partner:56918 Change-Id: I03edb880e0649977030c1b87219ebebac631a519 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17163 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 06:07:37 +0000