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2013-03-26Revert "samsung/exynos5: add resource functions for the display port"David Hendricks
This reverts commit 9427ca151e44644238b1b52138894195a9f5175f Looks like we were a bit too anxious to see this one get in. The devicetree.cb change seems to have broken things. coreboot memory table: 0. 0000000050000000-000000005000ffff: RESERVED 1. 00000000bff00000-00000000bfffffff: CONFIGURATION TABLES 2. 0000014004000000-00000140044007ff: RESERVED Before this patch: coreboot memory table: 0. 0000000040000000-00000000bfefffff: RAM 1. 00000000bff00000-00000000bfffffff: CONFIGURATION TABLES Change-Id: I618e4f1976265d56cfd6a61d0c5736c55a0f3cec Reviewed-on: http://review.coreboot.org/2914 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-26samsung/exynos5: add resource functions for the display portRonald G. Minnich
This does NOT turn on the graphics. The device tree has been changed enough so that, at the very least, the correct functions are called at the correct time, with the correct paramaters. We decided to yank the I2C entries as they did not obvious function and might not even have been correct. Not working, seemingly, but we need to add a 4M resource for memory, and it seems it needs to be fixed at the address shown. This address was chosen from current hardware. We realized that the display code should be part of the cpu -- that's how the hardware works! Change-Id: Ied65a554f833566be817540702f79a02e7b6cb6e Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2615 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-26armv7: add new dcache and MMU setup functionsDavid Hendricks
This adds new MMU setup code. Most notably, this version uses cbmem_add() to determine the translation table base address, which in turn is necessary to ensure payloads which wipe memory can tell which regions to wipe out. TODOs: - Finish cleaning up references to old cache/MMU stuff - Add L2 setup (from exynos_cache.c) - Set up ranges dynamically rather than in ramstage's main(). Change-Id: Iba5295a801e8058a3694e4ec5b94bbe9a69d3ee6 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2877 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22Unify coreboot table generationStefan Reinauer
coreboot tables are, unlike general system tables, a platform independent concept. Hence, use the same code for coreboot table generation on all platforms. lib/coreboot_tables.c is based on the x86 version of the file, because some important fixes were missed on the ARMv7 version lately. Change-Id: Icc38baf609f10536a320d21ac64408bef44bb77d Signed-off-by: Stefan Reinauer <reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/2863 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21Butterfly, Stout: Force SATA link speed to 3 GbpsShawn Nematbakhsh
Force link speed on these platforms to 3 Gbps to defeat buggy SATA drives. Change-Id: Ia38a7c486fb1f4469cd67ca5244bbf61f877d556 Signed-off-by: Shawn Nematbakhsh <shawnn@google.com> Reviewed-on: http://review.coreboot.org/2823 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-20link/graphics: Add support for EDIDRonald G. Minnich
This code is taken from an EDID reader written at Red Hat. The key function is int decode_edid(unsigned char *edid, int size, struct edid *out) Which takes a pointer to an EDID blob, and a size, and decodes it into a machine-independent format in out, which may be used for driving chipsets. The EDID blob might come for IO, or a compiled-in EDID BLOB, or CBFS. Also included are the changes needed to use the EDID code on Link. Change-Id: I66b275b8ed28fd77cfa5978bdec1eeef9e9425f1 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2837 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-20link/graphics: New state machineRonald G. Minnich
This is a new state machine. It is more programmatic, in the case of auxio, and has much more symbolic naming, and very few "magic" numbers, except in the case of undocumented settings. As before, the 'pre-computed' IO ops are encoded in the iodefs table. A function, run, is passed and index into the table and runs the ops. A new operator, I, has been added. When the I operator is hit, run() returns the index of the next operator in the table. The i915lightup function runs the table. All the AUX channel ops have been removed from the table, however, and are now called as functions, using the previously committed auxio function. The iodefs table has been grouped into blocks of ops, which end in an I operator. As the lightup function progresses through startup, and the run() returns, the lightup function performs aux channel operations. This code is symbolic enough, I hope, that it will make haswell graphics bringup simpler. i915io.c, and the core of the code in i915lightup.c, were programatically generated, starting with IO logs from the DRM startup code in the kernel. It is possible to apply the tools that do this generation to newer IO logs from the kernel. Change-Id: I8a8e121dc0d9674f0c6a866343b28e179a1e3d8a Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-20link/graphics: implement a palette setting operatorRonald G. Minnich
Add a new operator, P, for the state machine, meaning implement a palette fill. Implement a function (palette) that fills the palette when the P operator is hit. This replaces 256 lines in the state machine table with 1. Change-Id: I67d9219fe7de0ecf1fb9faf92130c00c9f5f8e88 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: http://review.coreboot.org/2835 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-19link/graphics: add functions to support aux channel communicationsRonald G. Minnich
For full integration of FUI into coreboot, we need aux channel communcations. The intel_dp.c is a file taken from Linux and is used for aux channel comms. This file has been cut down to work with coreboot. For now it is associated with the link mainboard until we get a better handle on how this all fits together. This code is almost certainly usable on other platforms in the long term. But one step at a time. Change-Id: I7be4c56e0a7903f3901ac86e12b28f3bdc0f7947 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: http://review.coreboot.org/2834 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-19armv7/exynos/snow: new cache maintenance APIDavid Hendricks
This adds a new API for cache maintenance operations. The idea is to be more explicit about operations that are going on so it's easier to manage branch predictor, cache, and TLB cleans and invalidations. Also, this adds some operations that were missing but required early on, such as branch predictor invalidation. Instruction and sync barriers were wrong earlier as well since the imported API assumed we compield with -march=armv5 (which we don't) and was missing wrappers for the native ARMv7 ISB/DSB/DMB instructions. For now, this is a start and it gives us something we can easily use in libpayload for doing things like cleaning and invalidating dcache when doing DMA transfers. TODO: - Set cache policy explicitly before re-enabling. Right now it's left at default. - Finish deprecating old cache maintenance API. - We do an extra icache/dcache flush when going from bootblock to romstage. Change-Id: I7390981190e3213f4e1431f8e56746545c5cc7c9 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2729 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-19google/snow: fix a GPIO array indexDavid Hendricks
This fixes a trivial error with the recovery mode GPIO index. Change-Id: I7290c1e23cdddaf91c9021d4e4252c0c772b6eab Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2825 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-19Include byteorder.h for the definition of ntohl in romstage.cHung-Te Lin
A fix to eliminate warnings when building romstage files with ChromeOS compilers Change-Id: Ia5d7bbdde3aa3439fd493f5795f2cc2bf4c4c187 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2781 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18Add support for "Stout" ChromebookStefan Reinauer
We're happy to announce coreboot support for the "Stout" Chromebook, a.k.a Lenovo X131e Chromebook. Change-Id: I9b995f8d0dd48e41c788b7c3d35b4fac5840e425 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2636 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13exynos5250/snow: enable branch predictionDavid Hendricks
This enables branch prediction. We can probably find a better place to do this, but for now we'll do it in snow's romstage main(). Change-Id: I86c7b6bc9e897a7a432c490fb96a126e81b8ce72 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2701 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13src/mainboard: Drop redundant `CHIP_NAME` again for new portsPaul Menzel
Since commit »Drop redundant CHIP_NAME in mainboard.c« (a93c3fe7) [1] `CHIP_NAME` is unneeded for mainboards as the name is composed automatically in `src/devices/root_device.c` from the strings in Kconfig. Unfortunately the ports for Google Butterfly, Link and Parrot as as well as IEI PM-LX2-800-R10 introduced CHIP_NAME again. So drop it again too. [1] http://review.coreboot.org/1635 Change-Id: Ice7577a2a5c6070e196f2647c440b7a8e140e27e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2708 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13exynos5250/snow: call PMIC's power_init() functionDavid Hendricks
Call the power_init() function. We appear to have forgotten about it when deprecating lowlevel_init_subsystems(), but it didn't seem to cause problems until we got to doing more interesting stuff recently. There are some clean-ups to do from the original code, such as not attempting to configure I2C from PMIC code, which we'll get around to in follow-up patches. (Credit to Gabe for spotting this) Change-Id: I6a59379e9323277d0b61469de9abe6d651ac5bfb Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2699 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-08ARMV7 and Google/Snow: Add exception support code to the ramstageRonald G. Minnich
This is previously used exception code from libpayload. On startup it installs and then tests an exception handler. The test is an unaligned memory operation. Yes, we've seen what might be exceptions in the ramstage, and it makes sense to handle them. This code is identical in structure and operation to the previously committed payload exception handler, though we reserve the right to change it as circumstances require. The remaining question is whether we need it in romstage. Change-Id: I24484686c33c9757af8ba171ebae9773828fb69d Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2614 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-07snow: add real values for GPIOs in fill_lb_gpios()David Hendricks
This adds some real GPIO mappings where virtual GPIOs were used before. Change-Id: I25d4be45f986c8d622b97151f8bdae2651baf3e6 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2603 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-07google/snow: fix coding styleStefan Reinauer
cosmetics Change-Id: Iea33768d901641861aa7b2c76af8753a848f584d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2601 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-06samsung/exynos5: add display port and framebuffer defines and initializationRonald G. Minnich
These are essential functions for setting up the display port and framebuffer, and also enable such things as aux channel communications. We do some very simple initialization in romstage, mainly set a GPIO so that the graphics is powering up, but the complex parts are done in the ramstage. This mirrors the way in which graphics is done in the x86 size. I've added a first pass at a real device, and put it in the mainboard Kconfig, hoping for corrections. Because startup is so complex, depending on device type, I've created a 'displayport' device that removes some of the complexity and makes the flow *much* clearer. You can actually follow the flow by looking at the code, which is not true on other implementations. Since display port is perhaps the main port used on these chips, that's a reasonable compromise. All parameters of importance are now in the device tree. Change-Id: I56400ec9016ecb8716ec5a5dae41fdfbfff4817a Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2570 Tested-by: build bot (Jenkins)
2013-03-06Google/Snow: enable sound hardware clocksRonald G. Minnich
Set up the clocks used for sound and turn on the sound clock. Change-Id: Ic59bfa9ae87116299503e6d25aeefba98c842fb8 Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2587 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-06google/snow: Change MMC0 to work in 8 bit mode.Ronald G. Minnich
The MMC0 on google/snow can run in 8 bit mode. To simplify driver development, we thought disabling it (using zero, which runs in 1-bit / 4-bit mode) may help. However, after some experiments in payload drivers, setting pinmux to 8 bit mode can still allow MMC to run in 1-bit / 4-bit mode, so it's pretty safe to enable 8 bit mode by default for better performance. Verified to boot on google/snow, and got MMC0 working. Change-Id: Ic0acc723fe6a8aecf373429d3801beadd70815d9 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2585 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-01armv7/snow: Add S5P MSHC initialization in ROM stage.Hung-Te Lin
The SD/MMC interface on Exynos 5250 must be first configured with, GPIO, and pinmux settings before it can be detected and used in ramstage / payload. Verified on armv7/snow and successfully boot into ramstage. Change-Id: I26669eaaa212ab51ca72e8b7712970639a24e5c5 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2561 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-28CBMEM: always initialize early if the board supports itStefan Reinauer
This allows to drop some special cases in romstage.c Change-Id: I53fdfcd1bb6ec21a5280afa07a40e3f0cba11c5d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2551 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-28Drop SRC_ROOT from mainboard Makefile.incsStefan Reinauer
It's not used, and not needed. Change-Id: Ifca92f3606ac58fc26e09676488c3add5d84ae79 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2548 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-28Drop CONFIG_WRITE_HIGH_TABLESStefan Reinauer
It's been on for all boards per default since several years now and the old code path probably doesn't even work anymore. Let's just have one consistent way of doing things. Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2547 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-27Google/snow: update the GPIO emulation.Ronald G. Minnich
Add two more GPIOs (total 6) as needed by the Google Snow laptop. These are faking out settings for now. This code is tested and working. Change-Id: I2077ffb8b85958eefdf54e19763d57cc1178ce89 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2538 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2013-02-25google/snow: enable GPIO entries and CHROMEOS in buildingRonald G. Minnich
These were not separable or it would have been two CLs. Enable CHROMEOS configure option on snow. Write gpio support code for the mainboard. Right now the GPIO just returns hard-wired values for "virtual" GPIOs. Add a chromeos.c file for snow, needed to build. This is tested and creates gpio table entries that our hardware can use. Lots still missing but we can now start to fill in the blanks, since we have enabled CHROMEOS for this board. We are getting further into the process of actually booting a real kernel. Change-Id: I5fdc68b0b76f9b2172271e991e11bef16f5adb27 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2467 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-23Add support for Google's Chromebook PixelStefan Reinauer
Ladies and gentlemen, I'm very happy to announce coreboot support for the latest and greatest Google Chromebook: The Chromebook Pixel. See the link below for more information on the Chromebook Pixel, and its exciting specs: http://www.google.com/intl/en/chrome/devices/chromebooks.html#pixel The device is running coreboot and open source firmware on the EC (see ChromeEC commit for more information on that exciting topic) Change-Id: I03d00cf391bbb1a32f330793fe9058493e088571 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2482 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-22*/acpi_tables.c: Use ALIGN macroPatrick Georgi
At the request of Paul Menzel, I reran an old classic of a coccinelle script: @@ expression E; @@ -(E + 7) & -8 +ALIGN(E, 8) @@ expression E; @@ -(E + 15) & -16 +ALIGN(E, 16) Change-Id: I01da31b241585e361380f75aacf3deddb13d11c3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2487 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-19snow: add cpu_cluster and domain resources via devicetree.cbDavid Hendricks
This patch will cause the resource allocator to actually set aside the memory resources using methods in the previous patch. The coreboot table output will include "RAM" entries (there were none before): coreboot memory table: 0. 0000000040400000-00000000bff001ff: RAM 1. 00000000bff00200-00000000bff00fff: CONFIGURATION TABLES 2. 00000000bff01000-00000000bfffffff: RAM Change-Id: I5cd76e93fc232fdae1754253efb4e9269b3a20c0 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2420 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14Chromebooks: mainboard.c: Do not spell Chromebook in CamelCasePaul Menzel
»Chromebook« is the official spelling [1]. So correct that with the following command. $ git grep -l ChromeBook | xargs sed -i s,ChromeBook,Chromebook, The incorrect spelling was only used for the chip name. [1] http://www.google.com/intl/en/chrome/devices/hp-pavilion-chromebook.html#hp-pav Change-Id: I9c19f399a3e3d36bd644ec375822daa384a14961 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2370 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-14Google Butterfly: thermal.h: Align macro contentPaul Menzel
Change-Id: I3729f9bf66fcd72fa8870bb56a9c253a7368c774 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2371 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14snow: Set up MMU after DRAM is workingDavid Hendricks
This was omitted earlier while we were debugging DRAM code (0a5bc7f). It was likely broken due to inconsistent units earlier on. Now that things are cleaned up and working, let's add it back in. Change-Id: I2f356355c98b2896e2371fa63b9c9f20ae76d634 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2379 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14snow: remove superfluous printk's from romstage mainDavid Hendricks
These were left over from earlier debugging and are no longer needed. They don't indicate any status or useful info (other than which line of code has been executed). Error messages are available in case something needs attention. Change-Id: Ie09fac29c42908cb8924169e56d8927fb76f02da Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2386 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename pci_domain -> domainStefan Reinauer
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-12Google Butterfly: acpi/thermal.asl: Fix typo »The*re* is no …«Paul Menzel
The commit introducing support for the Google Butterfly Chromebook commit d7bd4eb003f5b6a13943418ae0ac53248a2e34d2 Author: Stefan Reinauer <reinauer@chromium.org> Date: Mon Feb 11 11:11:36 2013 -0800 Add support for "Butterfly" Chromebook Reviewed-on: http://review.coreboot.org/2359 contains the typo, which is corrected now. Change-Id: I932f4cd248cac71c3ede39a7da97162e791827cb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2373 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-12Google Butterfly: gpio.h: Correct whitespace errorsPaul Menzel
Correct some whitespace inconsistencies introduced in the following commit. commit d7bd4eb003f5b6a13943418ae0ac53248a2e34d2 Author: Stefan Reinauer <reinauer@chromium.org> Date: Mon Feb 11 11:11:36 2013 -0800 Add support for "Butterfly" Chromebook Reviewed-on: http://review.coreboot.org/2359 Change-Id: Ifeda7eb29ddf855cdfea41ddbd685441ede55756 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2374 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-12Google Parrot/Butterfly: fadt.c: Align macros correctlyPaul Menzel
The commits adding support for the Google Parrot Chromebook commit a7198b34ccf120df2a9e5b9f104812e96916ad08 Author: Stefan Reinauer <reinauer@chromium.org> Date: Tue Dec 11 16:00:47 2012 -0800 Add support for Google Parrot Chromebook Reviewed-on: http://review.coreboot.org/2026 and the Google Butterfly Chromebook commit d7bd4eb003f5b6a13943418ae0ac53248a2e34d2 Author: Stefan Reinauer <reinauer@chromium.org> Date: Mon Feb 11 11:11:36 2013 -0800 Add support for "Butterfly" Chromebook Reviewed-on: http://review.coreboot.org/2359 had macros in `fadt.c` which were not aligned correctly and did not adhere to the coding style which uses just one space after `#define`. Fix this and use tabs instead of spaces everywhere. Change-Id: I1422c57a3bdc2faa29d2a6e2064e4d3aeed0f1cb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2375 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-11Add support for "Butterfly" ChromebookStefan Reinauer
We're happy to announce coreboot support for the "Butterfly" Chromebook, a.k.a HP Pavilion Chromebook. More information at: http://www.google.com/intl/en/chrome/devices/hp-pavilion-chromebook.html This commit also includes support for the ENE KB3940Q embedded controller running on Quanta's firmware. Change-Id: I194f847a94005218ec04eeba091c3257ac459510 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2359 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2013-02-11snow: fix high_tables_base calculationDavid Hendricks
It was off by a few orders of magnitude. D'oh. Change-Id: I9c8a3d5bd9ce261f914cfc7d05d86a1c61519b81 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2355 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-11armv7/exynos5250/snow: deprecate CONFIG_{RAMBASE,RAMTOP}David Hendricks
RAMBASE and RAMTOP are leftovers from the x86 port and do not apply the same way on ARM platforms. On x86 they refer to the low memory region where coreboot tables reside. However on ARM we don't have such a region which is architecturally defined. So instead we'll use the CPU-defined DRAM base address and the mainboard-defined DRAM size. This also has the pleasant side-effect of fixing the coreboot tables to not clobber ramstage code... Change-Id: I5548ecf05e82f9d9ecec8548fabdd99cc1e39c3b Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2351 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-10exynos/snow: move SPI GPIO setup to mainboard bootblock codeDavid Hendricks
This moves GPIO setup from chip-specific SPI code to mainboard- specific bootblock code. This makes exynos_spi_open a bit more generic so it can eventually be used for any SPI channel. This also benefits CBFS since the user can set media->context to to any set of SPI registers. Change-Id: I2bcb9de370df0a79353c14b4d021b471ddebfacd Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2347 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-10exynos/snow: set SPI clock rate in romstage mainDavid Hendricks
This moves the setting of SPI clock rate into romstage's main, which allows us to eliminate a bunch of dependencies from the bootblock (about 7KB worth). Change-Id: I371499bb4af6a6aa838294bc56f9dbc21864957a Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2346 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09snow: do something useful in ramstage()David Hendricks
This cleans up Snow's trivial ramstage, gives it a coreboot table address and calls hardwaremain(). Change-Id: I84c904bcfd57a5f9eb3969de8a496f01e43bc2f6 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2328 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-08armv7/snow: Move clock initialization from bootblock to romstage.Hung-Te Lin
Exynos system clock can be initialized before RAM init, not necessary to be in the very beginning (boot block). This helps reducing bootblock dependency. Verified to boot on armv7/snow. Note: this patch was originally introduced in 2308, but there were some ordering issues so it was reverted. Change-Id: Ibc91c0e26ea8881751fc088754f5c6161d011b68 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2320 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-08armv7: Use same console initialization procedure for all ARM stagesHung-Te Lin
Use same console initialization procedure for all ARM stages (bootblock, romstage, and ramstage): #include <console/console.h> ... console_init() ... printk(level, format, ...) Verified to boot on armv7/snow with console messages in all stages. Change-Id: Idd689219035e67450ea133838a2ca02f8d74557e Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2301 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-08console: Revise serial console configuration names.Hung-Te Lin
The console drivers (especially serial drivers) in Kconfig were named in different styles. This change will rename configuration names to a better naming style. - EARLY_CONSOLE: Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE because it also supports non-serial) - CONSOLE_SERIAL: Enable serial output console, from one of the serial drivers. (Renamed from SERIAL_CONSOLE because other non-serial drivers are named as CONSOLE_XXX like CONSOLE_CBMEM) - CONSOLE_SERIAL_UART: Device-specific UART driver. (Renamed from CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped) - HAVE_UART_SPECIAL: A dependency for CONSOLE_SERIAL_UART. Verified to boot on x86/qemu and armv7/snow, and still seeing console messages in romstage for both platforms. Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2299 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-08Revert "armv7/snow: Move clock initialization from bootblock to romstage."David Hendricks
This reverts commit 9029f4b63f6d0e29bf1608e666cdb025de45ca24 This patch needs to go at the end of the UART patch set. Sorry 'bout the confusion! Change-Id: I5702c7d6130daf95776f2c15d24e5d253691cefd Reviewed-on: http://review.coreboot.org/2319 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-07armv7/snow: Move clock initialization from bootblock to romstage.Hung-Te Lin
Exynos system clock can be initialized before RAM init, not necessary to be in the very beginning (boot block). This helps reducing bootblock dependency. Verified to boot on armv7/snow. Change-Id: Ic863e222871a157ba4279a673775b1e18c6eac0d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2308 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-07armv7/snow: Remove power_init from bootblock.Hung-Te Lin
The power_init is not required on Exynos 5250 (snow) in bootblock stage. To get a cleaner and faster bootblock, we can remove it. Note, power_init internally calls max77686 and s3c24x0_i2c, so both files are also removed. Verified to boot on armv7/snow. Change-Id: I5b15dfe5ac7bf4650565fea0afefc94a228ece29 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2317 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-07armv7/snow: Remove redundant I2C initialization calls in bootblock.Hung-Te Lin
The I2C initialization (on component MAX77688) is already done in power_init, so we should not need an explicit call inside bootblock. Verified to boot on armv7/snow. Change-Id: I68c248a8b5fee4ab838b2fb708649e112559cc41 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2316 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-07armv7: Clean up arm/snow bootblock build process.Hung-Te Lin
Remove duplicated / testing code and share more driver for bootblock, romstage and ramstage. The __PRE_RAM__ is now also defined in bootblock build stage, since bootblock is executed before RAM is initialized. Change-Id: I4f5469b1545631eee1cf9f2f5df93cbe3a58268b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2282 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-06armv7: Clean up: remove deprecated SPL.Hung-Te Lin
"SPL" from U-Boot is deprecated by bootblock in coreboot/arm, so we don't need it anymore. Change-Id: Id16877075d0b870839a10160073ad70777a2af0a Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2297 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-06snow: remove dead code from bootblockDavid Hendricks
This attempts to clean out some dead code which was copy + pasted into Snow's bootblock.c file, along with some unnecessary headers. Change-Id: If9f157a52395a047c249a2a6385e0e8ddf310e59 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2291 Tested-by: build bot (Jenkins)
2013-02-06exynos/snow: Move core/memory clock-related and board ID codeDavid Hendricks
This patch moves ARM core and DRAM timing functions around to simplify the dependencies for system_clock_init(). The original code was architected such that the system_clock_init() function called other functions to obtain core and memory timings. Due to the way memory timing information must be obtained on Snow, which entails decoding platform-specific board straps, the bottom- up approach resulted in having the low-level clock init code implicitly depend on board and vendor-specific info: main() ->system_clock_init() -> get_arm_ratios() -> CPU-specific code -> clock_get_mem_timings() -> board_get_revision() -> read GPIOs (3-state logic) -> Decode GPIOs in a vendor-specific manner -> Choose memory timings from module-specific look-up table ...then proceed to init clocks ...come back to main() The new approach gathers all board and vendor-specific info in a more appropriate location and passes it into system_clock_init(): main() -> get_arm_ratios() -> CPU-specific code -> get_mem_timings() -> board_get_config() -> read GPIOs (3-state logic) -> Decode GPIOs in a vendor-specific manner -> Choose memory timings from module-specific look-up table -> system_clock_init() ...back to main() Change-Id: Ie237ebff76fc2d8a4d2f4577a226ac3909e4d4e8 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2271 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-06snow: use bootblock build class for I2C codeDavid Hendricks
This gets rid of a bunch of duplicate I2C code in the bootblock. Change-Id: I51f625a0f738cca4ed2453fbcb78092e4110bc7e Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2289 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-06snow: use bootblock build class for GPIODavid Hendricks
This gets rid of a bunch of copy + pasted GPIO code. Change-Id: I548b2b5d63642a9da185eb7b34f80cbebf9b124f Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2288 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-05snow: use bootblock build class for UART codeDavid Hendricks
This gets rid of a bunch of copy + pasted code from Exynos UART files. Change-Id: I9fbb6d79a40a338c9fdecd495544ff207909fd37 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2286 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-02-04Intel based boards: Use tab instead of spaces to align comment in DSDTPaul Menzel
Mainboards using `COREBOOT` as their OEM Table ID in their DSDT header were copied from the same source and therefore had spaces instead of a tab to align that comment for that header field. These are mostly Intel based boards. Fix that in accordance with the coding style [1]. [1] http://www.coreboot.org/Development_Guidelines#Coding_Style Change-Id: I299b955930dbd50b9717e8ff141ce8f3fd534e5f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2277 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-04exynos/snow: get rid of board-specific arbitration codeDavid Hendricks
Snow's AP, EC, PMU, and smarty battery share a bus. Both the AP and EC can act as a master, so to avoid conflicts an arbitration mechanism consisting of two GPIOs is used. By default, the AP "owns" the bus unless it is off (in which case the EC doesn't monitor the arbitration pins). This means the boot firmware does not need to worry about these lines. The payload may if it needs to communicate with the EC, though. In any case, board-specific bus arbitration logic does not belong in a low-level driver that is supposed to be generic for an entire CPU family. If the payload needs to talk to the EC, we'll deal with it there. Change-Id: I0774d4592af2b21b6ad668441532c5ceab988404 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2272 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-04exynos/snow: partial clean-up of snow bootblock using build classDavid Hendricks
This removes some duplicate code from Snow's mainboard bootblock by utilizing the bootblock build class. Change-Id: I153247370a8c5127260082dcdca3ebdc5e104fb8 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2270 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-03armv7: Add 'bootblock' build class.Hung-Te Lin
For ARM platform, the bootblock may need more C source files to initialize UART / SPI for loading romstage. To preventing making complex and implicit dependency by using #include inside bootblock.c, we should add a new build class "bootblock". Also #ifdef __BOOT_BLOCK__ can be used to detect if the source is being compiled for boot block. For x86, the bootblock is limited to fewer assembly files so it's not using this class. (Some files shared by x86 and arm in top level or lib are also changed but nothing should be changed in x86 build process.) Change-Id: Ia81bccc366d2082397d133d9245f7ecb33b8bc8b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2252 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-01snow: make romstage init DRAM controller and call ramstageRonald G. Minnich
This is a first cut at a romstage. It sets up memory, although that needs some work; and finds and loads a ramstage. Change-Id: I02a0eb48828500bf83c3c57d4bacb396e58bf9a5 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2245 Tested-by: build bot (Jenkins)
2013-02-01armv7: unify stage hand-off routinesDavid Hendricks
This replaces the current stage-specific exit/entry functions with generic versions. Now all stages compile with stage_entry(), which is placed at .text.stage_entry.armv7, and stage_exit(). Snow's ramstage files are also updated to avoid build breakage. Change-Id: I953a2c4b8121bd4b66c3362557997a9ca3aa53b0 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2254 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-01-30armv7: Add SPI driver for Exynos.Hung-Te Lin
The SPI flash driver for Exynos chipset. Verified to boot on snow/armv7. Change-Id: I7eef67a9c57f825d09f13ea44c2b59b54345fa7b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2229 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-30Extend CBFS to support arbitrary ROM source media.Hung-Te Lin
Summary: Isolate CBFS underlying I/O to board/arch-specific implementations as "media stream", to allow loading and booting romstage on non-x86. CBFS functions now all take a new "media source" parameter; use CBFS_DEFAULT_MEDIA if you simply want to load from main firmware. API Changes: cbfs_find => cbfs_get_file. cbfs_find_file => cbfs_get_file_content. cbfs_get_file => cbfs_get_file_content with correct type. CBFS used to work only on memory-mapped ROM (all x86). For platforms like ARM, the ROM may come from USB, UART, or SPI -- any serial devices and not available for memory mapping. To support these devices (and allowing CBFS to read from multiple source at the same time), CBFS operations are now virtual-ized into "cbfs_media". To simplify porting existing code, every media source must support both "reading into pre-allocated memory (read)" and "read and return an allocated buffer (map)". For devices without native memory-mapped ROM, "cbfs_simple_buffer*" provides simple memory mapping simulation. Every CBFS function now takes a cbfs_media* as parameter. CBFS_DEFAULT_MEDIA is defined for CBFS functions to automatically initialize a per-board default media (CBFS will internally calls init_default_cbfs_media). Also revised CBFS function names relying on memory mapped backend (ex, "cbfs_find" => actually loads files). Now we only have two getters: struct cbfs_file *entry = cbfs_get_file(media, name); void *data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type); Test results: - Verified to work on x86/qemu. - Compiles on ARM, and follow up commit will provide working SPI driver. Change-Id: Iac911ded25a6f2feffbf3101a81364625bb07746 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2182 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-29armv7: Clean up the mmu setup a bitRonald G. Minnich
The previous incarnation did not use all of mmu_setup, which meant we did not carefully disable things before (possibly) changing them. This code is tested and works, and it's a bit of a simplification. Change-Id: I0560f9b8e25f31cd90e34304d6ec987fc5c87699 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2204 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2013-01-19armv7/snow: get to romstageDavid Hendricks
This patch does a few things to get us into romstage: - Add romstage as a stage (a later patch adds it as a binary, which is probably wrong). The Makefile magic is complex enough that we let it build the XIP file for now, but we no longer use it. - Replace findstage with loadstage. Loadstage will find a stage, load the code to memory, and zero the remaining part of memory. Now we can link the romstage to go anywhere! - Eliminate magic offsets from code/ldscripts and centralize Kconfig variables in src/cpu/samsung/exynos5250/Kconfig. - Tidy up code and serial output Change-Id: Iae4d2f9e7f429cb1df15d49daf9a08b88d75d79d Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2174 Tested-by: build bot (Jenkins)
2013-01-18armv7: add a wrapper for romstage's main() for ARM ISAGabe Black
This adds a wrapper around main() in romstage which is compiled using -marm. This assumes that the bootblock branches to romstage in ARM mode. The long-term idea is to enforce ABI compatibility when handing off to the next stage by using shims which are which are compiled in a pre- determiend manner and leave the main portions of each stage up to whatever the compiler wants. So it will eventually look like this: 1. bootblock_main (ARM/Thumb) 2. bootblock_exit (ARM) 3. romstage_entry (ARM) 4. romstage_main (ARM/Thumb) (credit to Gabe Black for writing the patch, I'm just uploading it) Change-Id: I4fdb8d2c6c2c0a7178bcb9154c378ddce0567309 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/2175 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-18Snow bootblock (bloated/debug version)David Hendricks
This is the bloated Snow bootblock which includes: - SPI driver - UART, including requisite I2C, Maxim PMIC, and clock config code. - Adjustments for magic offsets (id section, stack pointer address) This is just a temporary solution until we have romstage loading. Once that happens, we'll rip out all but the code necessary for copying SPI ROM content into SRAM. Change-Id: I2a11e272eb9b6f626b5d9783eabb4a720a1d06be Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2170 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-17make main() in snow's romstage.c our romstage entry pointDavid Hendricks
Our earlier attempt was jumping straight from asm to the old u-boot board_init_f in lowlevel_init_c.c. We are getting ready to transition to using a real bootblock for ARM, so add romstage.c to the files compiled and we'll make main() our entry point. This also updates romstage.ld to place main() (*(.text.startup)) at the beginning of romstage. Change-Id: Ifc77a6bfba27d915c4cad62c6c8040665294628a Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2163 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-17remove argument in snow's romstage main()David Hendricks
We don't pass any arguments into romstage on ARM. Change-Id: I018f28a57fc486c9240345cf0f4043b79027d864 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2162 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10armv7: replace magic constant for romstage locationDavid Hendricks
This replaces 0x02023400 with an SoC-specific Kconfig variable. Change-Id: I21482d54a1e1fa6c4437c030ddae2b0bb3331551 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2130 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-03Rename mainboard_smi.c to smihandler.cPatrick Georgi
This mirrors the naming convention of handlers in northbridge and southbridge. Change-Id: I45d97c569991c955f0ae54ce909d8c267e9a5173 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2058 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-03import SPL files for board_i2c_{claim,release}_bus()David Hendricks
This imports SPL (second phase loader) files from U-Boot. Most of the content of these files will eventually go away since they're fairly U-Boot specific. For now they are here to make Jenkins happy. Change-Id: Ib3a365ecb9dc304b20f7c1c06665aad2c0c53e69 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2081 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2012-12-29corrections for MAX77686 config variableDavid Hendricks
Fix some minor discrepancies which prevented the MAX77676 from getting compiled in properly. Change-Id: Ib29136da6c15a4bdb24926a91729431c507cd209 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2076 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-12Add support for Google Parrot ChromebookStefan Reinauer
AKA Acer C7 Chromebook See http://www.google.com/intl/en/chrome/devices/acer-c7-chromebook.html for more information. Thank you to Sage Electronic Engineering, LLC for making this possible! http://www.se-eng.com/ Change-Id: Ic4e4d50045a82cbb82e1dea3cd5a04525a648612 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2026 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-12Add minimal mainboard support for snowRonald G. Minnich
This is the minimal set of sources that allow the board to build. These need to be filled in with actual code. But if we get these in upstream we can stop working against a WIP patch. Change-Id: I9347a573bb40761f6a12be3ee8febe3ca4be55a3 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2018 Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 02:46:00 +0000