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2019-02-18soc/intel/skylake: Use real common code for VMX initNico Huber
Use the common VMX implementation, and set IA32_FEATURE_CONTROL lock bit per Kconfig *after* SGX is configured (as SGX also sets bits on the IA32_FEATURE_CONTROL register). As it is now correctly based on a Kconfig, the `VmxEnable` devicetree setting vanishes. Test: build/boot google/[chell,fizz], observe Virtualization enabled under Windows 10 when VMX enabled and lock bit set. Change-Id: Iea598cf74ba542a650433719f29cb5c9df700c0f Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/29682 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-18mb/google/sarien: Swap FMAP location for RW_LEGACY and NVRAMDuncan Laurie
The Intel SOC can only shadow the top 16MB of SPI into memory so in order to make it easier to access the NVRAM region with memory mapped interface move it above the much larger RW_LEGACY region. I tested to confirm that this region can now be read via MMIO interface and does not need to use the hwseq SPI controller. Change-Id: Iafacb01eec07beaf474b6a1f2b36a77117e327da Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-02-18mb/google/sarien: Create VR config settingsRoy Mingi Park
Create VR settings configuration as per board design. BUG=N/A TEST=Build and boot up into sarien platform. Change-Id: Ic196fd80e5211bd5146158d4d340b52c850a4e62 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/c/31404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-18mb/google/kahlee: Enable mode change as wake source for S3Mengqi Guo
This change enables mode change as a wake source for S3. BUG=b:124132058 Change-Id: I95b1eac800858ab17cdf69bdd3f2c5828516c184 Signed-off-by: Mengqi Guo <mqg@chromium.org> Reviewed-on: https://review.coreboot.org/c/31429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-18src/mainboard/kahlee: Remove delan variantMartin Roth
BUG=b:121354442 TEST=None Change-Id: I348c7106772eecd513baf9abe60ef19008d0ba4d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/31424 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-18mb/google/sarien/variants/arcada: Update thermal configuration for DPTFCasper Chang
Update dptf for arcada EVT. BUG=b:123924662 TEST=Built and tested on arcada system Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ieed8021b83776fdb6320ff89b57c8d2747667fd5 Reviewed-on: https://review.coreboot.org/c/31331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-02-18mb/google/laser: Disable touch screen device that according to SKU IDpeichao.wang
We need disable touch screen device on laser SKU ID 6. BUG=none TEST=according to sku_id (Laser(convertible): 5, Laser14(clamshell): 6, Laser14(clamshell + touch):7) distinguish whether disable touch screen device. Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6953c35a5e8c93d88fe63362156faa351e8ee71f Reviewed-on: https://review.coreboot.org/c/31428 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-15mb/google/hatch: Enable DPTF functionalitySumeet Pawnikar
Enable DPTF functionality on hatch platform. Change-Id: If9ef74364616f95b27b73c39fea42d2623d78ae2 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/31276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-15mb/google/octopus: Fix USB ACPI configuration for CNVi BT moduleKarthikeyan Ramasubramanian
CNVi Bluetooth module is at port 8 (zero-indexed) and not at port 9. Fix the device configuration in the devicetree. BUG=b:123296264 BRANCH=octopus TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured that the kernel btusb driver is able to find the exported GPIO in the devices with CNVi BT module. Change-Id: I302bc87b18a1aaad77bfb73d607ba28b89b79c14 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/31387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-15mb/google/sarien: Set ELAN as the default for touch panelChris Zhou
According to request of comment 35, setting ELAN as the default. BUG=b:122019253 BRANCH=master TEST=Verify touchscreen on sarien works with this change. Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Change-Id: Iee5e7a21545ca798c0c22f86906acc8e7d81e945 Reviewed-on: https://review.coreboot.org/c/31430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-15mb/google/sarien/variants/sarien: Enable Elan touchscreenChris Zhou
Eanble Elan touch for sarien EVT build BUG=b:119763054 BRANCH=master TEST=Verify touchscreen on sarien works with this change. Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Change-Id: I790436338705fc9d68f714245e9b9bb518ddb30a Reviewed-on: https://review.coreboot.org/c/31413 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-13mb/google/hatch: Bump up the BIOS region to 28MiBFurquan Shaikh
This change bumps up the BIOS region to 28MiB to use the hole between SI_ALL and SI_BIOS. Since this SPI flash part is 32MiB, only the top 16MiB actually gets memory mapped. Thus, the change ensures that only RW_LEGACY lies in the 12MiB that is not memory mapped. BUG=b:123443737 TEST=Verified that hatch still boots up. Ensured that fmap dump looks correct. Change-Id: I5832d2b89c7eedfc270755e2add16131cfbddff4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-02-13mb/google/poppy/var/rammus: Enable mode change wake source for S3/S0ixFurquan Shaikh
This change enables mode change as a wake source for S3 and S0ix. Change-Id: I2e7f9997776b1e024ea417eb69e6c2ffa8c62580 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-02-13mb/google/sarien: Support multiple touchscreen at same addressDuncan Laurie
The Sarien board may have different touchscreen devices that use the same I2C slave address but have different requirements such as needing a special driver or ACPI configuration. In order to support this the devicetree may be configured with multiple devices at the same address and at boot time the unused devices will be disabled. Because there is no GPIO for selecting the device that is present it can instead be selected with Kconfig, or by setting a VPD key to the HID of the touchscreen device that is present. The default for Sarien devices is to not enable a touchscreen for the OS. The touchscreen selection is currently limited to the Sarien variant but this also adds the touchscreen HID for Arcada to Kconfig so it would not complain about the key not being set. BUG=b:122019253 TEST=This was tested on a Sarien board by adding a second entry to the devicetree at the same address. Without this change the SSDT is not loaded by the kernel because of the address conflict. After this change no touchscreen is enabled by default, but one can be selected with Kconfig or by setting the 'touchscreen_hid' VPD key. Change-Id: I4da12b1de0c551bcd89325fe0d8c66c6ffeb7afc Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-13mb/google/sarien/variants/sarien: Add GPIO H3 for DVT1John Su
Follow Northbay and intermal project to add GPIO H3(CNVI_EN#) for DVT1. BUG=b:123461432 TEST=Built and tested on sarien system Change-Id: I580a6e094d84a7bada534b14c2b65ecf4b9942b0 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-13mb/google/sarien/variants/sarien: Add GPIO H15 for DVT1John Su
Follow b:123342945 to add GPIO H15(BT_RADIO_DIS#) for DVT1. BUG=b:123342945 TEST=Built and tested on sarien system Change-Id: I0caf97f6a2a8abf2914667350c76300733ead1b8 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-13coreboot: check Cr50 PM mode on normal bootKeith Short
Under some scenarios the key ladder on the Cr50 can get disabled. If this state is detected, trigger a reboot of the Cr50 to restore full TPM functionality. BUG=b:121463033 BRANCH=none TEST=Built coreboot on sarien and grunt platforms. TEST=Ran 'gsctool -a -m disable' and reboot. Verified coreboot sends VENDOR_CC_IMMEDIATE_RESET command to Cr50 and that the Cr50 resets and then the platform boots normally. TEST=Performed Cr50 rollback to 0.0.22 which does not support the VENDOR_CC_TPM_MODE command, confirmed that platform boots normally and the coreboot log captures the unsupported command. Tested-by: Keith Short <keithshort@chromium.org> Change-Id: I70e012efaf1079d43890e909bc6b5015bef6835a Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/31260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-13mb/google/hatch: Configure GPIO pad for non-inversionAamir Bohra
This implementation configures GPIO (GPP_A21, GPP_C21, GPP_D16) pad in non-inversion mode i.e Rx PAD state is not inverted as it is sent from GPIO to IOAPIC. BUG=b:123315212 TEST=Tested for below: -> Verify touchpad is working fine. -> TPM init is successful and boot with fixed boot media. Change-Id: I6034fd07ccc96a19218d57ef8bb9049c4b963ea5 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/31328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-13soc/intel/cannonlake: Don't use CAR_GLOBALArthur Heymans
All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I72effa93e36156ad35b3e45db449d8d0d0cabf06 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-12mb/google/octopus/casta: Tune usb2eye settingSeunghwan Kim
It needs to tune usb2eye setting for these ports: USB2[4] - type-c port USB2[6] - camera BUG=b:122878632 BRANCH=octopus TEST=built and passed usb2eye SI test Change-Id: Iaa3adaab2f391e95730b141dc0237ca62c459e5a Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/31359 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-12google/kahlee: Remove unneeded HAVE_ACPI_RESUME guardKyösti Mälkki
We leave it to linker garbage collection to drop unreferenced code and symbols from final object files. Function declarations and definitions are to be guarded with preprocessor directives only as a last resort. Change-Id: Ie8748ccddc8e31569c58deba5d08c98a04326fa8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-02-11mb/google/kahlee: Use GPIO_10 for EC_SYNC_IRQEdward Hill
Use AGPIO 10 as the EC sync interrupt for MKBP events for sensor data. On this platform, interrupts are routed via the GPIO controller so need to be registered using GpioInt instead of Interrupt. BUG=b:123750725 BRANCH=grunt TEST=MKBP events still received (with matching EC and kernel changes) Change-Id: If499d24511bbaa7054207b7e0b98445723332c4f Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://review.coreboot.org/c/31278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-08mb/google/hatch: Replace part-specific SPD files with generic onesShelley Chen
Traditionally, we have always allocated 1 DRAM ID per part number. However, on nami, we have run out of DRAM IDs because we have supported so many different parts. We are now adopting the use of generic SPD files that are feature-based rather than specific to each part, allowing us to support multiple parts with a single SPD. The common SPDs were created by taking current SPDs in Nami (which is using the same DDR4 parts as Hatch) and zeroing out all the manufacturer information and part names. Additionally, we zeroed out bytes 128 (raw card extension, module nominal height), 129 (module maximum thickness), and 130 (reference raw card used) after verifying that they are not used in FSP. We verified with these fields zeroed out, all nami devices could boot up without errors. We also verified on the two Hatch skus that we have (4G 2400, 8G 2666) that the generic SPDs boot properly. BUG=b:122959294 BRANCH=None TEST=Make sure that we can boot up on both 4G Samsung and 8G Hynix DDR4 devices that we currently have. Change-Id: I14d9e6b13975b6a65b506e6cd475160711b8f6d4 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/31261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-08drivers/gpio_keys: Remove redundant is_wakeup_source flagKarthikeyan Ramasubramanian
"is_wakeup_source" flag is used to indicate if the concerned device can trigger a wakeup. This flag is redundant with the "wake" GPE event definition. So remove the redundant flag and use the "wake" GPE event to mark the wakeup source. BUG=None BRANCH=None TEST=Boot to ChromeOS. Ensure that the device is marked as wakeup-source in SSDT if wake GPE is configured. Ensure that the system can suspend and the device acts as a wakeup source Change-Id: I99237323639df1cb72e3a81bcfed869900a2eefa Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/31258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-08mb/*/*/romstage: curly braces after the function definitionPeter Lemenkov
See Documentation/coding_style.md, specifically "Placing Braces and Spaces" section. Change-Id: Ia6a2f3d3547c16500996260b0ece9ec693f00113 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/31268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-07src: Remove unused include device/pnp_def.hElyes HAOUAS
Change-Id: Ibb7ce42588510dc5ffb04c950c4c8c64e9a2fa37 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-07mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_padsFurquan Shaikh
This change uses cnl_configure_pads to configure GPIOs in ramstage so that cannonlake SoC code can re-configure the GPIOs after FSP-S is run. This is just adding a workaround until FSP-S is fixed. BUG=b:123721147 BRANCH=None TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch. Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-02-07soc/intel/cannonlake: Add Whiskeylake SoC kconfigSubrata Banik
This patch performs below tasks 1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig. 2. Allow required SoC to select this kconfig to extend CANNONLAKE SoC support and add incremental changes. 3. Select correct SoC support for hatch, sarien, cflrvps and whlrvp. * Hatch is WHL SoC based board * Sarien is WHL SoC based board * CFLRVP U/8/11 are CFL SoC based board * WHLRVP is based on WHL SoC 4. Add correct FSP blobs path for WHL SoC based designs. Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-06mb/google/hatch: Configure I2C busesFurquan Shaikh
This change enables I2C bus 2, 3 and 4 in devicetree and configures GPIO pads for the same. It also configures pads for I2C5 as no-connect. BUG=b:123711244 TEST=Verified that i2c shows up in "i2cdetect -l" after booting to OS. Change-Id: Ib4714a670d73228332115415e4393f82802c6475 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31237 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-06mb/google/reef: Expand the coreboot RO sectionMathew King
Current coreboot size is not adequate for adding new features. Note for cros: This change is for merge to ToT only and should not be cherry-picked into reef's firmware branch. BUG=chromium:903833 TEST=emerge-reef coreboot Change-Id: Ie7a25c4638c474e81fb34b57de0dfc1bf393ea67 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/31230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05mb/google/sarien: Set system type for the board variantsDuncan Laurie
Select the appropriate system type for the different variants of the Sarien board. This will allow the Arcada variant to use the tablet mode feature of the Intel Virtual Button driver. Change-Id: I8a829aab012256ec196c8ec0fa298fd2bc77f2e1 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05mb/google/hatch: Add keyboard backlight supportIvy Jian
This change adds keyboard backlight feature for Hatch platform. BUG=b:122799544 BRANCH=none TEST=keyboard backlight works when EC reports correct info. Change-Id: I29273122f061e0e442f6629351ef3670535c0507 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31175 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-05mb/google/poppy/variants/atlas: config GPP_D1 as no-connectCaveh Jalali
This reconfigures the GPP_D1 GPIO pin as a no-connect. It really doesn't go anywhere today or on previous revs of the board. BUG=b:110614620 BRANCH=none TEST=atlas still boots Change-Id: Iea53cf909f8f060c4e0f14e8b4ad579b838b7caa Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/31210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05Revert "mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHz"Caveh Jalali
This reverts commit 7696290004b6490c7ef8027d7ddf67b163e7dad8. We're seeing trackpad problems on some units with the I2C bus running at 1MHz but not at 400KHz. So, revert back to 400KHz until we understand how to make 1MHz operation more robust. BUG=b:123650686 Change-Id: Ifb06afece9eee0c153240d35e6c3001f5b74f310 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/31212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05mb/google/kukui: Add default HWID for Chrome OSHung-Te Lin
The default value for Chrome OS HWID should be different. Calculated as HWID v1. BUG=b:123336677 BRANCH=kukui TEST=build and boots properly. Change-Id: I39c640562c1c3b117292b8abacd36a4a9c2fa6c6 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/31088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-05mb/google/octopus: Add USB ACPI configuration for CNVi BT moduleKarthikeyan Ramasubramanian
This change enables exporting the reset GPIO for CNVi Bluetooth module to the kernel for use in an rf-kill operation. BUG=b:123296264 BRANCH=octopus TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured that the kernel btusb driver is able to find the exported GPIO in the devices with CNVi BT module. Change-Id: I10f28bfe705da5104d709ae2ed91a8ae003fa639 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/31183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05mb/google/hatch: Add USB port capability ACPI support for USB2 port10Aamir Bohra
This implementation adds support to create ACPI package for USB port capability (_UPC) and physical location of device (_PLD) for USB2 port 10. BUG:b:123375275 TEST:Verify _UPC and _PLD ACPI packages gets published for USB2 Port 10 in SSDT and BT is functional in discrete and integrated mode. Change-Id: Ifeab24505a700e8e4677be20074c7d0400769cec Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/31197 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-04soc/intel/cannonlake: Remove SOC_INTEL_CANNONLAKE_MEMCFG_INIT KconfigSubrata Banik
This patch removes duplicate selects of same SOC_INTEL_CANNONLAKE_MEMCFG_INIT from various CFL/WHL SoC based boards to include cnl_memcfg_init.c file and include the cnl_memcfg_init.c file by default in CNL SoC Makefile.inc. Change-Id: Ib21ea305871dc859e7db0720c18a9479100346c3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-01mb/google/hatch: Enable S0ixShelley Chen
BUG=b:123540469 BRANCH=None TEST=None Change-Id: I713e6ad70efdd152895afa45aee44a5b53a8136b Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/31157 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-31mb/google/sarien: Turn on ASPM L1.2 for Card ReaderLijian Zhao
Enable ASPM L1.2 support for embedded realtek card reader, after change the power consumption for SD controller from 5mW to less than 2mW. BUG=N/A TEST=Build and boot up on Arcada platform, check the PCI configuration on pcie root port offset 0x208 is 0x0f, and offset 0x168 on card reader is also 0x0f. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I08d85ee332ceee8ed85cd816bc3e6c895528fdb0 Reviewed-on: https://review.coreboot.org/c/31145 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-31mb/google/octopus: Add Bluetooth USB ACPI configurationKarthikeyan Ramasubramanian
Enable USB ACPI driver for octopus boards and add bluetooth USB ACPI configuration in devicetree. This change enables exporting the bluetooth reset GPIO to the kernel for use in an rf-kill operation. BUG=b:123296264 BRANCH=octopus TEST=Boots to ChromeOS Change-Id: Ie40f1ad70f21a6fd398ce23d060e0c588ba6ce41 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/31130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-31google/kukui: Set GPIO_RESET to output modeTristan Shieh
In payloads, we didn't set GPIO modes. We have to set up GPIO mode in coreboot for payloads. BUG=b:80501386 BRANCH=none TEST=HW reboot works in depthcharge Change-Id: Ibd2c6c071871edc59497fbb245cdbec6a814f621 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31148 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-30mainboard/{google,intel}: Remove SaGv hard codingRonak Kanabar
Remove hard coding for SaGv config in devicetree.cb and apply macro for SaGv config for CNL variants boards Change-Id: If007589d5c1368602928b1550ec8788e65f70c05 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/31120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-30mb/google/sarien/variants/arcada: Adjust TP/TS/H1 I2C CLK to meet specCasper Chang
After adjustment on Arcada EVT TouchScreen: 390 KHz TouchPad: 389 KHz H1: 389 KHz BUG=b:120584026, b:120584561 BRANCH=master TEST=emerge-sarien coreboot chromeos-bootimage measure by scope Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ia6eb332e7a664b211a5025ad07e0d01bf7f8d5bb Reviewed-on: https://review.coreboot.org/c/31124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-30mb/google/octopus/casta: Correct unused GPIO pad configurationSeunghwan Kim
Real unused GPIO pad is GPIO_123, but GPIO_122 is configured as unused pad. This patch corrects the configuration. BUG=NONE BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: I4473bd66a4162f5aee3b998aacba906824728fc8 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/31135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-01-30mb/google/hatch: Enable AP Wake from ECShelley Chen
Initialize EC_PCH_WAKE_ODL GPIO to make sure that ec events will wake the AP from suspend. Also create a task to initialize the hostevent wake mask properly. BUG=b:123325238,b:123325720 BRANCH=None TEST=from AP console: powerd_dbus_suspend from EC console: hostevent (make sure wake mask set) from EC console: gpioset PCH_WAKE_L 0 Make sure device wakes up Also, checked to make sure keyboard press wakes up device from S3. Change-Id: I53d5291a6b9ab9a21e89ccd21f172180ce473bd5 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/31100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-29mb/google/octopus/var/phaser: Hook up Raydium touchscreenHao He
List Raydium touchscreen in the devicetree so that the correct ACPI device are created. BUG=b:121105424 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage reflash the coreboot to DUT, make sure the Raydium touchscreen can work. Change-Id: I9ffb2a858f31a8b003086806de07f4079870cddf Signed-off-by: Hao He <hao.he@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31116 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-29google/kukui: Move some initialization from bootblock to verstageYou-Cheng Syu
MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. This CL moves some initialization steps from bootblock to verstage. This will save us about 2700 bytes (before compression) / 1024 bytes (after LZ4 compression) in bootblock. In case of CONFIG_VBOOT is disabled, these initialization steps will be done in romstage. BRANCH=none BUG=b:120588396 TEST=manually boot into kernel Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/30331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-29google/kukui: Implement HW reset functionTristan Shieh
Asserting GPIO PERIPHERAL_EN8 will send a signal to EC to trigger a HW reset for SoC and H1. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; manually verified the do_board_reset() on Kukui P1 Change-Id: I9afad84af2031a766bc08fc76c8b5f55588c453a Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31118 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-29mediatek: Separate WDT reset function from WDT driverTristan Shieh
Separate WDT reset function from WDT driver, then we can use the common WDT driver and have a board-specific reset function on different boards. In Kukui, we plan to use GPIO HW reset, instead of WDT reset. Add config "MISSING_BOARD_RESET" in Kukui to pass the build for now. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot; emerge-kukui coreboot; Change-Id: Ica07fe3a027cd7e9eb6d10202c3ef3ed7bea00c2 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31121 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-28mb/google/octopus: Fix termination for unused dual voltage pinsShamile Khan
These pins should not have pull downs configured in standby state as that can cause contention on the termination circuitry and lead to incorrect behavior as per Doc# 572688 Gemini Lake Processor GPIOTermination Configuration. BUG=b:79982669 TEST=Checked that code compiles with changes. Change-Id: If3cadc000ec6fc56019ee3f57e556dc819d5e0a5 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/c/30823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-28mainboard/google/octopus/variants/casta: Decrease touchpad I2C CLK frequencySeunghwan Kim
ELAN touchpad supports up to 400KHz, so we need to limit its CLK frequency to 400HKz. BUG=b:123376618 BRANCH=octopus TEST=built and verified touchpad I2C clk frequency gets be lower than 400KHz Change-Id: If7a43fe20c7e5abdf23c8c36e34c072c371563bf Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/31085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-28mb/google/sarien: Using HID over I2C to enable Melf TouchScreenChris Zhou
Current Melfas touchscreen driver cannot unregister ifself when connecting without Melfas touchscreen or connecting with other devices. And Melfas touchscreen FW can use I2C and HID over I2C driver, so switch to using HID over I2C driver. BUG=b:122710830 BRANCH=master TEST=Verify touchscreen on sarien works with this change. Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Change-Id: If04a2904a0f72a6c8363ab2c9865926c71cb5186 Reviewed-on: https://review.coreboot.org/c/31062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-25mb/google/octopus: Override emmc DLL values for AmptonKane Chen
New emmc DLL values for Ampton BUG=b:122307153 TEST=Boot to OS on 5 systems Change-Id: Iadd58d254f4bb384f483c2c3e5615f7569d5211c Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/31048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-01-25mb/google/sarien: Force power on after cr50 updateDuncan Laurie
By default this board is configured to not power up after an EC reset. However in the case of a cr50 firmware update that will reset the EC it will end up powered off. In order to have it stay powered up configure the board to power up. This will get reset to the configured default when it boots again. BUG=b:121380403 TEST=update cr50 firmware and reboot to ensure system boots and does not end up powered off. Change-Id: I85beae24b1bc56bb0813f1fd1305218f04b0c1c8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31058 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25mb/google/sarien: Increse BIOS region size to 28MBLijian Zhao
Increase BIOS region(SI_BIOS) from 16MB to 28MB to make more spaces for upcoming payloads. BUG=b:121169122 TEST=Build and boot up fine into OS on sarien and arcada platform. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I4b03e20a485cb819b468c00e68f1539e92731237 Reviewed-on: https://review.coreboot.org/c/31054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-25mb/google/kahlee/variants/aleena: Add support Synaptics touch padLucas Chen
Add support Synaptics touch pad for Aleena/Kasumi. BUG=b:122549449 BRANCH=master TEST= Check if synaptics touch pad working in ChromeOS. Change-Id: Icab1b312f1943b27037ef458044ce9e7172919ee Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31064 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25sb/intel/common: Show "Add gigabit ethernet firmware" only for boards that ↵Jan Tatje
need it Hide "Add gigabit ethernet firmware" option for boards that do not use GbE firmware in GbE section. The option is now hidden by default and can be reenabled on a per-board basis by selecting MAINBOARD_USES_IFD_GBE_REGION in the mainboards Kconfig. The following boards seem to use this: mb/roda/rv11 mb/ocp/wedge100s mb/ocp/monolake mb/lenovo/x230 mb/lenovo/x220 mb/lenovo/x201 mb/lenovo/x200 mb/lenovo/t530 mb/lenovo/t520 mb/lenovo/t430s mb/lenovo/t430 mb/lenovo/t420s mb/lenovo/t420 mb/lenovo/t400 mb/kontron/ktqm77 mb/intel/saddlebrook mb/intel/kblrvp mb/intel/dg43gt mb/intel/dcp847ske mb/intel/coffeelake_rvp mb/intel/camelbackmountain_fsp mb/hp/revolve_810_g1 mb/hp/folio_9470m mb/hp/compaq_8200_elite_sff mb/hp/8770w mb/hp/8470p mb/hp/8460p mb/hp/2760p mb/hp/2570p mb/google/sarien mb/facebook/watson mb/compulab/intense_pc mb/asus/maximus_iv_gene-z The boards were identified by looking at devicetree.cb, but this list is possibly still incomplete. Change-Id: Ibfb07902ad93fe5ff2bd4f869abcf6579f7b5a79 Signed-off-by: Jan Tatje <jan@jnt.io> Reviewed-on: https://review.coreboot.org/c/30790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-24mb/google/sarien/variants: Set tcc offset valueSumeet Pawnikar
Set tcc offset value to 5 degree celsius for Sarien system. BRANCH=None BUG=b:122636962 TEST=Built and tested on Sarien system Change-Id: I06fbf6a0810028458bdd28d0d8a4e3b645f279ca Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/31037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2019-01-24mb/google/sarien: Fix recovery mode detectionDuncan Laurie
In order to support the physical recovery GPIO on sarien it needs to enable the option VBOOT_PHYSICAL_REC_SWITCH and set the GPIO number in the coreboot table appropriately so that depthcharge can correctly determine the GPIO number. The same is done for the write protect GPIO in this table. Additionally since we are reading a recovery request from H1 it needs to cache the result since H1 will only return true on the first request. All subsequent queries to H1 will not indicate recovery. Add a CAR global here to keep track of the state and only read it from H1 the first time. BUG=b:121380403 TEST=test_that DUT firmware_DevMode Change-Id: Ia816a2e285d3c2c3769b25fc5d20147abbc71421 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31043 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24mb/google/octopus/bobba: Add support to handle PEN_EJECT eventKarthikeyan Ramasubramanian
Enable gpio_keys driver for bobba and add required configuration in the device tree to handle the pen eject event. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus tools open on pen eject. Ensure that the system wakes on Pen Eject. Ensure that the system enters S0ix and S3 states after the pen is ejected. Ensure that the system enters S0ix and S3 states when the pen remains inserted in its holder. Ensured that the system does not wake when the pen is inserted. Ensure that the suspend_stress_test runs successfully for 25 iterations with the pen placed in its holder. Change-Id: I768b89d2b45f4dcab6d235b11ce00544a827f22d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/30108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24mediatek/mt8183: Move some initialization into mt8183_early_initYou-Cheng Syu
MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. This CL adds a new function mt8183_early_init, which includes all initializations that should be done in early stages. All mainboards using MT8183 should manually call it in either bootblock or verstage. BRANCH=none BUG=b:120588396 TEST=manually boot into kernel Change-Id: I35d7ab875395da913b967ae1f7b72359be3e744a Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/31024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-24mb/google/hatch: Enable support for WWANMaulik V Vaghela
This patch enables relevant GPIOs to enable WWAN. WWAN also requires to enable USB 2 port 6 and USB3 port 5 which is already enabled in device tree related changes. BUG=b:120914069 BRANCH=none TEST=check if code compiles with changes. Change-Id: I1559bbc6168aec1a369bf3291d2c1e2f9a2fbe07 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24mb/google/hatch: Enable PCIe WLAN and BTMaulik V Vaghela
Enable PCIe WLAN for hatch 1. Enable PCI port 14 for PCIe WLAN 2. Enable CLKREQ, CLK SRC 3 for PCI port 14 3. GPIO pad config for WLAN and BT USB port for BT has already been enabled so not included in this patch BUG=b:120914069 BRANCH=none TEST=check if code compiles correctly and verify GPIO configuration with schematics Change-Id: I4f2a6eb37a467ad8b8cdde8fe6b657fabb383b04 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-01-24cpu/intel/model_206ax: Remove the notion of socketsArthur Heymans
With the memory controller the separate sockets becomes a useless distinction. They all used the same code anyway. UNTESTED: This also updates autoport. Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31031 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23mb/google/sarien: Replace B0D4 with TCPUSumeet Pawnikar
Replace B0D4 with TCPU for DPTF thermal sensor. This helps to maintain consistency between coreboot and UEFI BIOS. Change-Id: I024068c19160e1c08badef3d304ada14455c045f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/31028 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23mb/*/*/devicetree.cb: Make sandybridge devicetree uniformArthur Heymans
This is a merely cosmetic change. Change-Id: If36419fbee9628b591116604bf32fe00a4f08c17 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-23google/kukui: Revise FMAP layout for larger CBFSHung-Te Lin
Kukui with vboot enabled will build with `detachable_ui`, which needs larger space in CBFS for more complicated assets. So we need to revise FMAP sections: - BOOTBLOCK (not really used) only needs <= 32K. - GBB can be much smaller since assets moved from GBB to CBFS. - FMAP is re-ordered (with the cost of less efficient in bsearch) so CBFS can get larger continuous space. - COREBOOT(CBFS) should take all space left. Since FMAP and COREBOOT have changed location, the system will need to reflash EC (which contains the new bootblock) as well. BUG=b:123202015 TEST=Builds and boots on Kukui P1 Change-Id: I22cff99dca8c396c5897c3f6631721af40f3ffbd Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/31035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-23mb/google/poppy/variant/nami: disable unused usb2 portsRen Kuo
disable unused usb2 ports of bard and ekko skus BUG=120874946 TEST=build a test firmware and run lsusb to check usb ports Change-Id: I2ef3cd17ada8b65c96bc80675650905949f235e1 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30986 Reviewed-by: Vincent Wang <vwang@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23mb/google/arcada: Add settings for noise mitgationCasper Chang
Enable acoustic noise mitgation for arcada platform, the slow slew rates are fast time dived by 2. BUG=none BRANCH=none TEST=none Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ia838818a76a7f638b24146f3eb48493a4091c9cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/31034 Reviewed-on: https://review.coreboot.org/c/31034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-23mediatek/mt8183: Add Micron 4GB LPDDR4X DDR supportHuayang Duan
BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: I985c5061ce4ed4d88a17619aa5cde7d0121dd3a3 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-01-23mb/google/poppy/variants/nami: close the FP power in S5Ren Kuo
close the FP module power in power off (s5) BUG=122887366 BRANCH=Nami TEST= build test firmware and measure the fp power enable pin Change-Id: I80ddfbf1edf7c6435d263d5f5e0edb8b8701817d Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30910 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Vincent Wang <vwang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23mb/google/hatch: Enable SD card support for hatchMaulik V Vaghela
Enable support for SD card support for hatch 1. Enable PCI device for SD and also configure SD detect GPIO 2. Configure SD card related GPIOs in gpio.c BUG=b:120914069 BRANCH=none TEST=Verify GPIO configuration with schematics Change-Id: I8ccaa28323b1e1fcc192e245347a96309227660b Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-23mb/google/octopus: Override emmc DLL values for MeepKane Chen
New emmc DLL values for Meep. BUG=b:122308271 TEST=Boot to OS on 13 Meep system Change-Id: I4247114ed69ff3aa283f0f72d5531ad0f37309ad Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/31021 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22Revert "UPSTREAM: mainboard/google/kahlee: Also configure GPIO_9 in RAM stage"Daniel Kurtz
This reverts commit 3278f859c3dd97a6d6d885a91dfd33d44e95d58b. Reason for revert: It turns out all we want to set in RAM stage is GPIO's DEBOUNCE config, not its SCI configuration. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BUG=b:113880780 BRANCH=none TEST=Boot grunt, does not go to recovery screen Change-Id: I500934f3e03e66c97873accd4a979a23d4509675 Reviewed-on: https://review.coreboot.org/c/30997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-01-22mb/google/hatch: Remove MAINBOARD_USES_IFD_EC_REGION selectionSubrata Banik
hatch shouldn't make use of internal ec.bin through IFD tool. Change-Id: Ib1a324291b1c8ac90a7d790b63427b2e85c74fd1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-01-20mb/google/octopus/variants: Disable xHCI compliance mode for FleexAmanda Huang
Some usb devices exhibits signal loss which causes xHCI entering compliance mode. The resolution is to disable xHCI compliance mode. BRANCH=octopus BUG=b:120009029 TEST=Verified usb operation successfully. Change-Id: Ic7fa08c894397598dee3c4ff9a764e43383a0627 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-01-20mb/google/octopus/variants/meep: Disable xHCI compliance modeWisley Chen
Some usb devices exhibit signal loss which causes xHCI entering compliance mode. The resolution is to disable xHCI compliance mode. BUG=b:122671995 TEST=check "Disable Link Compliance Mode" bit of "SuperSpeed Port Link control" register and usb operation successfully. Change-Id: Ia2ae7e52391fadc8ed23b8b76c45d410757d22ec Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/30948 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18mb/google/sarien/variants: Add Thermal Sensors informationSumeet Pawnikar
Add available thermal sensors information for CPU throttling action. BRANCH=None BUG=b:120058043 TEST=Built and tested on Arcada system Change-Id: I748ca0ce43915c96d71e63fb03fc3d1a02adc56c Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/30919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-18mb/google/sarien/variants/sarien: Adjust TP/TS/H1 I2C CLK to meet specDtrain Hsu
After adjustment on Sarien EVT TouchScreen: 380.7 KHz TouchPad: 379.3 KHz H1: 392.2 KHz BUG=b:122657195 BRANCH=master TEST=emerge-sarien coreboot chromeos-bootimage measure by scope Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I0dd92b054d934b38a17898dc8ce9cc18bda1633f Reviewed-on: https://review.coreboot.org/c/30949 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-17mb/google/hatch: Configure miscellaneous featuresRonak Kanabar
set SaGv = SaGv_Enabled , To Enable System Agent dynamic frequency support set HeciEnabled = 1, To Enable heci communication set speed_shift_enable = 1 To Enable Speed Shift Technology support Change-Id: Iea90a65a77ef5e45a802cfe6fd31e1921163b02b Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/30774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-01-17src/mainboard/google/sarien: query recovery mode from Cr50Keith Short
On the Sarien/Arcada platforms, the EC is not trusted to provide the state of the ESC+REFRESH+PWR recovery combination. On these platforms the Cr50 latches the state of REFRESH+PWR for use as the recovery mode key combination. BUG=b:122715254 BRANCH=none TEST=Verify recovery mode screen shown after pressing REFRESH+PWR Change-Id: If336e9d7016987be151ab30d5c037ead3a998fe0 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/30937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-17hatch: Add sbmios_mainboard_sku functionShelley Chen
BUG=b:122578255 BRANCH=None TEST=mosys platform id/name/family Change-Id: I6288ea1a4e9f692b6e04440e61f59ea53f01ebec Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/30944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-17hatch: disable sw syncShelley Chen
Disabling software sync since EC patches haven't landed yet. BUG=b:120914069 BRANCH=None TEST=build bios image and make sure gbb flag 0x200 is set Change-Id: I1661bcd6ebbee6d9aa8068efcc18b259fb4c8203 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/30943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-16mb/google/sarien/variants/sarien: Set up tcc offset for sarienJohn Su
Change tcc offset from 15 to 3 for sarien. BUG=b:122636962 TEST=Match the result from TAT UI Change-Id: I1c5d144e92d1e6e9c81b3e6686805ccf744b7203 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30808 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16mainboard/google/kahlee: Also configure GPIO_9 in RAM stageDaniel Kurtz
The general rule is to configure GPIOs used by coreboot in bootblock (using the reset table), and GPIOs used by OS in RAM stage. However, GPIO_9 will be used as both, and we need to reconfigure it to properly set up debounce, however, it is no longer possible to change bootblock, so we also configure it in RAM stage to make the new debounce configuration take affect. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BUG=b:113880780 BRANCH=none TEST=Reboot stress test grunt (>100 times); no messages in dmesg like: tpm tpm0: Timeout waiting for TPM ready Change-Id: I0f1bca176ed3f9cebf6b9e9e1008905e492a2f03 Reviewed-on: https://review.coreboot.org/c/30922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-01-16mb/google/kahlee/careena: Add 20ms delay to captureAkshu Agrawal
define wakeup-delay-ms to 20ms. This avoids the pop noise heard at the start of capture. BUG=b:119926436 TEST=with kernel patch https://lore.kernel.org/patchwork/patch/1029806/ no pop sound heard at start of capture Change-Id: I299a584ef2ba66d1e752515100cbe3919b2108f6 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/c/30726 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16mb/google/kahlee/liara: Add 20ms delay to captureAkshu Agrawal
define wakeup-delay-ms to 20ms. This avoids the pop noise heard at the start of capture. BUG=b:119926436 TEST=with kernel patch https://lore.kernel.org/patchwork/patch/1029806/ no pop sound heard at start of capture Change-Id: I2593afa69cfb955f6a2b695406855e0f31f28468 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/c/30725 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16nb/intel/sandybridge: Remove the C native graphic initArthur Heymans
Libgfxinit provides a better alternative to the native C init. While libgfxinit mandates an ada compiler, we want to encourage use of it since it is in much better shape and is actually maintained. This way libgfxinit also gets build-tested by Jenkins. Change-Id: Ic6678d3455f1116e7e67a67b465a79df020b2399 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/27532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-16mb/google/sarien: Enable Camarillo DeviceLijian Zhao
Whiskeylake processor have an internal device called Camarillo dedicated for thermal management support, turn it on so processor thermal driver can be loaded. BUG=N/A TEST=Boot up and run lspci on Sarien board, Bus 0 Device 4 Funcion 0 can be seen. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I937960fde2704cddb1fe0058ab622f4b5de401d7 Reviewed-on: https://review.coreboot.org/c/30858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-16mb/google/sarien: Set PL1 and PL2 valuesSumeet Pawnikar
Set PL1 and PL2 values to 25W and 51W respectively for processor power limits control. BRANCH=None BUG=b:122343940 TEST=Built and tested on Arcada system Change-Id: I4098f334ed5cb6c4a6f35f1a7b12809f34c23fa3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/30908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
Does not fix 3rdparty/, *.S or *.ld or yet. Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/17656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-16mb/google/sarien: Set Vref Config to 2Lijian Zhao
Accoding to desciption in FSP header, Vref Configuration will be set to 2 if VREF_CA to CH_A and VREF_DQ_B to CH_B. BUG=N/A TEST=Build and boot up on Arcada platform. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I02e16e141b81d766a6060ca08283f432abd96647 Reviewed-on: https://review.coreboot.org/c/30280 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-15mb/google/atlas: Enable camera module NVMChen, JasonX Z
Enable at24 EEPROM by adding ASL of nvm BUG=b:122583978 BRANCH=master TEST=Build and run for basic camera functions Change-Id: Ifc2060c2ceb7d1a8ef490f36f484deb425a37c95 Signed-off-by: Chen, JasonX Z <jasonx.z.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/30795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-01-15mb/*/*: Use libgfxinit on sandy and ivy bridge boardsArthur Heymans
Change-Id: I41ad1ce06d9afcc99941affa232fa76ffa6631fb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/27531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-14Revert "mb/google/kalista: Disable EC-EFS"Patrick Georgi
This reverts commit 4e3cd744492c7a3d80bca55a35276efeada731e5. Reason for revert: Daisuke says "We'll keep EFS on Kalista/Karma enabled" Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I2f11ffc9dd7eb05a2560261bbf472e8488c274d9 Reviewed-on: https://review.coreboot.org/c/30857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14console: Change BOOTBLOCK_CONSOLE default to `y`Nico Huber
Invert the default instead of selecting it everywhere. Restores the ability to use its Kconfig prompt. Beside Qemu targets, the only platforms that didn't select it seem to be samsung/exynos5420, intel/cannonlake, and intel/icelake. The latter two were about to be patched anyway. Change-Id: I7c5b671b7dddb5c6535c97c2cbb5f5053909dc64 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30891 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14/src/mb/google/poppy/variants/atlas: Revise SPK resetGaggery Tsai
This patch revises the pad reset config of speaker reset GPIO pin from RSMRST to PLTRST. Audio engineer suggested to reset the amps with warm reset. BUG=b:122441567 BRANCH=None TEST=warm & cold reset & suspend_stress_test -c 10 and ensure the speakers are working well. Change-Id: I87c554b186b068da93e1662a97afaf01dddae0ef Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/30866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-14mb/google/octopus/variants: Configure PLT_RST_L pad IOSSTATE maskedJohn Zhao
PLT_RST_L was asserted twice at boot-up and a glitch was observed when coming out of suspend mode. Configure PLT_RST_L pad IOSSTATE from HIZCRx1 to be masked. BRANCH=octopus BUG=b:117302959 TEST=Verified no glitch on PLT_RST_L at S3 and PLT_RST_L stays high 3.3v during S0ix. Change-Id: I8c23aadda72be54fb45e67aab2bc8ed51e473bae Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30815 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14mb/google/octopus/variants: Disable xHCI compliance modeJohn Zhao
Some usb devices exhibits signal loss which causes xHCI entering compliance mode. The resolution is to disable xHCI compliance mode. BRANCH=octopus BUG=b:115699781 TEST=Verified usb operation successfully. Change-Id: I41fecaa43f4b1588a0e4bbfc465d595feb54dd24 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30817 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-03 03:39:12 +0000