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2017-11-28mb/google/poppy/variants/nautilus: set I2C speed to 400KHzChris Wang
Add "speed_config" for each I2C port configuration to set speed to 400KHz. BRANCH=master BUG=none TEST=compiled/verified Change-Id: Icb48733b87cefc92577547b1eab661a8cbb12be6 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22589 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-28mb/google/poppy/variants/nautilus: Change IA/GT/SA slow slew rate settingsChris Wang
Change IA/GT/SA slow slew rate settings. System's audible noise will be reduced with them. - Slow slew rate for IA/GT/SA : fast/16 - Fast PKG C-state ramp for IA/GT/SA: disabled BRANCH=master BUG=none TEST=compiled/verified Change-Id: Ibf11aba7bafb3b02c510905d7d904507eee6394b Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: shkim <sh_.kim@samsung.com>
2017-11-28mb/google/soraka: configure WLAN_PE_RST gpio in early_gpio_tableDivya Chellap
On shutdown, Soraka enters Deep S5 and not S5 state. Setting pad reset config of a gpio to RSMRST will not preserve the gpio config across deepSx and the gpio should be configured again. The WLAN_PE_RST signal should be brought up early in the bootflow for giving the device enough time to initialized before PCIE init in FSP-S. Hence, the gpio WLAN_PE_RST (GPP_B8) pad configuration is done in early pad configuration in bootblock also. BUG=b:64386481 BRANCH=none TEST= WiFi functionality across S5, S3, DeepS3, S0ix and warm/cold reboot. Change-Id: I5c7a4a3871a3bff69c1136379c78a8368c6258a6 Signed-off-by: Divya Chellap <divya.chellappa@intel.com> Reviewed-on: https://review.coreboot.org/22587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-11-28mb/google/poppy/variants/nautilus: correct the SIO_EC_ENABLE_P2SK typoChris Wang
correct the typo from SIO_EC_ENABLE_P2SK to SIO_EC_ENABLE_PS2K. BRANCH=master BUG=b:66462881 TEST=compiled/boot to ChromeOS. Change-Id: Iaded458e202bc975c73cd295f7b363e2c9bfa861 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: shkim <sh_.kim@samsung.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28mb/google/poppy/variants/nautilus: remove ALS for nautilusChris Wang
nautilus doesn't support ALS. remove the definition from ec.h. BRANCH=master BUG=b:66462881 TEST=compiled/boot to ChromeOS. Change-Id: Ib357328799015f78b18cd260db221e524e98cef7 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: shkim <sh_.kim@samsung.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28mainboard/google/kahlee: Update Grunt for 16MB ROM chipMartin Roth
- Update Grunt to 16MB chip in Kconfig. - Move chromeos.fmd into variant directory & update Kconfig with the new location. - Add Grunt specific chromeos.fmd file. BUG=b:69691210 TEST=Build grunt; Build & Boot Kahlee Change-Id: I8d2f5e3255984d0d9a18df560f84f6db03b73a78 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-28mainboard/google/kahlee: Update chromeos.fmdMartin Roth
- Remove SI_ALL section. This is no longer needed as the PSP dirctory is placed into the RO coreboot section. - Add 1MB Legacy section. - Add Memory cache section. These sections are called "MRC", which is an Intel term, but AMD platforms will use the same regions for saving the same sort of data. BUG=b:65497959, b:67035984 TEST=Build & boot kahlee Change-Id: I5e41a0aa6bd4b29b8014c6559126a29cd7ed45d8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-27google/fizz: correct memory rcomp settingsKane Chen
Follow the schematic and Doc 573387 to correct the rcomp and rcomp target settings for fizz TEST= boot ok and the system can enter and resume from S3. Change-Id: Iffa90461509cfadaca20e335a6655e549e79e749 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/22479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-25google/fizz: Remove tpm i2c configs from KconfigShelley Chen
We are disabling tpm over i2c, so the configs are not needed anymore. BUG=b:65056998 BRANCH=None TEST=emerge fizz and make sure can still boot up. Change-Id: Id88f32fa952801749544534442fc15d85fc1a892 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-25google/fizz: Disable unused i2c linesShelley Chen
As cr50 has now switched to using SPI, no need to enable the i2c1 anymore. Additionally, disabled unused I2C devices -- I2C0, I2C2 and I2C3. BUG=b:69374421 BRANCH=None TEST=test on fizz celeron. Make sure /dev/tpm0 created on (many) reboots. cat /proc/interrupts. Make sure # interrupts for 16 after booting is reasonable (not > 10k) and idma64.0, i2c_designware.0 are not listed with that interrupt line anymore. Should look something like this: 16: 1174 0 IO-APIC 16-fasteoi i801_smbus, snd_soc_skl, AudioDSP Change-Id: Iac3e31264a937a1d7ed6bd41632e7e065317781b Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-23google mainboards: select SYSTEM_TYPE_LAPTOP where appropriateMatt DeVillier
Some Google boards are missing this selection, leading them to being incorrectly identified as type 'Desktop' in SMBIOS type 3 table. Correct this by adding 'select SYSTEM_TYPE_LAPTOP' to the boards' Kconfigs. TEST: boot Linux and check correct chassis type listed via dmidecode Change-Id: Ib1145e314812a3f300cfd1a435a687aa0862158a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-23src/mainboard: Fix various typosJonathan Neuschäfer
These typos were found through manual review and grep. Change-Id: Ia5a9acae4fbe2627017743106d9326a14c99a225 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-23google/fizz: Define smbios_mainboard_sku to return OEM IDsShelley Chen
Currently, mosys just returns "fizz" as model/chassis values. Returning proper OEM IDs so that mosys can return the proper variant. BUG=b:67732053 BRANCH=None TEST=mosys platform model; mosys platform chassis; Make sure returns the right variant string and not fizz. Change-Id: I42e293e833b0f7c9870dc275561ad13256836e60 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-22chromeec: Change the API for hostevent/wake masks to handle 64-bitFurquan Shaikh
ChromeEC is getting ready to bump up the hostevents and wake masks to 64-bits. The current commands to program hostevents/wake masks will still operate on 32-bits only. A new EC host command will be added to handle 64-bit hostevents/wake masks. In order to prevent individual callers in coreboot from worrying about 32-bit/64-bit, the same API provided by google/chromeec will be updated to accept 64-bit parameters and return 64-bit values. Internally, host command handlers will take care of masking these parameters/return values to appropriate 32-bit/64-bit values. BUG=b:69329196 Change-Id: If59f3f2b1a2aa5ce95883df3e72efc4a32de1190 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-22google/gru: Add support for rainierEge Mihmanli
Rainier is a scarlet-derived board but uses eDP as opposed to MIPI. Using GRU_BASEBOARD_SCARLET is enough, except for display related logic. In those cases, use board specific logic instead of baseboard. Change-Id: I596f7ca6bc26312ecaeb261c96cebd46974c2cdf Signed-off-by: Ege Mihmanli <egemih@google.com> Reviewed-on: https://review.coreboot.org/22542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-22Create SOC description file soc.aslRichard Spiegel
Request from commit 519680948b (move carrizo_fch.asl code to soc), merge several includes into a single file in soc directory. Rename soc_fch.asl to sb_fch.asl. Rename fch.asl to sb_pci0_fch.asl. Then copy the required section from dsdt.asl into a new soc.asl. Affected boards: amd/gardenia and google/kahlee. BUG=b:69368752 Change-Id: I83d850cf9457f7c2c787336823d993ae2e9d28ce Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22541 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-21mb/google: Update/add ChromeOS device marketing namesMatt DeVillier
Commit c09c2a4 [mb/google: Add Chromebook marketing names] added marketing names for many ChromeOS devices; add some that were left out, correct some errors, and try to format model names/numbers consistently (or as consistently as the manufacturers allow). Change-Id: Ia13858e2e6ba7d7e025f25fad33e6338250498e5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-20mainboard/google/fizz: Enable separate MRC cache for recovery modeShelley Chen
Enable separate MRC cache for recovery mode. This requires change in flash layout to accomodate another region for RECOVERY_MRC_CACHE. BUG=b:69473883 TEST=Verified following scenarios: 1. Boot into recovery does not destroy normal mode MRC cache. 2. Once recovery MRC cache is populated, all future boots in recovery mode re-use data from the cache. 3. Forcing recovery mode to retrain memory causes normal mode to retrain memory as well. Change-Id: Icdfac3698507d89d98a51cfc3d756a56d2a2d648 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-20google/gru: Add config for scarlet-derived boardsEge Mihmanli
There is merit in having new boards use the pinouts and controls in scarlet. This adds a config so new scarlet-derived boards can easily use scarlet structure without going through every file and adding new logic. TEST=Run "emerge-scarlet coreboot" Signed-off-by: egemih@chromium.org Change-Id: I5808f93f4563033ce93050e1eedb6eac2b52c3b3 Reviewed-on: https://review.coreboot.org/22517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-20amd/stoneyridge: Fix SPD files and functions camel caseMarc Jones
Remove ugly camel case in the soc/amd/common and Stoney Ridge SPD files and functions. Update the related mainboards. Also, remove a unreferenced function prototype, smbus_readSpd(). Change-Id: I51045b6621f0708d61a570acbdcb4e6522baa1ea Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19mb/google/kahlee: Move ec.h into variant include directoriesMartin Roth
The mainboard directory is included through the PI makefile - most mainboard directories aren't in the include path at all. Move the ec.h file into the baseboard/variant directory that is already in the include path. BUG=b:69220826 TEST=Build Change-Id: I89d361b700c66ba576de724927574fdab9461fc6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19mainboard/google/kahlee: Remove direct AGESA header includesMartin Roth
All AGESA headers should be included only through agesawrapper.h I missed this file in the Kahlee cleanup. BUG=b:66818758 TEST=Build gardenia; Build & boot kahlee Change-Id: Id9b303cb3cee8088fb5cca5257566c033d28c692 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19mainboard/google/kahlee: Update memory.cMartin Roth
This fixes some issues with the initial implementation that was copied from reef. - The board ID value shouldn't be size_t - it's not a size. - Kahlee doesn't even need the memory.c file - it uses an SoDIMM. BUG=b:68293392 TEST=build stoney platforms, boot kahleebo Change-Id: Ife5660d36912e887edfd0365a9f16c5a172c9c86 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22515 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-17mb/google: Add Chromebook marketing namesJonathan Neuschäfer
It's sometimes hard to find the code name of a Chromebook. Add the marketing names to Kconfig, since they are easily available. Information (mostly) taken from: https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices Unknown boards (unreleased, etc.): * Fizz * Foster * Nasher, Coral * Purin * Rotor * Rowan * Scarlet, Nefario * Soraka * Urara * Veyron_Rialto Baseboards: * Glados * Gru * Jecht * Kahlee * Nyan * Oak * Poppy * Rambi * Zoombini White label boards: * Enguarde * Heli * Relm, Wizpig TODO: How does this interact with the board_status code? Change-Id: I20a36e23bd3eea8c526a0b3b53cd676cebf9cd86 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-15variants/kahlee: Add thermal ASLMarc Jones
Connect the EC thermal to Kahlee and Grunt thermal ASL. Intialize GNVS thermal values in the mainboard finalize. BUG=b:67999819 Change-Id: I89159a5fd3c639e511139b8c5948b6a4ee19aaa3 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-15google/kahlee: Get power plug notification from the ECMarc Jones
Set the EC SCI reporting mask to include the power plug reporting. BUG=b:65637324 TEST=Check power_supply_info on AC/DC. Change-Id: I58814fc495081ffe8e47162da0fa4fbeba49d67b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-15mb/{amd/gardenia,google/kahlee}: move carrizo_fch.asl code to socRichard Spiegel
Code within carrizo_fch should be SOC specific instead of board specific. BUG=b:64034810 Change-Id: I5de2020411794bfcd3730789f62af9c9834a018b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22455 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-14mb/google/eve: Add DSP calibration clock name/rate for RT5514Cheng-Yi Chiang
Add a property for DSP calibration clock name and rate such that RT5514 codec driver can control ssp1_mclk for DSP clock calibration. BUG=b:67763576 TEST=boot on eve check RT5514 codec driver can get this device property. Change-Id: Icf9695ef67efb2bb073e39b2ece02d57f0460a0c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Original-Change-Id: Ie204dda81a099f23beb20be71380a8494a9bee31 Original-Reviewed-on: https://chromium-review.googlesource.com/756261 Original-Reviewed-by: Dylan Reid <dgreid@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Set DSP SPI clock to 12MHzDuncan Laurie
To enable faster download of hotword data set the SPI clock to the Realtek 5514 DSP chip to 12MHz instead of the default 1MHz. BUG=b:67763576, b:66161281 TEST=cras_test_client --listen /tmp/rec.raw, trigger hotword, and check the samples using hexdump or cras_test_client --playback_f /tmp/rec.raw Change-Id: I92710eae25613a8202c63888b86a269803c40fe6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Original-Change-Id: I7e50d755a90d739b6dec155228351c3974b2f3b9 Original-Reviewed-on: https://chromium-review.googlesource.com/686675 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Chinyue Chen <chinyue@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Chinyue Chen <chinyue@chromium.org> Original-Commit-Queue: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Enable VMXDuncan Laurie
This feature was enabled at the kernel level, but that is triggering an issue where FSP expects it to be disabled so it forces a cold reboot on every warm reboot. Since we want this enabled anyway just set it this way in the BIOS so it matches what the kernel expects. BUG=b:68666100 TEST=pass firmware_FWtries on Eve with R63 OS image Change-Id: I294e34d25406365d591da06ce4c931b710cfbbaa Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: I964d3d30392d130e808f37a661f2c89ec926cf58 Original-Signed-off-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/749733 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Tune I2C4 hold timesDuncan Laurie
Tune PCH I2C4 hold times to ensure the frequency is always <400KHz. BUG=b:67029862 TEST=boot on eve and measure I2C4 at Tp262 to be 385KHz Change-Id: Ie93c5c40bc74069b285f6c3ee311f1bd7cefcaf1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: Iceabc806a17b9e6a144a4f6288c6cca790d03950 Original-Signed-off-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/739841 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Enable AER and LTRFurquan Shaikh
AER and LTR must be enabled individually on ports that need it, in this case it should be enabled for WiFi and NVMe. BUG=b:65457528 TEST=Wifi team verified that the performance is better with these changes. Change-Id: I0d688fe07a1f3117c1ca617c2ce78e0d024a3510 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: Ib059517fa782ccc18ba5ef1f76058a1898b7bf7a Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/671211 Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Commit-Queue: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Use rt5663 driver and set propertiesDuncan Laurie
Use the rt5663 driver and provide values for the offsets which are needed for providing manual values to compensate the DC offset for L and R channels between headphone and headset. BUG=b:62712227 TEST=build and boot on eve and ensure rt5663 is functional. Change-Id: I88113616e4b7c79cff840168b7c54ae754dfa75f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: Ica4090636c1ff29f0298114e62c9cc6fe167a425 Original-Signed-off-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/611606 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Hsinyu Chao <hychao@chromium.org> Reviewed-on: https://review.coreboot.org/22446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Remove ACPI control of touchscreen powerDuncan Laurie
Change the touchscreen power control back to coreboot instead of under the ACPI _ON/_OFF methods, and switch the TOUCHSCREEN_STOP_L pin back to an output. This reverts previous changes to touchscreen GPIOs that were made to get back to a known good/working state. Having ACPI control these pins was resulting in a small percentage of touchscreen not being discovered at boot. This platform is not intending to use S0ix so the ACPI control is not needed. BUG=b:63718744 TEST=manual testing on Eve devices. Change-Id: I3fd64a435a053da1558ef736fe7baceee3c8f3a0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: Ia1e2ae7ca2a8b668c60fbda2aa50373e580646b2 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/572692 Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Commit-Queue: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22445 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/kahlee: Remove direct AGESA header includesMartin Roth
All Stoney AGESA headers should be included only through agesawrapper.h BUG=b:66818758 TEST=Build and boot tested Change-Id: I642f5caf8a37ae4042c32fec3a92e0995193cb7a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13mb/google/kahlee: Add getter function for GPIO arrayMartin Roth
Instead of getting the address of the GPIO function with an extern, add a getter function and make the GPIO arrays static. TEST=Build Grunt; Build & boot Kahlee BUG=b:69164070 Change-Id: I3defcb66696459b915d7d4f43234d5c08ab7d417 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13mb/google/kahlee: Remove mainboard.hMartin Roth
mainboard.h only had a single function definition. Move it into baseboard/variants.h and get rid of the file. TEST=Build grunt/kahlee BUG=b:69164070 Change-Id: I6b7d50d5c949733d77c42b4daf56ed1f97ed6954 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13mainboard/google/kahlee: Add Grunt variant frameworkMartin Roth
Update common files and add files for grunt to the variant directory. BUG=b:68293392 TEST=Build only Change-Id: I7b80e470058872d6613e66e64c8dd1494942e9b9 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13mainboard/google/kahlee: Add baseboard frameworkMartin Roth
BUG=b:68293392 TEST=Build only Change-Id: Ie4d039b4da10a992fc9dd2b0221fd4a1644aae6a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13google/chell: add missing SPD hex filesMatt DeVillier
Several SPD hex files for chell were missing from upstream coreboot (as compared to the Chromium tree/branch), which resulted in the incorrect type and amount of RAM being reported on chell boards with > 4GB RAM. Add these missing files and their Makefile entries. TEST: boot google/chell m7/16GB config and observe correct RAM type and amount reported via dmidecode and cbmem console log. Change-Id: I37d708c96e754b438e40fc413420aa64bf234c29 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22402 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-10google/kahlee: Use devicetree register values for UMAMarshall Dawson
Set the UMA memory size to 128 MiB. This value was empirically tested by AMD as the lowest value one could use. BUG=b:64927639 TEST=default, and 64, 128, 256, 384MB non-legacy configurations. Change-Id: I2bc808d8b402c3eb16a1a5962f3fa9d6b224cf52 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21335 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-10google/kahlee: Add defines in OemCustomize.cMarshall Dawson
Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max supported for the device. AGESA's DRAM procedures follow the BKDG and may vary depending on the number of slots on the motherboard. DIMM numbering and ordering is also affected by this value. Replace hardcoded integers with defined values for DIMM slots and number of channels. Change-Id: I4f7336da80b4e3d7f351502a63de0652e9ff5395 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21853 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-10google/kahlee: Move DRAM clear override to devicetreeMarshall Dawson
Kahlee needs to keep its DRAM contents after a reset. Move this override out of the OemCustomize.c file to a devicetree register setting. Change-Id: I3196cb8b94bec64e8ce59e4285cf8d97f442bd3d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21858 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-10mainboard/google/coral: power off EN_PP3300_DX_LTE_SOC when entering S5Ben Chan
On Astronaunt, after the system enters the S5 power state, there is a 10-second timeout before the system transitions the power state from S5 to G3. The EN_PP3300_DX_LTE_SOC signal, which is controlled by GPIO_78 on the APL platform, remains on during that period. If the system is powered back on before going to G3, the built-in modem won't go through a power cycle as EN_PP3300_DX_LTE_SOC is never de-asserted. Keeping the modem, and indirectly the SIM, powered during a quick system power cycle may sometimes be undesirable. For instance, we would like a SIM with PIN lock enabled to require unlocking each time the system is powered on. After the SIM receives a PIN, it may remain unlocked until its next power cycle. Also, it is often desirable to power cycle the modem when the system goes through a power cycle. For instance, a user may power cycle the system to recover a wedged modem. BUG=b:68365029 TEST=Tested the following on an Astronaunt device: 1. Verify that the modem is powered on after the system boots from cold. 2. Suspend the system to S0ix. Verify that the modem remains powered on when the system is in S0ix. After the system goes back to S0, verify that the SIM with PIN lock enabled doesn't request unlocking, and the modem can quickly reconnect to a network. 3. Configure the system to suspend to S3 instead of S0ix, and then repeat (2). 4. Perform a quick system power cycle, verify that the modem is powered cycle and the SIM with PIN lock enabled requests unlocking. Change-Id: Ie60776d5d9ebc6a69aa9e360bd882f455265dfa2 Signed-off-by: Ben Chan <benchan@chromium.org> Reviewed-on: https://review.coreboot.org/22415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-09mainboard/google/zoombini: add dptf.asl and gpio.hNick Vaccaro
Add dptf.asl (copied from reef) to baseboard variant includes, instruct zoombini variant to use the baseboard's dptf.asl, instruct zoombini variant to use the baseboard's gpio.h. BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I9aa37f5afc35dab372917a4c84ff3121ec569546 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/22381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-09mainboard/google/zoombini: fix EC_SCI_GPI gpio defineNick Vaccaro
Change EC_SCI_GPI to GPE0_ESPI. BUG=b:69011806 BRANCH=master TEST=none Change-Id: I5d07bc0ef295d776635ff3a585c8de9028bd3f6a Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/22380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09mb/google/{poppy,nautilus,soraka}: Disable deep S3Furquan Shaikh
Poppy and variants won't be using deep S3. This change disables deep S3 option in devicetree. BUG=b:69053636 Change-Id: I5fb4a6a0e4216a3648b5ed888f6dc6618f1a9fc4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22378 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09mb/google/fizz: Enable NIC ledsGaggery Tsai
This patch enables customized NIC leds as follows: Green Orange (Amber) 100M off blinking 1000M on blinking BUG=b:65437780, b:68284778 TEST=Make sure the registers are programmed as expected and observe the LEDs are behaving as expected. Perform suspend/resume test and the LEDs are still working as expected. Change-Id: I9bb1367a4c742c2755d620e14ee6dfe70ee7f34b Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/22293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-09mainboard/google/kahlee: Move usb_oc.asl into variant/acpiMartin Roth
This compares to the acpi directory in other variants. BUG=b:68293392 TEST=Build and boot kahlee Change-Id: I05d402995b280d6f020bc2575063dbffefa30670 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09mainboard/google/kahlee: Define MEM_CONFIG3 for Kahlee variantMartin Roth
Even though this GPIO isn't used for Kahlee, it needs to be defined so that the weak version of the variant_board_id() function can compile. BUG=b:68293392 TEST=Build and boot kahlee Change-Id: Ia8daf70fbafe02ec37c6b5eb8421cdb11de3be8b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08google/fizz: add VBOOT_PHYSICAL_REC_SWITCH configShelley Chen
Now that recovery button has been enabled through cr50, we can add VBOOT_PHYSICAL_REC_SWITCH config and treat the recovery button like on any other chromebox. BUG=b:37751915, b:63893483 BRANCH=None TEST=With DUT in normal mode, boot into recovery, press ctrl+d followed by pressing the recovery button. Should successfully boot into dev mode. CQ-DEPEND=CL:737477 Change-Id: I72fb42508083295e317dd06900796dc0cda753f6 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22368 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-07mb/google/poppy/variants/nautilus: Enable Dialog DA7219 supportNaveen Manohar
Enable Dialog DA7219 codec i2c device and add required SSDT parameters BUG=b:68686020 TEST=With req'd driver support in kernel v4.4 verify audio on headset Change-Id: Ic815c929f29bec0d26a2981e9933b752c2d84c70 Signed-off-by: Naveen Manohar <naveen.m@intel.com> Signed-off-by: Shruthi Sudhakar <shruthi.sudhakar@intel.com> Reviewed-on: https://review.coreboot.org/22264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-07mb/google/poppy/variants/nautilus: add nhlt supportNaveen Manohar
Nautilus board uses Dialog da7219 headset codec, Select the appropriate NHLT blob to be packaged in CBFS. Also generate the required ACPI NHLT table for codec and the supported topology in nautilus. Removes unwanted DMIC blob pick for nautilus BUG=b:68686020 TEST=With the required driver support in kernel verify that the Audio plays on headset and recording on headset mic Change-Id: I104889f54da1de38854bcb72aabbc88b739d6c09 Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/22325 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-07mainboard/google/kahlee: Add MAINBOARD_FAMILYLann Martin
BUG=b:68865273 Change-Id: Ia2e9b10035e9dd502a563cdf8324ea8ea1922db3 Signed-off-by: Lann Martin <lannm@chromium.org> Reviewed-on: https://review.coreboot.org/22359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-06gru: Fix and export SPK_PA_EN GPIO for ScarletJulius Werner
On older Grus, GPIO0_A2 was an audio voltage rail enable line. On Scarlet, we instead moved the audio codec enable (previously on GPIO1_A2) there. Unfortunately the code still had some hardcoded leftovers that were overlooked in the initial port and make our speakers smell weird. This patch fixes the incorrect GPIO settings and adds the speaker enable pin to the GPIOs passed through the coreboot table, so that depthcharge doesn't have to keep its own definition of the pin which may go out of sync. Change-Id: I1ac70ee47ebf04b8b92ff17a46cbf5d839421a61 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Alexandru Stan <amstan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-06mainboard/google/coral: Override VBT selection for astronautren kuo
Current VBT setting for T8 is only 1ms which is under Innolux N116BCA-EA1 panel's spec. Modify T8 to 100ms. (Innolux's panel's spec requires T8 needs to be greater than 80ms) CQ-DEPEND=CL:*496012 BUG=b:67756548 BRANCH=master TEST=emerge-coral depthcharge coreboot chromeos-bootimage Run on DUT and check panel sequence meets spec. Change-Id: I580567decfccd78366c37181255015ac2cd76493 Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/22306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quantatw.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-04mainboard/google/kahlee: remove unused FILECODE macroAaron Durbin
From what I can tell FILECODE isn't used at all in this file. Remove it. Change-Id: Ie88140e63a4917f470f42119c1fe4e8c7d2584ca Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-03soraka: update pad reset config of WLAN_PE_RST to RSMRSTDivya Chellap
In skylake based platforms, setting GPIO pad reset config to DEEP will reset the gpio configuration across warm reset, set it to RSMRST to preserve the configuration across warm resets. Also, moving the configuration from early to late as appropriate. BUG=b:64386481 BRANCH=none TEST= WiFi functionality across S3, DeepS3, S0ix and warm/cold reboot. Change-Id: I38940b7c7d71e60bf0e51d6978a00be148ad61bc Signed-off-by: Divya Chellap <divya.chellappa@intel.com> Reviewed-on: https://review.coreboot.org/22174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-03google/reks: override USB2 Phy settings on BSW D-Stepping SOCMatt DeVillier
Adapted from Chromium commit 12ad5b5: Reks : override USB2 Phy settings... Base on Intel recommendation, override following settings for USB2 port 1/2/3 on BSW D-stepping SOC. 1. Set USB[1] register for right side to 7321 2. Set USB[2] register for left side to 7021 3. Set USB[3] register for CCD to 7021 Original-Change-Id: I04240a010e875f29c47f4fea83ff918f180b0273 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Change-Id: Iabd6312576e9897315c4e4dbf19341380d9d1414 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03google/reks: override RX ODT limit, RAM geometry if neededMatt DeVillier
Adapted from Chromium commit 6ee6f3d: Reks: To set the RX ODT limit... Override RX ODT and DRAM geometry for Micron part MT52L256M32D1PF-107. Use get_ramid() to determine if override is necessary. Original-Change-Id: I41f3aba030a00152e1217533ef953338ac396605 Original-Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Original-Reviewed-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Change-Id: Iea8c3c67e5afb21285dc15ad665474ad5f192423 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03google/kahlee/acpi: Serialize method _CRSPaul Menzel
ASL+ Optimizing Compiler/Disassembler version 20170831 shows the remark below. ``` dsdt.aml 87: Method (_CRS, 0x0, NotSerialized) Remark 2120 - ^ Control Method should be made Serialized \ (due to creation of named objects within) ``` So, serialize the method. Fixes: commit 4a51ea8470 (google/kahlee: Add ASL for Elan touchpad) Change-Id: I664f493318cbfd80d91565c0d29ec918278c4906 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/21901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-03mainboard/google/kahlee: Prepare for variantsMartin Roth
Move files that are particularly specific to the mainboard into the variant directory. Files that only have small areas of mainboard specific pieces use #if to separate between the boards. Add memory.c to split out the variant board id into a weak function. Add baseboard/gpio.h to satisfy the build - this will be updated in the next commit. BUG=b:68293392 Change-Id: I7c1beb45f571f2547f3b5b0d7ec78923d0cec761 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03google/nautilus: enable elan touchpad supportChris Wang
add elan touchpad in devicetree. BRANCH=master BUG=b:66462881 TEST=emerge-nautilus coreboot Change-Id: I30e6797ef06351690ff0b5c78ea76918547167a7 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: shkim <sh_.kim@samsung.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-03google/nautilus: Update GPIO tableChris Wang
Update GPIO settings to meet nautilus's schematic design. BRANCH=master BUG=b:66462881 TEST=emerge-nautilus coreboot Change-Id: I11930df62130431764702371a3ba84949a65ba30 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: shkim <sh_.kim@samsung.com>
2017-11-03google/nautilus: add spd data by ram idChris Wang
update with nautilus memory spds. RAM_ID = 0 => K4E8E324EB-EGCF RAM_ID = 1 => K4E6E304EB-EGCF RAM_ID = 2 => K4EBE304EB-EGCG BRANCH=master BUG=b:66462881 TEST=emerge-nautilus coreboot Change-Id: I29d8a76b170aee64bb0125276df0e4709012daba Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: shkim <sh_.kim@samsung.com>
2017-11-02mainboard/google/coral: Override VBT selection for santaTim Chen
Current VBT setting for T8 is only 1ms which is under Innolux N116BCA-EA1 panel's spec. Modify T8 to 100ms. (Innolux's panel's spec requires T8 needs to be greater than 80ms) BUG=b:67756548 BRANCH=master TEST=emerge-coral depthcharge coreboot chromeos-bootimage Run on DUT and check panel sequence meets spec. CQ-DEPEND=CL:*493633 Change-Id: I7934b0f6d40b15796c55d360995c5eb0c5049222 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/22294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01google/fizz: enable SPD read by wordKane Chen
This is to enable SPD word access to reduce boot time. It can save 80 ~ 100 ms per DIMM. BUG=b:67021853 BRANCH=None TEST=system boot, and boot time is reduced Change-Id: Ic527a539ed634e15b939b18fff4b4e08ebb3ec57 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/22267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01mainboard/google/coral: Update touchscreen device ACPI nodesSheng-Liang Pan
For Raydium, export reset GPIO as well as PowerResource. Let EN_PP3300_TOUCHSCREEN signal will goes to low at S3 mode. BUG=b:67879912 BRANCH=coral TEST=emerge-coral coreboot Change-Id: Ibf501b40ecfc957fd8be7ebffd2357dfa0e07757 Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com> Reviewed-on: https://review.coreboot.org/22252 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-31mainboard/google/snappy: Update touchscreen device ACPI nodesKevin Chiu
For MELFAS/Raydium, export reset GPIO as well as PowerResource BUG=b:68141940 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I1915ff8207502b80ecba6b63ce2ce1b866faf4c4 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/22146 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-28mainboard/google/Kahlee: Combine BiosCallOuts filesMartin Roth
There's no need to have these separated. BUG=b:64932381 Test=Build & Boot Change-Id: I22898d3bf95d5e9a8fc2643bfccae1e2f5b29e44 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-23mainboard/google/coral: Add USB2 phy setting override for Astronautren kuo
In order to pass type C USB2 eye diagram for sku Astronaut, USB2 port#1 PHY register needs to be overridden. sku ID:0,1 Astronaut (USB) port#1: PERPORTPETXISET = 7 PERPORTTXISET = 2 sku ID:61,62 Astronaut (LTE) port#1: PERPORTPETXISET = 7 PERPORTTXISET = 5 BUG=b:68120012 BRANCH=master TEST=emerge-coral coreboot chromeos-bootimage Change-Id: Icf5c9e5f4dae15630ec4d6ca6648cae78ca910c6 Signed-off-by: Ren Kuo <ren.kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/22135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22google/kahlee: Add PSP to devicetree.cbMarshall Dawson
Add the missing device and ensure it shows up in the devicetree prior to PCI enumeration. Change-Id: Ia2c4ba1200422b36c533e86065a4fcd10c4b2722 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22055 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-22mb/google/link: Enable libgfxinitNico Huber
Beside the high-resolution eDP panel, it features a dual-mode mini-DP port. Change-Id: Iae60c1f930f5778ee3b5d9d19227168257e9ae06 Tested-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-10-20kahlee: Set Kahlee GPEsMarc Jones
Add GPE configuration table. Remove GPE3 from the power button ASL and set the EC to GPE3(AGPIO22). Set the EC and PCIE/WLAN SCI GPIO signals. Set GPE ASL methods for: PCIE/WLAN 8h EHCI 18h XHCI 1fh Note EC GPE3 methods are in the EC ASL. BUG=b:63268311 BRANCH=none TEST=Test lidswitch powers the device on and off at the login screen. Change-Id: I27c880ee84b6797d999d4d5951602b654ede948e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22096 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-20google/fizz: Set PL2 value based on sku id/charge max powerShelley Chen
Set PL2 based on either 90% of usb c charger's max power or sku id if using a barrel jack. BUG=b:37473486 BRANCH=None TEST=output debug info for different skus and make sure PL2 set correctly. Change-Id: I487fce4a5d0825a26488e71dee02400dbebbffb3 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/21772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20stoneyridge: Fix USB ASLMarc Jones
Stoney Ridge has one EHCI controller and one XHCI controller. Also, update the Kahlee and Gardenia mainboards ASL to match. Change-Id: I5749ca0640796732e74e551147f8c4446317b77e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20Stoney Ridge Platforms: cast AGESA tables to void *Martin Roth
In the original AGESA headers, these tables are not defined as const. Cast them to void * so that they'll work with either version of the headers. BUG=b:64766233 TEST=Build in cros tree and upstream coreboot, with old headers and updated headers. Change-Id: I75387b57caf5a3c6c25655120aafd942254b5c73 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22059 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-20Stoney Ridge Platforms: Make AGESA callout tables commonMartin Roth
There was no reason to have the AGESA callout tables in each mainboard, so move them to soc/amd/common. Move chip specific functions into the stoneyridge directory: - agesa_fch_initreset - agesa_fch_initenv - agesa_ReadSpd Combine agesa_ReadSpd and agesa_ReadSpd_from_cbfs, and figure out which to use. Soldered-down memory still needs to be supported in a future commit, as stoney supports both DDR3 & DDR4. A bug has been filed for support for the upcoming Grunt platform. BUG=b:67209686 TEST=Build and boot on Kahlee Change-Id: Ife9bd90be9eb0ce0a7ce41d75cfef979b11e640b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-19mb/google/poppy: Log EC events during S0ix resumeFurquan Shaikh
This change adds support for logging EC events during S0ix resume. BUG=b:67874513 TEST=Verified that EC events are correctly logged during S0ix resume: 284 | 2017-10-16 20:45:12 | S0ix Enter 285 | 2017-10-16 20:45:16 | S0ix Exit 286 | 2017-10-16 20:45:16 | Wake Source | Power Button | 0 287 | 2017-10-16 20:45:16 | EC Event | Power Button 288 | 2017-10-16 20:45:35 | S0ix Enter 289 | 2017-10-16 20:45:40 | S0ix Exit 290 | 2017-10-16 20:45:40 | Wake Source | GPIO | 112 291 | 2017-10-16 20:45:40 | EC Event | Lid Open 292 | 2017-10-16 20:50:51 | S0ix Enter 293 | 2017-10-16 20:50:59 | S0ix Exit 294 | 2017-10-16 20:50:59 | Wake Source | GPIO | 112 295 | 2017-10-16 20:50:59 | EC Event | Mode change Change-Id: I9f6dcb8852d94ebf90bb5b63a17fde524d58d49f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18google/snappy: Override USB2 strength by SKUIDKevin Chiu
14" BigDaddy needs to override USB2 TxiSet additionally to enhance driving strength. Otherwise EA test will fail on USB2 eye pattern. BUG=b:67820719 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I674c121a71866a5d44439eeb49e07f917d816de8 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/22037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18mb/google/fizz: skip reading SPD data when DUT resumes from S3Gaggery Tsai
This patch skips SPD data reading when system resumes from S3 since MRC cahce is adopted and validated in fsp_memory_init. BUG=b:67021596 TEST=Run suspend/resume on Fizz and make sure the systems are working well when system resumes from S3. Checked dmidecode information and SMBIOS type 17 data is the same with cold boot. Change-Id: I1692fca8456290d1471973b746537b5fec504e03 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/21987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16google/reef: Add more special cases for coral nasherPatrick Georgi
BUG=b:65386429 BRANCH=none TEST=panel lights up Change-Id: I9871969314b9b64bee2b20332e35bfc6fbd2ddda Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/22002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-16src/mainboard/google/kahlee: Remove legacy tablesRichard Spiegel
Remove IRQ and MP tables. Modern OS use ACPI instead of legacy tables. Use Kconfig for reversable configuration if using old OS. BUG=b:62241143 Change-Id: I5fc833c8af47b5f6fad757e129250e6202810dbb Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-16mb/google/fizz: enable AER for PCIe root portsKane Chen
Enable PCIe Advanced Error Reporting for PCIe root port 2, 3, 4 ,8. BUG=b:64798078 TEST="lspci" shows that AER is enabled in the capabilities list. Change-Id: I6438250d674e7d06cdecd8f25fadebca1973721e Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/21946 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16src/mainboard/kahlee: Default AMD FW position to 1MBMartin Roth
For Kahlee, the AMD firmware directory should be in the 1MB location so that it's in the RO cbfs section. BUG=b:65484600 TEST=Build & boot Change-Id: I650d8bc0bfa773f5fb5dc11167fe3db3b9550b68 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22003 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-15google/kahlee: Add SMI sleep handlerMarshall Dawson
Notify the EC the system is going to sleep. Change-Id: I025e268a4f806d827348d91effff43a6a339a148 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-15google/kahlee: Add SMI apmc handlerMarshall Dawson
Forward the apmc call to the chromeec. Change-Id: Id724c1abf15617ad1ba28f2c0247455b014c1867 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-15google/wizpig: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/wizpig (white label Chromebook) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new wizpig variant - Add new shared SPD file to the baseboard Sourced from Chromium branch firmware-strago-7287.B, commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF) Change-Id: I424d2256eb79ca3ea0a62620954c57c09ae0c0b2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15google/ultima: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/ultima (Lenovo Yoga 11e G3) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new ultima variant Sourced from Chromium branch firmware-ultima-7287.131.B, commit 3ef9e73: Revert "Revert "soc/intel/braswell: Put SERIRQ in quiet mode"" Change-Id: Ib38b110f50f4d6ae6eda40e787cd3c1c8dd5ece7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-10-15google/setzer: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/setzer (HP Chromebook 11 G5) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new setzer variant - Add new I2C touchscreen device and SPD files to the baseboard for potential reuse by other variants Sourced from Chromium branch firmware-strago-7287.B, commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF) Change-Id: Ibcebebeb469c4bd6139b8ce83a1ca5ca560c2252 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-13google/kahlee: Add AGESA_DO_RESET in bootblockMarc Jones
Support the required AGESA_DO_RESET in bootblock. BUG=b:64719937 BRANCH=none TEST=Check AGESA reset request in booblock does a reset in the serial console or ec console. Change-Id: I462a1f81b8d209c15417946a314f2bfb9b226e4d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-13google/fizz: Enable cr50 over SPIShelley Chen
We are changing the bootstraps in the EVTs so that the SOC communicates with cr50 over SPI instead of cr50. SPI is more reliable than I2C. Thus, disabling cr50 over I2C and enabling cr50 over SPI. BUG=b:65056998, b:62456589 BRANCH=None TEST=make sure that we can boot into kernel run cold_reset and warm_reset and make sure both boot successfully. CQ-DEPEND=CL:714237 Change-Id: I85b9a61f0305e3c7ccada79d7702234a285a6d2a Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/21970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-13google/relm: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/relm (white label Chromebook) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new relm variant - Add new shared SPD files to baseboard Sourced from Chromium branch firmware-strago-7287.B, commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF) Change-Id: Ife10f5f75435f356cd896588dd6f425e54f3c88e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-10-13google/kefka: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/kefka (Dell Chromebook 11 3180) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new kefka variant - Add new shared SPD file to baseboard Sourced from Chromium branch firmware-strago-7287.B, commit ef41a46: Kefka: Modify USB2 settings to match the eye diagram Change-Id: Ic6c8c5e5b6029bb99039c64b0182214e93552fa2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-13google/cyan variants: fix non-functional typo in gpio.cMatt DeVillier
Typo found/fixed in to-be-merged boards; applying same fix to already-merged boards. Change-Id: I15f97467a5442888165399be997b0b690a3c312a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-13google/cyan variants: fix single/dual channel reportingMatt DeVillier
Fix typos in determining single/dual channel in cyan variants which resulted in all boards being reported as 4GB/dual channel in the cbmem console log. These typos were found and fixed in yet-to-be-merged variants; this patch applies the same fixes to already-merged boards. Change-Id: I615463668e77bd817d5270f0f04d4d01f74e3b47 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-11mainboard/google/kahlee: Add EC_IN_RW flagMartin Roth
Depthcharge was complaining that the GPIO for this flag wasn't set. The GPIO also needs to be an input, not an output. BUG=b:67614692 TEST=Depthcharge no longer complains that there is no GPIO set for flag5. The system boots again. Change-Id: Ib854e97b0a3aa42a95ceb8a42a9776f0345ff8b1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-11mainboard/google/fizz: Enable Devslp for SATA port 1Gaggery Tsai
This patch is to enable the support of device sleep for SATA port 1 and disable unused SATA port 0. BUG=b:65808359 BRANCH=None TEST=Ran "suspend_stress_test -c 2500" and passed the test. Change-Id: I33b8f5fd0c51d83e154ef7daac3274ff377bc8b3 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/21765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Shelley Chen <shchen@google.com>
2017-10-10mb/google/poppy/variants/nautilus: add nautilus boardChris Wang
Create Nautilus board which derives from Poppy, a KBL reference board. BRANCH=master BUG=b:66462881 TEST=Build (as initial setup) Change-Id: I6ca5ab821a7ba1746b37dfd3ea1ed367094d4f52 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/21895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 01:46:21 +0000