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Add Cirque Touchpad devicetree configuration to export relevant ACPI
objects to the kernel.
BUG=b:141259109
BRANCH=sarien
TEST=Boot to ChromeOS. Ensure that relevant ACPI objects are exported in
the SSDT.
Change-Id: I91dcb27b86c6a2bed5579f1f6c1102871d55b315
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change removes an inversion of GPP_D17 that caused the
device to get stuck in a reboot loop because the kernel was crashing
within the first couple seconds of kernel boot.
BUG=b:142515200
BRANCH=none
TEST=Flash and boot nocturne, verify boot is stable and that device
doesn't reboot after jumping into kernel, and that it passes the
'tast -verbose run <ip> hardware.SensorRing' test.
Change-Id: Ia1408ef6ea92f6b31a9f3eee8720954af3a7c382
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35967
Reviewed-by: Yicheng Li <yichengli@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:142987639
TEST=emerge-hatch coreboot
Change-Id: I0ff1a81d0579d0b328a48bc7d4f867592ec63e8b
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I46d131f76ec930d2ef0f74e6eaabae067df10754
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I3d90e46ed391ce323436750c866a0afc3879e2e6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36359
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This drops support for FSP 1.1 in soc/intel/skylake, after all boards
have been migrated to FSP 2.0, which is backwards compatible.
Any moving of files happens in a follow-up commit to make review easier.
Change-Id: I0dd2eab0edfda0545ff94c3908b8574d5ad830bd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35813
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic2f0944b92dcad7048a0c38720d2ef3c855ef007
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Change-Id: I50cafce0aaf465ee95562ccff6c8f63fb22096c0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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mainboard_silicon_init_params() is supposed to be used for only
overriding any FSP params as per mainboard configuration. GPIOs should
be configured by mainboard as part of its chip init(). This ensures
proper ordering w.r.t. any common operations that the SoC code might
want to perform e.g. snapshot ITSS polarities.
This change moves the configuration of GPIOs from
mainboard_silicon_init_params() to mainboard chip->init().
Change-Id: I5d10c01c5b9d5f8ed02274d51dcf9c2a17269685
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36270
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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mainboard_silicon_init_params() is supposed to be used for only
overriding any FSP params as per mainboard configuration. GPIOs should
be configured by mainboard as part of its chip init(). This ensures
proper ordering w.r.t. any common operations that the SoC code might
want to perform e.g. snapshot ITSS polarities.
This change moves the configuration of GPIOs from
mainboard_silicon_init_params() to mainboard chip->init().
Change-Id: I5cd89c6e24b6a4b0c20fd476915f3781a0d46e0d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36269
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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mainboard_silicon_init_params() is supposed to be used for only
overriding any FSP params as per mainboard configuration. GPIOs should
be configured by mainboard as part of its chip init(). This ensures
proper ordering w.r.t. any common operations that the SoC code might
want to perform e.g. snapshot ITSS polarities.
This change moves the configuration of GPIOs from
mainboard_silicon_init_params() to mainboard chip->init().
Change-Id: Ied0201b954894acd3503801e7739b91a2cc9b4a8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36268
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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mainboard_silicon_init_params() is supposed to be used for only
overriding any FSP params as per mainboard configuration. GPIOs should
be configured by mainboard as part of its chip init(). This ensures
proper ordering w.r.t. any common operations that the SoC code might
want to perform e.g. snapshot ITSS polarities.
This change moves the configuration of GPIOs from
mainboard_silicon_init_params() to mainboard
chip->init(). Additionally, this change moves mainboard_ec_init() to
mainboard dev->init().
TEST=Verified that GPIOs are configured properly and hatch boots to
OS.
Change-Id: Ia509471a3678c60454cd4f14625f151860d9b9d2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36267
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set VPD keys for DSM parameters in overridetree.cb for Helios.
RT1011 driver will load values from VPD and set them to device property.
BUG=b:140397934
BRANCH=none
TEST=On Helios, with patch series, check realtek,r0_calib and
realtek,temperature_calib are available to rt1011 codec driver.
Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Change-Id: Ic72fd57becf93e70a1a716dbb76633509f2fd5c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The correct mapping for speakers to their names should be:
uid 0: Woofer Left
uid 1: Woofer Right
uid 2: Tweeter Left
uid 3: Tweeter Right
Also, fix the name to be 4-character.
BUG=b:140397934, b:143192767
BRANCH=none
TEST=On Helios, with patch series, check realtek,r0_calib and
realtek,temperature_calib are available to rt1011 codec driver.
And the speaker mapping is correct.
Change-Id: I353fb9ad0ca8ec85431eb2b59be748b4887278cf
Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36256
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add thermal sensor: TSR2 to ACPI table, monitor CPU temperature
BUG=b:143046086
TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec
chromeos-bootimage
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Id150c5c3cb6d07407fd20417237457b5722e6f2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Philip Chen <philipchen@google.com>
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Add enum for Vorticon sku.
Vortininja/Vorticon will load vbt_vortininja.bin
Dorp will load vbt_dorp.bin
BUG=b:143197918
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
check i915_drrs_status shows DRRS supported NO
when SKU-ID sets to Dorp/Vortininja/Vorticon.
Change-Id: I67d7a8ab62a1838b0a0a05f532d8b067ece686d9
Cq-Depend: chrome-internal:2026287
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Found-by: ACPICA 20191018
Change-Id: I8bcdfa7a4dc33c3e3866d3135249a602379b9615
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36265
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use RT1011 driver for Helios. Select CHROMEOS_DSM_CALIB to set device
properties for RT1011 speaker calibration.
BUG=b:140397934
BRANCH=none
TEST=On Helios, with patch series, check realtek,r0_calib and
realtek,temperature_calib are available to rt1011 codec driver.
Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Change-Id: I1010be15466c5060aa1d73318393853a2515daac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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On hatch and variant HW designs supports VCCPRIM_CORE Low Voltage Mode.
VCCPRIM_CORE can be down to 0.75v when slp_s0 is asserted.
This commit enables PchPmSlpS0Vm075VSupport UPD so that FSP can
program related setttings to save power.
BUG=b:134092071
TEST=Run suspend_stress_test on kohaku and pass 100 cycles
Change-Id: Ia02ff8823883489b36349457213409496f082f36
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Correct ICC_MAX values per SKL-Y EDS spec.
Adapted from chromium commit 1c4e89e8 [Chell: Update ICC_MAX configuration]
Original-Change-Id: Ic660cc6a2d11e995a86a30ddde800d096d93e012
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/593715
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ia31ce432cf979d574d84e9205a287f87de5de057
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Michael Niewöhner
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Change GPP_B21 default to low. This can prevent power leakage
of non-touch sku.
BUG=b:142849034
BRANCH=N/A
TEST=Measure the power of non-touch sku, check GPP_B21 is 0V.
Boot up with touch sku and check touch functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I80a3e5dc224e4dab97c21fd469d8c3f2d3e774e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
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Configure enable pin GPP_D9 pull high when active
BUG=b:143046441
TEST=build bios and verify touch screen works fine
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I83060f31d4d22c9be05bba119816c6aa66e4126c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36186
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Share the same vbt_blooguard.bin to disalbe DRRS support.
BUG=b:143045247
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
check i915_drrs_status shows DRRS supported NO when SKU ID is blooglet.
Change-Id: Ia180f265080f801a09f10ce8a8b520c47f218775
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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This patch is part of the patch series to drop support for FSP 1.1 in
soc/intel/skylake.
The following modifications have been done to migrate the board(s) from
FSP 1.1 to FSP 2.0:
- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0)
- switch to using the FSP default VBT
TODO:
- testing
Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I0c965e598e260ff8129aa07fb9fc5bf6e784e1d8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add ELAN EKTH6915 USI touchsreen support.
BUG=b:139392144
TEST=check touchscreen work, and confirmed power sequence with vendor.
Change-Id: I8ebc067bbb407498de00ea0b6c23b0848023cffe
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36125
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add data.vbt and modify Kconfig appropriately;
allows use of FSP/GOP display init.
VBT extracted from stock ChromeOS firmware.
Change-Id: I8a2d093ad96f72fb420b94aafa790e3ba900d905
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Akemi unused devices declare:
- I2C #1 gpio_keys
- close I2C #3
- close GSPO #1
BUG=b:142800988
TEST=Reboot stress test and suspend stress test, the DUT will be
able to working properly
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ibff1446ccb213abce1a2ae19718774d9d6737cc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36086
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This commit creates a dood variant for Octopus. The initial settings
override the baseboard was copied from variant bobba.
BUG=b:141960652
BRANCH=octopus
TEST=emerge-octopus coreboot
Change-Id: Id8852e1f04f4356fac5445f6da6d56d430c88ad0
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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The change applies the DPTF parameters.
BUG=b:142849037
TEST=build and verified by thermal team
Change-Id: I5da8d373f38d23929ffec95bc1c9e942f131297f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Chrome OS firmware images have moved bitmap resources from GBB into CBFS
for a long time, so the GBB should only hold firmware keys and HWID,
that is usually less than 10k.
ARM boards usually limit GBB to 0x2f00 (see gru, cheza and kukui) but
many recent x86 simply copy from old settings and may run out of space
when we want to add more resources, for example EC RO software sync.
Note, changing the GBB section (inside RO) implies RO update,
so this change *must not* be cherry-picked back to old firmware
branches if some devices were already shipped.
BRANCH=none
BUG=None
TEST=make # board=darllion,hatch,kahlee,octopus,sarien
Change-Id: I615cd7b53b556019f2d54d0df7ac2723d36ee6cf
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Tune I2C bus 1 clock and insure it meets I2C spec.
BUG=b:142683257
TEST==flash coreboot to the DUT and measure I2C bus 1 clock
frequency less than 400KHz
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Id4cdbad4dd9d451763fb536988402d6e6fe3a378
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add enable pin for elan touchscreen
BUG=b:142710871
TEST=touchscreen work
Change-Id: I09b6ffb962272bfe46e63b057be885b1bdf13554
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Update power sequence to meet spec.
BUG=b:142710867
TEST=touchscreen work, and make sure power sequence to meet
spec with vendor.
Change-Id: I98f8b095374caa8c3540307a51f9d3b69baec905
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36060
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the SPD data for MT40A1G16KD-062E:E
BUG=b:139397313
TEST=Compile successfully.
Change-Id: I3d1ae9269ff3129845a7f53dbacbab6e1b66b6d5
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Disable DRRS on Blooguard SKU - 49, 50, 51, 52
BUG=b:142632381
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
check i915_drrs_status shows DRRS supported NO when SKU ID is blooguard.
Cq-Depend: chrome-internal:1983227
Change-Id: I36a313fd2beacb878da7383f733e206067c1c0fb
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This sets up some common default LPC decode ranges in a common place.
This may set up more decode ranges than needed but that typically does
not hurt. Mainboards needing additional ranges can do so in the
mainboard pch_enable_lpc hook.
Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Port the backlight-PWM handling from Skylake instead of the previously
used Haswell version. We use a 200Hz PWM signal for all boards. Which
is higher than the previous devicetree value, 183Hz, but that was over-
ridden by the VBIOS anyway. 200Hz is still very low, considering LED
backlights, but accurate values are unknown at this time.
Lynx Point, the PCH for Haswell and Broadwell, is a transition point
for the backlight-PWM config. On platforms with a PCH, we have:
o Before Lynx Point:
The CPU has no PWM pin and sends the PWM duty-cycle setting
to the PCH. The PCH can choose to ignore that and use its own
setting (BLM_PCH_OVERRIDE_ENABLE).
We use the CPU setting on these platforms.
o Lynx Point + Haswell:
The CPU has an additional PWM pin but can be set up to send
its setting to the PCH as before. The PCH can still choose
to ignore that.
We use the CPU setting with Haswell.
o Lynx Point + Broadwell:
The CPU can't send its setting to the PCH anymore. BLM_PCH_
OVERRIDE_ENABLE must always be set(!) if the PCH PWM pin is
used (it virtually always is).
We have to use the PCH setting in this case.
o After Lynx Point:
Same as with Broadwell, only BLM_PCH_OVERRIDE_ENABLE is
implied and the bit not implemented anymore.
Change-Id: I1d61d9b3f1802ebe18799fc4d06f1f1d3b54c924
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Helios adds TEMP_SENSOR4 to the EC ADC2 pin. Add this to
the DPTF.
BRANCH=None
BUG=b:142266102
TEST=`emerge-hatch coreboot`
Verify that Helios builds correctly.
Change-Id: I3bc19f9b9bd644e134987749ad9a4d875ad8b40a
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
Enable wifi sar feature and set wifi sar name for dragonair sku.
BUG=b:142109545
TEST=emerge-hatch coreboot chromeos-bootimage
1. Check wifi_sar-dragonair.hex in /cbfs-rw-raw/dratini
2. Add iwlwifi.debug into kernel params.
3. check SAR value from dmesg only when sku id is 21/22
Change-Id: I0e08610b7c7d2d8da5a749d278bcde26af590e31
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
FPMCU_PCH_BOOT1 pin is connected to GPP_C12. So, config GPP_C12.
BUG=b:142188003
TEST=emerge-hatch coreboot
Change-Id: I73a5c3529330ef3e72f4c7d5fcbbd2f6693494d8
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35845
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The next board rev will have a new option for an Elan touchscreen. Add
support for this in the devicetree, as well as use the 'probed' property
on both touchscreen options.
BUG=b:141957731
BRANCH=none
TEST=compiles (next board rev not available yet)
Change-Id: I135e693304cbb8dffc0caf4c07846033d6802208
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
Update GPIO_138 and GPIO_139 setting to fix EMR function.
BUG=b:141729962,b:141281846
BRANCH=octopus
TEST=verify EMR function in Grob360S.
Change-Id: I28cef592374fb4aeee2f3d3010cc0e237d62a2fd
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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|
Load the calibration params from flash first and check the correctness
of the params. If the params have correct format, perform DRAM fast
calibration with these params to reduce bootup time. Otherwise, load the
DRAM blob and perform DRAM full calibration.
Bootup time of DRAM partial calibration:
- 1,349,385 usecs with low frequency
- 924,698 usecs with middle frequency
- 1,270,089 usecs with high frequency
3,544,172 usecs in total.
Bootup time of DRAM fast calibration:
- 216,663 usecs with low frequency
- 328,220 usecs with middle frequency
- 322,612 usecs with high frequency
867,495 usecs in total.
BUG=b:139099592
BRANCH=none
TEST=emerge-kukui coreboot
Change-Id: I8de29b14b1fb24b3b4f351c855c5c4d8f350cc34
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Load calibration params from flash. If the format of the params is
correct, use these calibration params for fast calibration to reduce the
bootup time.
Bootup time of DRAM partial calibration:
- 1,349,385 usecs with low frequency
- 924,698 usecs with middle frequency
- 1,270,089 usecs with high frequency
3,544,172 usecs in total.
Bootup time of DRAM fast calibration:
- 216,663 usecs with low frequency
- 328,220 usecs with middle frequency
- 322,612 usecs with high frequency
867,495 usecs in total.
BUG=b:139099592
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I9ef4265dd369a1c276bb02294696556df927e7bc
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35164
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Drallion uses UART 0 for console, other two variants remain as UART 2.
BUG=b:139095062
TEST=emerge-drallion coreboot chromeos-bootimage.
Console should be visible.
Change-Id: I520a07ad6f755bc2e6481329fc69bef9a36e31e2
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35785
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Dratini/Dragonair doesn't support pen insertion/ejection feature,
so remove it.
BUG=b:142159117
TEST=emerge-hatch coreboot
Change-Id: I64859a162d8dc75ffe55d98b72a056dd72e8de75
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
FreeBSD's sh (basic posix shell) did not interpret the '\%o' escape
in the same way bash/zsh do. As a result, the decoded files ended up
with ASCII numbers instead of the decoded binary data.
Change-Id: I95b414d959e5cd4479fcf100adcf390562032c68
Signed-off-by: Greg V <greg@unrelenting.technology>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
BUG=b:142131099
BRANCH=None
TEST=powerd_dbus_suspend, ensure DUT in S0ix
touch fp sensor and ensure DUT wakes up in S0
Change-Id: If57094aa1076d79ac0886b71fa5532411bfeb45f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
Add the missing detect pin to fix Wacom touchscreen function.
BUG=b:140415892,b:138082886
BRANCH=N/A
TEST=N/A
Change-Id: I8a1b48d4d502945b88e38393383512d30b684fa4
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35790
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Applying reset_gpio config of stylus for kohaku. GPP_A19 has been assigned in
the latest schematics.
We would keep GPP_A10 as output high for old revision devices temporarily.
BUG=b:141914474
BRANCH=none
TEST=verified stylus works internally
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: I61f0f9a4378f47bf455f0726d44beeaf2f67197b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
Add PRESERVE to UNIFIED_MRC_CACHE so that we don't retain the memory
training data upon a FW update unless we need to. We have had users
complaining that a 15 second memory training upon update makes them
believe that their device is not booting, thus many of them hard
resetting before bootup.
BUG=b:142084637
BRANCH=None
TEST=flash RW_SECTION_A, RW_SECTION_B, and WP_RO sections and make
sure memory training doesn't occur on following bootup.
Change-Id: Ia5eb228b1f665a8371982544723dab3dfc40d401
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35803
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
After adjustment on Grob360S
I2C0 CLK: 389.9 KHz
BUG=b:141729962
BRANCH=master
TEST=emerge-octopus coreboot chromeos-bootimage
measure by scope with Grob360S.
Change-Id: I6a30257b7978cc8899a55f9fd6ffffe01cb2a851
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
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The SPI flash component requirement for Kukui family is 8M so we should
update FMAP for that:
- Add more comments for alignment and size recommendation.
- Enlarge RO to 4M, and RW_SECTION_{A,B} both ~1.5M.
- BOOTBLOCK: 32K->128K, aligned with other ARM boards.
- Preserve RW_DDR_TRAINING for new calibration.
- Reorder the sections for better alignment.
- RW_MISC to contain RW sections that should be merged when creating AU image.
BUG=b:134624821
TEST=Built Kukui image and boots. dump_fmap -h image-kukui.bin:
# name start end size
RW_LEGACY 00700000 00800000 00100000
RW_SHARED 006f7000 00700000 00009000
RW_UNUSED 006f8000 00700000 00008000
SHARED_DATA 006f7000 006f8000 00001000
RW_SECTION_B 00580000 006f7000 00177000
RW_FWID_B 006f6f00 006f7000 00000100
FW_MAIN_B 00582000 006f6f00 00174f00
VBLOCK_B 00580000 00582000 00002000
RW_MISC 00577000 00580000 00009000
RW_ELOG 0057f000 00580000 00001000
RW_DDR_TRAINING 0057d000 0057f000 00002000
RW_NVRAM 0057b000 0057d000 00002000
RW_VPD 00577000 0057b000 00004000
RW_SECTION_A 00400000 00577000 00177000
RW_FWID_A 00576f00 00577000 00000100
FW_MAIN_A 00402000 00576f00 00174f00
VBLOCK_A 00400000 00402000 00002000
WP_RO 00000000 00400000 00400000
RO_VPD 003f8000 00400000 00008000
RO_SECTION 00000000 003f8000 003f8000
RO_FRID 003f7f00 003f8000 00000100
GBB 003f5000 003f7f00 00002f00
COREBOOT 00021000 003f5000 003d4000
FMAP 00020000 00021000 00001000
BOOTBLOCK 00000000 00020000 00020000
Change-Id: Id342d57dc95c6197d05b8a265742a2866c35ae09
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Previously all boards using eSPI for the Chrome EC just called it
LPC as the code for the chrome EC is the same between the two
busses.
I'm adding a new Kconfig symbol to specify eSPI, so switch the
boards that actually use eSPI to that symbol and add the LPC
symbol to all the others.
The EC_GOOGLE_CHROMEEC_LPC symbol will no longer default
to enabled for x86 platforms, so one symbol or the other needs to be
specified for each platform.
BUG=b:140055300
TEST=Build tested only.
Change-Id: Icf242ca2b7d8b1470feda4e44b47a2cdc20680f2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
BUG: None
TEST: Build successful, checked the CBMEM log if 1f.6 is disabled with this patch
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.corp-partner.google.com>
Change-Id: I4e74b259ce8f5f70833dce94692dcbe33e8504db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35509
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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The previously provided device path made no difference, all
integrated PCI devices point back to the same chip_info
structure.
Change reduces the exposure of various SA_DEVFN_xx and
PCH_DEVFN_xx from (ugly) soc/pci_devs.h.
Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Disable memory channel by HW strap pin. Using for factory
debug.
BUG=b:139773082
BRANCH=N/A
TEST=Rework HW strap pin and check /proc/mem_info
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic5f53f0ba3bd432fbcb7513d2a8aa49d42f7a23e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35241
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Two fields of struct sdram_params are renamed for future CL of DRAM full
calibration. Field 'impedance' is also removed.
BUG=none
BRANCH=none
TEST=emerge-kukui coreboot
Change-Id: I2f9673fd5ea2e62ee971f0d81bdd12aaf565e31c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35738
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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* Disable SATA controller and related configs.
* Disable PCIe root ports 10 and related configs.
-> Board uses integrated CnVi for WLAN
* Disable PCIe root ports 12 and related configs.
-> Board uses WWAN intarfaced over USB
Change-Id: If9d49cef290dcccb114afccc3ac34cd072802ea4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35723
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
drallion uses below LPSS controllers:
I2C: 0/1/4
GSPI: None
UART: 0(Console)
BUG=b:141575294
Change-Id: I9c57f8054f5da5add667168502ebc3e089c440f8
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
|
|
To support mt8183 power saving during suspend to RAM, this patch loads
SPM firmware to support SPM suspend. SPM needs its own firmware to do
these power saving in the right timing under correct conditions. After
linux PM suspends, SPM is able to turn off power for the last CPU and do
more power saving for the SoC such as DRAM self-refresh mode and turning
off 26M crystal.
BUG=none
BRANCH=none
TEST=suspend/resume passes for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
The CONFIG_GBB_HWID can be generated automatically now so we can remove
the test-only HWIDs set in board config files.
BUG=b:140067412
TEST=Built few boards (kukui, cheza, octopus) and checked HWID:
futility gbb -g coreboot.rom
Change-Id: I4070f09d29c5601dff1587fed8c60714eb2558b7
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35635
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Internal pull up need to be enabled for GPD3 as power button pin for
PCH according cometlake pch EDS vol1 section 17-1. Without that pin will
stay floating and hook up XDP can cause system shutdown as power buttone
event will trigger.
BUG=N/A
TEST=Hook up XDP on drallion platform, able to boot up into OS and stay
at power up state.
Change-Id: Idd1befeb14a251b7c0542ca1f99049d07b28fb98
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
|
|
BUG=b:141734594
Change-Id: I419f7d11dffebe6c44eefa05750834d07d19857b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
BUG=b:141575294
Change-Id: I1b2b4362b84b170bd73b760828ca300ec86c4534
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Drallion uses UART 0 for console, change the config accordindly.
BUG=b:139095062
Change-Id: I0ae2f8459b6225b99b758180413afa22386355d4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35633
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Modify IRQ pin from D21 to A21 and support wake-up from touchpad
BUG=b:141519690
TEST=build bios and verify elan touchpad works fine
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6cc5b780ffcee24f1f2a04e88c30628ceb5904e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35551
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
new DDR particle:
1. Samung K4A8G165WC-BCWE
2. Hynix H5AN8G6NCJR-XNC
BUG=b:139085024
BRANCH=master
TEST=rework new source to DUT and re-flash bios to DUT and
verify DUT will bring up successfully
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I0d039af53938086733308a081a77a7398e7bf5d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add the configuration 'Juniper' for the new mainboard.
BUG=b:137517228
TEST=make menuconfig; select 'juniper' and build
Change-Id: I94e3ac7f6de3fecf177e344cb217eaecf6362d69
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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All variants of hatch are using Comet Lake and so the selection can be
done in Kconfig without requiring each variant to do the same.
Change-Id: Ief34296334ede5ba0f5f13381e92427ccc440707
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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This change applies fine-tuned DPTF parameters and TCC offset setting
for kohaku. Also enables EC_ENABLE_MULTIPLE_DPTF_PROFILES for tablet
mode.
BUG=b:137688474
BRANCH=none
TEST=built and verified the setting values
Change-Id: I92e268b2e07ca5a04e29bda84ddb8fc21eb23251
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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BUG=b:140545732
TEST=build bios and spd index set to 6, verify DUT bring up normally
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I337b0bdcd37a9c4baacccbc6786968031a41b31e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35511
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add G2Touch Touchscreen support for dratini
BUG=b:141281841
TEST=emerge-hatch coreboot chromeos-bootimage, and check touchscreen
work.
Change-Id: I0dbde7f8396da6335b22aeb4a9703336e2b862b8
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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A closer read of the EDS indicates that when GPIO Driver mode is
selected, GPIO input event updates are limited to GPI_STS only.
GPI_GPE_STS updates are therefore masked, and we don't want to enable
this behavior. It masks the GPE and does not allow us to see this GPE
as a wake source, obscuring the reason that the system woke up.
Also switch the IRQ from level-triggered to edge-triggered,
otherwise the system will auto-wake from any sleep state when the
pen is ejected from the garage.
BUG=b:132981083
BRANCH=none
TEST=Wake up system from S0ix using pen eject, verify that mosys
eventlog shows GPE#8 as the S0ix wakeup source. Wake up system from S3
via pen eject, and verify that the wakeup source shows as GPE#8.
Change-Id: If017e12e23134f5cfed7cbb6047cc9badd9bf7e8
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35459
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=none
TEST=emerge-hatch coreboot, use ectool to write oem name in
CBI, and checked smbios manufacturer name.
Change-Id: I9be85fbc47031d049b5bd51cfaf6232cab24e9fe
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Implementing logic base on sensor detection to determine SKU id.
BUG=b:140472369
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5e71ae6b97378b78055735bbf4b6b55ffe38b978
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35366
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This implementation adds below support
1. Add support to read memory strap
2. Add support to configure below memory parameters
-> rcomp resistor configuration
-> dqs mapping
-> ect and ca vref config
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Add DPTF based thermal control for ambient sensor for CML based
Helios system. Also, update other sensor names information.
BUG=b:139335207
BRANCH=None
TEST=Build and Boot on Helios board and check all sensor details.
Change-Id: I322d53536fbdf6db70f5a24afb322d9f206eaeac
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update DPTF thermal temperature threshold values for CML based
Helios system. This updates CPU active cooling temperature
threshold to appropriate values which addresses the issue of
running the Fan at lower CPU temperature as per bug.
Also, added active cooling temperature thresholds for other
TSR sensors.
BUG=b:141087272
BRANCH=None
TEST=Build and boot on Helios board to check the fan functionality.
Change-Id: I5c8502f8c9e6121c18024d2a8d5a4f7680797b8d
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35446
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add SKU#18 to config power sequence below:
GPIOs related to power sequnce are
GPIO_67 - EN_PP3300
GPIO_117 - FULL_CARD_POWER_ON_OFF
GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
- keep GPIO_67 and GPIO_117 high and
- pull down GPIO_161 for 30ms then release it.
BUG=b:134854577,b:137033609
BRANCH=octopus
TEST=build
Change-Id: I58e07518f6daaf608684c9fa1b1c88fc592ea117
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change adds SPD files for Drallion. Use spd_index
matrix to correspond mem_id. This can save the dummy spd index
to reduce the size of SPD.bin.
BUG=b:139397313
TEST=Compile successfully
Change-Id: I2f7e75fdbca4183bcd730e40fef4bfe280ab900b
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35346
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Implementing logic to detect SKU model and enable ISH accordignly.
BUG=b:140748790
Change-Id: I22fafb43dce6545851883be556a02d65a01fc386
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35303
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Source: Pin Schematics
BUG=b:139370304
Signed-off-by: Varun Joshi <varun.joshi@intel.com>
Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35175
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To support gpio reset SoC, we need to pass the reset gpio parameter to
BL31.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui and ATF(BL31) can get this parameter.
Change-Id: Iefa70dc0714a9283a79f97d475b07ac047f5f3b0
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Change-Id: Icdbccb3af294dd97ba1835f034669198094a3661
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33528
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change overrides USB port settings for kohaku.
Some port settings are same with baseboard, but I'd like to describe all
settings here to be aware of current setting and usage of USB ports on
kohaku.
BUG=none
BRANCH=none
TEST=built and measured SI of USB ports internally
Change-Id: I5ac05485d1cd94416e5a0aecf7fa6769bd7c9e84
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I901cb35488e08f58cdf97f3a8d0f5a8d03560f86
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33729
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch uprevs the Arm Trusted Firmware submodule to the new upstream
master (commit 42cdeb930).
Arm Trusted Firmware unified a bunch of stuff related to BL31 handoff
parameters across platforms which involved changing a few names around.
This patch syncs coreboot back up with that. They also made header
changes that now allow us to directly include all the headers we need
(in a safer and cleaner way than before), so we can get rid of some
structure definitions that were duplicated. Since the version of entry
point info parameters we have been using has been deprecated in Trusted
Firmware, this patch switches to the new version 2 parameter format.
NOTE: This may or may not stop Cavium from booting with the current
pinned Trusted Firmware blob. Cavium maintainers are still evaluating
whether to fix that later or drop the platform entirely.
Tested on GOOGLE_KEVIN (rk3399).
Change-Id: I0ed32bce5585ce191736f0ff2e5a94a9d2b2cc28
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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BUG=b:140008849, b:140573677
TEST=verify eMMC SKU and SSD SKU will bring up normally.
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I0c0adf569cc92e8b44ab72379420f2b190fa31f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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drallion_ish.bin is updated for drallion GPIO changes
and not compatible with arcada_cml.
TEST=Build and boot arcada_cml
Signed-off-by: Selma BENSAID <selma.bensaid@intel.com>
Change-Id: Idb35c33425bfd50533df74349dd645db18a65bc5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Even though GT7375P programming guide rev0.4 only requires a reset delay
of 120ms, in practice, we have to increase the reset delay to 500ms, or
Goodix FW update would fail.
This is a workaround. In the long run, we hope Goodix can fix the power
sequence in touch firmware.
BUG=b:138795891, b:138796844
TEST=boot helios board and verify Goodix FW update succeeded
Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: Ic0049bf240de0a1c7f1b1f39bf155d48bb76fb86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35350
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This will increase ME region size and reduce the BIOS region size.
BUG=b:140665483
TEST='compile successfully'
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I5be2580d280569421d0870a06f9b93124b564b6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35304
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PchPwrOptEnable FSP UPD is for internal testing and not really available
in externally released FSP source hence assigning this UPD using devicetree
config dmipwroptimize doesn't do anything.
TEST=Build and boot sarien/arcada.
Change-Id: I6da2a088fb697e57d12008fa18bd1764b3da7765
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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BUG=b:140545315
TEST=builds Kodama image and verify display working properly
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I52a56f9bbbbef5937a9601f9371e415c74ac9a7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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BUG=b:133000685
Change-Id: Ia12174e3254153dbca55070f5daf84fd8aac51d0
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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Change-Id: I3323d25b72dab2f9bc8a575ba41faf059ee1ffc4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Create dratini variant
BUG=b:140610519
TEST=emerge-hatch coreboot, and boot into chromeos on proto board
Change-Id: Ied1240d1be831568e4ab4695b893c3f48821f68b
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35285
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drallion uses the same touch panel as Sarien. Copy the deivce
from Sarien.
BUG=b:140415892,b:138082886
BRANCH=N/A
TEST=N/A
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8e6d2dcf4bd2ed2325137a05811af03692d40342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35305
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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