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Implement reset using PSHOLD.
Change-Id: I472bf73cc7b227187b284a3730ec5dea5373695c
Signed-off-by: Santhosh Hassan <sahassan@google.com>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch adds support to copy the wifi calibration
data to CBMEM so that the depthcharge can use it to
populate the data into wifi dt node.
Change-Id: Ia8184e48a7176bb3b52e4d43866b7d065952c13e
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This change adds support for logging EC events during S0ix resume.
BUG=b:124131938
BRANCH=none
TEST=Verified that the wake events are logged during the S0ix resume:
4 | 2019-03-05 07:55:27 | System Reset
5 | 2019-03-05 07:55:27 | Chrome OS Developer Mode
6 | 2019-03-05 07:56:54 | S0ix Enter
7 | 2019-03-05 07:57:09 | S0ix Exit
8 | 2019-03-05 07:57:09 | Wake Source | Power Button | 0
9 | 2019-03-05 07:57:09 | EC Event | Power Button
Change-Id: I624f94c29bc66dbf4d9e1fec573d259985260ed3
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: If5c5ebacd103d7e1f09585cc4c52753b11ce84d0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Move these configs to Kconfig.name as well.
BUG=b:127310803
BRANCH=None
TEST=emerge-hatch coreboot chromeos-bootimage
Change-Id: I793363740fa0730a1e9e1aa7a9fa82d2789334b4
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Adding a new board variant 'Mistral' based on qcs405 soc.
TEST=build
Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Update the Kconfig option for disabling ESPI SMI source
to disable it entirely, not just when ACPI mode is disabled.
For the situations where this is needed (just the sarien
board) it is better to completely stop the EC from sending
any SMI events as no actions are taken.
Change-Id: Id94481bb2f0cfc948f350be45d360bfe40ddf018
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add bluetooth Rfkill function to recover the Bluetooth controller in
cases where itself has entered a bad state and needs to be recovered.
Bug=b:123342945
TEST=Boot up into OS and dump SSDT table, check there's _DSD entry under
Bluetooth devices with GPIO in.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ibbe67887227af42b6c040deade7bf5da4ce3227f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Disable the use of AMD's Secure OS through the Kconfig option.
BUG=chromium:903833
TEST=Build google/aleena, verify types 02, 0c, 0d are removed
from PSP directory table
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iabb0632eef88170dde45dea2e2e15b54b3a06f7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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We were used to set the same values in the system and board tables.
We'll keep the mainboard values as defaults for the system tables,
so nothing changes unless somebody overrides the system table hooks.
Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Change-Id: Ie7afe77053a21bcf6a1bf314570f897d1791a620
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This change enables tablet mode ACPI device for all hatch boards.
BUG=b:125355874
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I4d3818497172828d750b34fe91cbb6cc65e69fc5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Enable ACPI TBMC notification on tablet mode change to support
convertible Aleena devices.
BUG=b:124132058
BRANCH=grunt
TEST=evtest shows tablet mode events
Change-Id: Iaf8ef031d4660f0791b5f664880437e6dfa58dc8
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Accoriding to 574354, we need to tune each port to pass eye diagram
other than just use recommanded setting as they are base guidence only.
Bug=b:124407280
TEST=Build and boot up on arcada board.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I587695809b368edd33852c4241de097ca31e9d66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31632
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:125933998
CQ-DEPEND=CL:1510513
BRANCH=None
TEST=manually verify on hatch, chromeos-ec interrupt count increases
Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: I1dd38ca5aed1e0ddecb4738910cbfa92de33d315
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31814
Reviewed-by: Enrico Granata <egranata@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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From doc#573387 CML System Memory DQ DQS Rcomp Mapping Information
User Guide, RCompResistor[0] should be 121.
BUG=b:122959294
BRANCH=None
TEST=emerge coreboot and make sure boots up
Change-Id: If69e7fb41e79d88d21b0e50fb65107a1686d696a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31868
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update Hatch DRAM IDs to use the new DRAM ID assignment for general
spds:
0 = 4G 2400
1 = 4G 2666
2 = 8G 2400
3 = 8G 2666
4 = 16G 2400
5 = 16G 2666
BUG=b:122959294
BRANCH=None
TEST=emerge coreboot and make sure boots up
Change-Id: Ic47737ce37597318bb794b63a47ced2467d8bbb0
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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MEM_CH_SEL is used to indicate whether we are on a single or dual
channel device, where MEM_CH_SEL = 1 for single channel skus and
MEM_CH_SEL = 0 for dual channel skus. Initialize single_channel field
(from GPP_F2), which will in turn initialize MemorySpdPtr pointers in
cannonlake soc code. In the first build, we did not use GPP_F2, so we
need to add an internal pulldown as those early devices were all dual
channel devices.
BUG=b:123062346, b:122959294
BRANCH=None
TEST=Boot into current boards and ensure that we have 2 channels as expected
Also, verify that GPP_F2 is set to 0.
Change-Id: I89d022793580be603a93d0b177d73ce968529b5c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This commit create bloog variant for Octopus.
Initial settings are copy from meep.
Remove I2C tuning, WACOM digitizer and WEIDA touchscreen.
Override GPIO configuration for unused LTE and Pen.
BUG=b:127736039
BRANCH=octopus
TEST=None
Change-Id: I1d04c97cb0622075a25825ba2c835d556c8b0423
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The board version is part of EC's EEPROM, select Kconfig items to enable
requesting the EC for board version.
BUG=b:128385395
TEST=Verified the mainboard version is from EC's EEPROM.
Change-Id: I4bc1cac43c6cf73522f3a4bee89cc000a430d996
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31858
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable WLAN SAR power table.
BUG=b:123552641
TEST=Verified WLAN SAR power table forllows VPD setting
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I882b1c7ed0b1142a84eb338142e1c984df45eeba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This change reads DRAM part number from EEPROM if available and
returns it using the SoC callback (mainboard_get_dram_part_number).
BUG=b:127609572
TEST=Verify that DRAM part number from EEPROM is added to DMI table
17 (dmidecode -t 17).
Change-Id: I6ade6999828b6d67aa78d04199138f195a97ba8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I1341f90230f318ac81a4aea24872ff272adad1eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31856
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use <arch/acpi.h> when appropriate.
Change-Id: I05a28d2c15565c21407101e611ee1984c5411ff0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Adding Hatch_whl as a variant of hatch. This is a snapshot of the WHL
version of hatch so that we can rebuild the bios images for Hatch with
WHL SoC.
BUG=b:127310803
BRANCH=NONE
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
make sure HATCH_WHL is built as well.
Change-Id: I24510fa226878582a61f1846f0b56a2c65204a92
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Following changes are done to enable audio support on hatch
1. Enable I2C4 device at 400Khz at 1.8V
2. Configure GPIO for HP INT and SPKR_PA_EN
3. Add ACPI entry for RT5682 and MAX98357A
4. Enable I2S0 and I2S1 lines
5. Enable generic max98357a driver in Kconfig
BUG=b:123738217
BRANCH=none
TEST=Check SSDT table for RT5682 & MAX98357a entry.
Verify audio using Sound Open firmware (SOF)
Change-Id: I93f3917c19cc3f0f8fd7b5e1b4d9b24a59f45f84
Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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In preparation for the transition of hatch from WHL to CML, we are
creating a checkpoint called hatch_whl that we can use for creating
firmware compatible with the WHL hatch variant.
BUG=b:127310803
BRANCH=NONE
TEST=NONE
Change-Id: Iecae584ee6feefcf29955a4720e9c24bdc8abe6d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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BUG=b:123490912
BRANCH=None
TEST=flash BIOS and make sure hatch boots up properly
Change-Id: I9e41f0b38703f2c7a2b5a7ac9b108f8f10070004
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31724
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I7e181111cd1b837382929071a350b94c3afc1aaa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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variants
BUG=b:127394249
BRANCH=master
TEST=emerge-grunt coreboot chromeos-bootimage
Change-Id: Ibb4beddf186233fd82ec8f3a01bf14d00b1352ff
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31778
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new Pantheon sku-id for loading vbt-pantheon.bin
BUG=b:78663963
BRANCH=firmware-nami-10775.B
TEST=Boots to OS and display comes up.
Change-Id: Icd56905e1e04de6f307393ae23f741b93ff23a4c
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31747
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We want to publish "arcada_ish.bin" as the fw name for Integrated
Sensor Hub (ISH) so the kernel shim loader code can use it to
construct the correct path in /lib/firmware/intel for the firmware
load process.
BUG=b:122722008
TEST=Verify that shim loader CLs use new value when constructing
firmware path
Change-Id: I6299de82566a3bad8521f8158bb047d5c1ff0cf8
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The other DEFAULT_ entries are just immediate
constants.
Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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For Chrome OS (or vboot), The PRESERVE flags should be applied on
following sections:
RO_PRESERVE, RO_VPD, RW_PRESERVE, RW_ELOG, RW_NVRAM, RW_SMMSTORE,
RW_VPD, RO_FSG (b:116326638), SI_GBE (chromium:936768),
SI_PDR (chromium:936768)
With the new PRESERVE flag, we don't need RO_PRESERVE and RW_PRESERVE in
the future. But it's still no harm to use it if there are multiple
sections all needing to be preserved.
BUG=chromium:936768
TEST=Builds google/eve and google/kukui inside Chrome OS source tree.
Also boots successfully on eve and kukui devices.
Change-Id: I6664ae3d955001ed14374e2788d400ba5fb9b7f8
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Follow b:123342945 to add GPIO H15(BT_RADIO_DIS#).
BUG=b:123342945
TEST=Verified BT function on Arcada DVT1 system
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I260a2312d47385da3c7ec215267ff63ada04f2c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Add 6GB dual-channel memory configuration for future use.
BUG=b:124634885
BRANCH=octopus
TEST=emerge-octopus coreboot
Change-Id: I36d6c704ac6708b29cc570a2209eeb32de6148b3
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31460
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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MMIO operations are arch-agnostic so the include
path should not be arch/.
Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I91158452680586ac676ea11c8589062880a31f91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31692
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fixes indirect includes that would break with followup work.
Change-Id: I37ca01b904a0b422a4d09475377e755e167a6ab3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Enable the support for providing a MAC address for a dock to use based on
the VPD values set in the platform.
BUG=b:123925776
TEST=tested on sarien by setting VPD values and observing the string
returned by the AMAC() method:
> vpd -i RO_VPD -s "ethernet_mac0"="AA:AA:AA:AA:AA:AA"
> vpd -i RO_VPD -s "dock_mac"="BB:BB:BB:BB:BB:BB"
1) Test with no policy set, returns "dock_mac"
ACPI Debug: "VPD region RW did not verify"
ACPI Debug: "Found VPD KEY dock_mac = BB:BB:BB:BB:BB:BB"
ACPI Debug: "MAC address returned from VPD: BB:BB:BB:BB:BB:BB"
ACPI Debug: "AMAC = _AUXMAC_#BBBBBBBBBBBB#"
2) Test with policy set to "builtin", returns nothing
> vpd -i RW_VPD -s "dock_passthru"="builtin"
ACPI Debug: "Found VPD KEY dock_passthru = builtin" [AMAC returns Zero]
3) Test with policy set to "ethernet_mac0"
> vpd -i RW_VPD -s "dock_passthru"="ethernet_mac0"
ACPI Debug: "Found VPD KEY dock_passthru = ethernet_mac0"
ACPI Debug: "Found VPD KEY ethernet_mac0 = AA:AA:AA:AA:AA:AA"
ACPI Debug: "MAC address returned from VPD: AA:AA:AA:AA:AA:AA"
ACPI Debug: "AMAC = _AUXMAC_#AAAAAAAAAAAA#"
4) Test with policy set to "dock_mac"
> vpd -i RW_VPD -s "dock_passthru"="dock_mac"
ACPI Debug: "Found VPD KEY dock_passthru = dock_mac"
ACPI Debug: "Found VPD KEY dock_mac = BB:BB:BB:BB:BB:BB"
ACPI Debug: "MAC address returned from VPD: BB:BB:BB:BB:BB:BB"
ACPI Debug: "AMAC = _AUXMAC_#BBBBBBBBBBBB#"
Change-Id: I90474e264cc433c0fd1a4b0dbaf98e5f74180d54
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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This reverts commit 5e90ef8c356099e42612bc97976c67092d0810ff.
Reason for revert: The 1s interval causes early throttle in usage spike. (log in b/123895423#comment3)
BUG=b:113101335
BRANCH=None
TEST=learning from Nocturne
Change-Id: Id6467b51eb937b89b4c08641f36266544c8fa176
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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In order to prevent keyboard keys pressed at boot from causing issues
in the payload remove the PS2 keyboard driver so it does not get
initialized until it is needed in libpayload.
This was enabled initially because the keyboard controller on this
platform does not come up in translated mode, so unless coreboot
called keyboard_init() the keyboard would never work properly in the
kernel because it would come up as an "AT Raw" device instead of an
"AT Translated" device.
Instead of initializing the keyboard in coreboot a workaround is
added to the payload to put the keyboard into translated mode.
BUG=b:126633269
TEST=boot on sarien while pressing keys and ensure libpayload and/or
the kernel does not have any issues initializing the keyboard.
Change-Id: I765e808f0d2589cf23c0349798a07e2706a2a7a4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.
Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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We had two ways to configure the serial IRQ mode. One time in the
devicetree for FSP and one time through Kconfig for coreboot. We'll
use `enum serirq_mode` from soc/intel/common/ as a devicetree option
instead. As the default is `quiet mode` here and that is the most
common mode, this saves us a lot of lines.
In four cases kblrvp8, 11 and librem 13v2, 15v3, we had conflicting
settings in devicetree and Kconfig. We'll maintain the `continuous`
selection, although it might be that coreboot overrode this earlier
on the kblrvps.
Note: A lot of Google boards have serial IRQ enabled, while the pin
seems to be unconnected?
Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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INT_MODEL defined in ACPI 1.0 and renamed to reserved since V 2.0.
The value for this field is zero but 1 is allowed to maintain
compatibility with ACPI 1.0.
So set this value to zero as we are using greater version than ACPI 1.0.
Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29986
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On Sarien, change pin config of 0x19 (headset mic) and
0x21(headset headphone) to change jack location so that naming does
not use "Front" in the name."Front Headphone" --> "Headphone" so it
matches naming on Arcada.
BUG=b:126334749
TEST= verify with 'evtest' command that jack name is
"HDA Intel PCH Headphone" not "HDA Intel PCH Front Headphone"
Change-Id: I36ccf0c0a3952ab363fe6ee313fac8f0cce4dd61
Signed-off-by: Joyce Toh <joyce.toh@intel.com>
Reviewed-on: https://review.coreboot.org/c/31624
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Preliminary dptf change for Atlas
- Throttle charger using all temp sensors (not just ambient)
- Throttle charger with higher priority than CPU
- Update throttle temperature using data from surface thermistor
in thermal chamber test
BUG=b:113101335
BRANCH=None
TEST=based on preliminary data from thermal chamber test
Change-Id: Ic1ab72f569e8a4f7bffc5560518fb703d32f4b21
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
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Use 7w PL1 with DPTF throttle to enable better performance for atlas.
BUG=b:113101335
BRANCH=None
TEST=Recommend setting from thermal team. Build coreboot on atlas
Change-Id: Idcf44f213259634a507a013b31b410ed322e9479
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31627
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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coreboot did not program all GPIOs from C0 to C7 correctly which are
SMBUS GPIO. Some of the GPIOs are left in default mode which is
native function but we need to configure as GPIO mode and provide proper
configuration as per schematic.
After fixing GPIO, CSME power gating issue also gets fixed since SMBUS was not
getting idle due to GPIO configuration and CSME was not getting power
gated due to SMBUS.
BUG=b:123702553
BRANCH=none
TEST=Check on hatch board. CSME was not getting power gated for s0ix.
After applying this patch CSME is power gated now
Change-Id: I5c6b9310dcc7bade0023abd5524781ce71df28be
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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|
Initialize RTC at ROM stage.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I9d9c68755e8a6ac65dd794211e6ccf06e5057567
Signed-off-by: Ran Bi <ran.bi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Instead of using 2, 0 is now used for non-CBI provisioned board or
corrupted CBI board to confrom to the sku encoding.
BUG=b:123676982
BRANCH=kukui
TEST=test with un-provisioned board to verify the sku_id.
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I66f29f8a46cd774b40354def7d3623ec44cb96ce
Reviewed-on: https://review.coreboot.org/c/31623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Initialize GPIO_PCH_WP early in boot. Update cros_gpios[] array with
GPIO_PCH_WP information. Also, Configure recovery mode GPIO as virtual
since hatch does not have one.
BUG=b:125943273
Change-Id: I0b7e6dbf9229941aca4952965fb54f07457dccae
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Hatch implements active high SD_PWR_EN and requires a workaround
in _PS0 and _PS3 control methods to make sure SD_PWR_EN stays low
in D3. Select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE to enable the same.
BUG=b:123350329
Change-Id: I96ab9660eb50100207fe9a237f5924b65eae0928
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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SD_CD# in Cannonlake PCH is also wired to an internal virtual GPIO,
expose that GPIO for kernel to configure card detect IRQ.
BUG=b:123350329
Change-Id: I566cc2eb11dc257366897a1efba905b8ddcf493d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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Adapted from Chromium commit 5351dc0d
[Edgar: To set the RX ODT limit and dram geometry with RAMID detection]
Several cyan variants require memory init parameters be passed to FSP
for handling of specific Micron modules; without these, RAM init will
fail when loading training data from the MRC cache, and boot will halt.
This was missed when I upstreamed edgar along with the other cyan
variants, so add the required memory init parameters for edgar as per
its source Chromium branch.
Test: build/boot on edgar board with affected Micron memory
modules, verify boot successful with populated MRC cache.
Change-Id: I6a2bc30b54ff1a17c854a90dfcb2308d27ee2be7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31615
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On flapjack, retrieve the board information via CBI interface.
Also reserving 0x2 sku_id for the case of un-provisioned board as this is the id
used prior to the readiness of cbi.
BUG=b:123676982
BRANCH=kukui
TEST=provisioned cbi info and verify the sku_id.
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: Iad7a52df38e2045abbdded8ba0a1f1544de961fc
Reviewed-on: https://review.coreboot.org/c/31586
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For some reason, wake does not currently work from GPP_D21, but IRQs
are working fine from that gpio. Thus, we have to switch IRQ to
GPP_D21 and wake to GPP_A21, which was previously used for IRQs from
the trackpad. Additionally, we need to use two gpios for irqs and
wake source at the moment because of b:123967687, where FSP is locking
down PCR and configuring ITSS. We need to configure the wake source
gpio as inverted and the IRQ gpio as non-inverted until the bug is
resolved.
BUG=b:121212459
BRANCH=None
TEST=run evtest with trackpad
Use trackpad with ChromeOS UI and make sure it reacts as expected.
Run powerd_dbus_suspend and press trackpad and make sure DUT
wakes.
Change-Id: I7b236136befc05c6586d9ba69185ed4b5d385273
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The latest rev. of the atlas board moves the WiFi wake source from
WAKE# to GPP_B7. The original GPP_A0 in the device tree is just
wrong. This also reconfigures DW1 to the GPP_B group so we can use
GPP_B7 as a wake source.
GPP_B7 is still configured as a no-connect in gpio.c, so this doesn't
actually enable WiFi wake. We'll follow up with another patch to set
up GPP_B7 properly on boards that support it.
BUG=b:122327852
BRANCH=none
TEST=atlas still boots
Change-Id: I1816500dd0ab6186fd51aa6945faf73d00c152fe
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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When <symbols.h> was first introduced, it only declared a handful of
regions and we didn't expect that too many architectures and platforms
would need to add their own later. However, our amount of platforms has
greatly expanded since, and with them the need for more special memory
regions. The amount of code duplication is starting to get unsightly,
and platforms keep defining their own <soc/symbols.h> files that need
this as well.
This patch adds another macro to cut down the definition boilerplate.
Unfortunately, macros cannot define other macros when they're called, so
referring to region sizes as _name_size doesn't work anymore. This patch
replaces the scheme with REGION_SIZE(name).
Not touching the regions in the x86-specific <arch/symbols.h> yet since
they don't follow the standard _region/_eregion naming scheme. They can
be converted later if desired.
Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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EC software sync had been disabled because BIOS was not bundling a
useful EC image. This is no longer required. This CL removes that
change so EC software sync is enabled by default.
BUG=b:124208414
BRANCH=None
TEST=Tested with a system that have a different RW image and verified
that this image was overwritten to the one bundled in the BIOS and
that the EC was running its RW image.
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Change-Id: Ic1ffdb62e9fa2cacb3296cb3807082f23e171ab5
Reviewed-on: https://review.coreboot.org/c/31537
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Change-Id: I91b54b43c8bb5cb17ff86a6d9afa95f265ee49df
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
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This patch adds the _DSM method 5 and 6 for entering and exiting S0ix.
The _DSM method gets injected into DSDT table and called from kernel.
LPIT table is hardcoded in this patch but the proper way to implement
is to use inject_dsdt to make the _DSM methods available for soc's to
implement.
Calling the LPIT table from mainboard here so that with the current
implementation the platforms which do not have lpit support throw
compilation error.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db
Reviewed-on: https://review.coreboot.org/c/31101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
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After adjustment on Sarien EVT
Touch Screen CLK (Elan): 389.7 KHz
Touch Screen CLK (Melfas): 377.7 KHz
Touch Pad CLK: 385 KHz
BUG=b:122657195
BRANCH=master
TEST=emerge-sarien coreboot chromeos-bootimage
measure by scope with sarien.
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Change-Id: I53b60354e5a7a0ace8efb677775c0a9f8779061d
Reviewed-on: https://review.coreboot.org/c/31476
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow b:123461432#5 to update GPIO H3(CNVI_EN#) for DVT1.
Update setting GPIO H3 to output and low level.
BUG=b:123461432
TEST=Built and tested on sarien system
Change-Id: I6a56df9a7bf75f49133a646312ae5093c2652698
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
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Follow thermal table (b:123383634 comment#1) for EVT1 tunning.
BUG=b:123383634
TEST=Built and tested on sarien system
Change-Id: I22908e4bf39aedb8cf31a9060084f6f36bff56ca
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Use the common VMX implementation, and set IA32_FEATURE_CONTROL
lock bit per Kconfig *after* SGX is configured (as SGX also sets
bits on the IA32_FEATURE_CONTROL register).
As it is now correctly based on a Kconfig, the `VmxEnable` devicetree
setting vanishes.
Test: build/boot google/[chell,fizz], observe Virtualization enabled
under Windows 10 when VMX enabled and lock bit set.
Change-Id: Iea598cf74ba542a650433719f29cb5c9df700c0f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29682
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Intel SOC can only shadow the top 16MB of SPI into memory so
in order to make it easier to access the NVRAM region with memory
mapped interface move it above the much larger RW_LEGACY region.
I tested to confirm that this region can now be read via MMIO
interface and does not need to use the hwseq SPI controller.
Change-Id: Iafacb01eec07beaf474b6a1f2b36a77117e327da
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
|
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Create VR settings configuration as per board design.
BUG=N/A
TEST=Build and boot up into sarien platform.
Change-Id: Ic196fd80e5211bd5146158d4d340b52c850a4e62
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/31404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
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This change enables mode change as a wake source for S3.
BUG=b:124132058
Change-Id: I95b1eac800858ab17cdf69bdd3f2c5828516c184
Signed-off-by: Mengqi Guo <mqg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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BUG=b:121354442
TEST=None
Change-Id: I348c7106772eecd513baf9abe60ef19008d0ba4d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/31424
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Update dptf for arcada EVT.
BUG=b:123924662
TEST=Built and tested on arcada system
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Ieed8021b83776fdb6320ff89b57c8d2747667fd5
Reviewed-on: https://review.coreboot.org/c/31331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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We need disable touch screen device on laser SKU ID 6.
BUG=none
TEST=according to sku_id (Laser(convertible): 5, Laser14(clamshell):
6, Laser14(clamshell + touch):7) distinguish whether disable touch
screen device.
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6953c35a5e8c93d88fe63362156faa351e8ee71f
Reviewed-on: https://review.coreboot.org/c/31428
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Enable DPTF functionality on hatch platform.
Change-Id: If9ef74364616f95b27b73c39fea42d2623d78ae2
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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CNVi Bluetooth module is at port 8 (zero-indexed) and not at port 9. Fix
the device configuration in the devicetree.
BUG=b:123296264
BRANCH=octopus
TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset
gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured
that the kernel btusb driver is able to find the exported GPIO in the
devices with CNVi BT module.
Change-Id: I302bc87b18a1aaad77bfb73d607ba28b89b79c14
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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According to request of comment 35, setting ELAN as the default.
BUG=b:122019253
BRANCH=master
TEST=Verify touchscreen on sarien works with this change.
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Change-Id: Iee5e7a21545ca798c0c22f86906acc8e7d81e945
Reviewed-on: https://review.coreboot.org/c/31430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Eanble Elan touch for sarien EVT build
BUG=b:119763054
BRANCH=master
TEST=Verify touchscreen on sarien works with this change.
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Change-Id: I790436338705fc9d68f714245e9b9bb518ddb30a
Reviewed-on: https://review.coreboot.org/c/31413
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change bumps up the BIOS region to 28MiB to use the hole
between SI_ALL and SI_BIOS. Since this SPI flash part is 32MiB, only
the top 16MiB actually gets memory mapped. Thus, the change ensures
that only RW_LEGACY lies in the 12MiB that is not memory mapped.
BUG=b:123443737
TEST=Verified that hatch still boots up. Ensured that fmap dump looks
correct.
Change-Id: I5832d2b89c7eedfc270755e2add16131cfbddff4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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This change enables mode change as a wake source for S3 and S0ix.
Change-Id: I2e7f9997776b1e024ea417eb69e6c2ffa8c62580
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The Sarien board may have different touchscreen devices that use the
same I2C slave address but have different requirements such as needing
a special driver or ACPI configuration.
In order to support this the devicetree may be configured with multiple
devices at the same address and at boot time the unused devices will be
disabled.
Because there is no GPIO for selecting the device that is present it can
instead be selected with Kconfig, or by setting a VPD key to the HID of
the touchscreen device that is present. The default for Sarien devices
is to not enable a touchscreen for the OS.
The touchscreen selection is currently limited to the Sarien variant but
this also adds the touchscreen HID for Arcada to Kconfig so it would not
complain about the key not being set.
BUG=b:122019253
TEST=This was tested on a Sarien board by adding a second entry to the
devicetree at the same address. Without this change the SSDT is not
loaded by the kernel because of the address conflict. After this change
no touchscreen is enabled by default, but one can be selected with
Kconfig or by setting the 'touchscreen_hid' VPD key.
Change-Id: I4da12b1de0c551bcd89325fe0d8c66c6ffeb7afc
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Follow Northbay and intermal project to add GPIO H3(CNVI_EN#) for DVT1.
BUG=b:123461432
TEST=Built and tested on sarien system
Change-Id: I580a6e094d84a7bada534b14c2b65ecf4b9942b0
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Follow b:123342945 to add GPIO H15(BT_RADIO_DIS#) for DVT1.
BUG=b:123342945
TEST=Built and tested on sarien system
Change-Id: I0caf97f6a2a8abf2914667350c76300733ead1b8
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Under some scenarios the key ladder on the Cr50 can get disabled. If
this state is detected, trigger a reboot of the Cr50 to restore full
TPM functionality.
BUG=b:121463033
BRANCH=none
TEST=Built coreboot on sarien and grunt platforms.
TEST=Ran 'gsctool -a -m disable' and reboot. Verified coreboot sends
VENDOR_CC_IMMEDIATE_RESET command to Cr50 and that the Cr50 resets and
then the platform boots normally.
TEST=Performed Cr50 rollback to 0.0.22 which does not support the
VENDOR_CC_TPM_MODE command, confirmed that platform boots normally and
the coreboot log captures the unsupported command.
Tested-by: Keith Short <keithshort@chromium.org>
Change-Id: I70e012efaf1079d43890e909bc6b5015bef6835a
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This implementation configures GPIO (GPP_A21, GPP_C21, GPP_D16)
pad in non-inversion mode i.e Rx PAD state is not inverted as
it is sent from GPIO to IOAPIC.
BUG=b:123315212
TEST=Tested for below:
-> Verify touchpad is working fine.
-> TPM init is successful and boot with fixed boot media.
Change-Id: I6034fd07ccc96a19218d57ef8bb9049c4b963ea5
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/31328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: I72effa93e36156ad35b3e45db449d8d0d0cabf06
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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It needs to tune usb2eye setting for these ports:
USB2[4] - type-c port
USB2[6] - camera
BUG=b:122878632
BRANCH=octopus
TEST=built and passed usb2eye SI test
Change-Id: Iaa3adaab2f391e95730b141dc0237ca62c459e5a
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/31359
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We leave it to linker garbage collection to drop
unreferenced code and symbols from final object files.
Function declarations and definitions are to be guarded
with preprocessor directives only as a last resort.
Change-Id: Ie8748ccddc8e31569c58deba5d08c98a04326fa8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Use AGPIO 10 as the EC sync interrupt for MKBP events for sensor data.
On this platform, interrupts are routed via the GPIO controller so need to be
registered using GpioInt instead of Interrupt.
BUG=b:123750725
BRANCH=grunt
TEST=MKBP events still received (with matching EC and kernel changes)
Change-Id: If499d24511bbaa7054207b7e0b98445723332c4f
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Traditionally, we have always allocated 1 DRAM ID per part number.
However, on nami, we have run out of DRAM IDs because we have
supported so many different parts. We are now adopting the use of
generic SPD files that are feature-based rather than specific to each
part, allowing us to support multiple parts with a single SPD.
The common SPDs were created by taking current SPDs in Nami (which is
using the same DDR4 parts as Hatch) and zeroing out all the
manufacturer information and part names. Additionally, we zeroed out
bytes 128 (raw card extension, module nominal height), 129 (module
maximum thickness), and 130 (reference raw card used) after verifying
that they are not used in FSP. We verified with these fields zeroed
out, all nami devices could boot up without errors. We also verified
on the two Hatch skus that we have (4G 2400, 8G 2666) that the generic
SPDs boot properly.
BUG=b:122959294
BRANCH=None
TEST=Make sure that we can boot up on both 4G Samsung and 8G Hynix DDR4
devices that we currently have.
Change-Id: I14d9e6b13975b6a65b506e6cd475160711b8f6d4
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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"is_wakeup_source" flag is used to indicate if the concerned device can
trigger a wakeup. This flag is redundant with the "wake" GPE event
definition. So remove the redundant flag and use the "wake" GPE event to
mark the wakeup source.
BUG=None
BRANCH=None
TEST=Boot to ChromeOS. Ensure that the device is marked as wakeup-source
in SSDT if wake GPE is configured. Ensure that the system can suspend
and the device acts as a wakeup source
Change-Id: I99237323639df1cb72e3a81bcfed869900a2eefa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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See Documentation/coding_style.md, specifically "Placing Braces and
Spaces" section.
Change-Id: Ia6a2f3d3547c16500996260b0ece9ec693f00113
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ibb7ce42588510dc5ffb04c950c4c8c64e9a2fa37
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This change uses cnl_configure_pads to configure GPIOs in ramstage so
that cannonlake SoC code can re-configure the GPIOs after FSP-S is
run. This is just adding a workaround until FSP-S is fixed.
BUG=b:123721147
BRANCH=None
TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch.
Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch performs below tasks
1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig.
2. Allow required SoC to select this kconfig to extend CANNONLAKE
SoC support and add incremental changes.
3. Select correct SoC support for hatch, sarien, cflrvps
and whlrvp.
* Hatch is WHL SoC based board
* Sarien is WHL SoC based board
* CFLRVP U/8/11 are CFL SoC based board
* WHLRVP is based on WHL SoC
4. Add correct FSP blobs path for WHL SoC based designs.
Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change enables I2C bus 2, 3 and 4 in devicetree and configures
GPIO pads for the same. It also configures pads for I2C5 as
no-connect.
BUG=b:123711244
TEST=Verified that i2c shows up in "i2cdetect -l" after booting to OS.
Change-Id: Ib4714a670d73228332115415e4393f82802c6475
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31237
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Current coreboot size is not adequate for adding new features.
Note for cros: This change is for merge to ToT only and should not be
cherry-picked into reef's firmware branch.
BUG=chromium:903833
TEST=emerge-reef coreboot
Change-Id: Ie7a25c4638c474e81fb34b57de0dfc1bf393ea67
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Select the appropriate system type for the different variants of
the Sarien board.
This will allow the Arcada variant to use the tablet mode feature
of the Intel Virtual Button driver.
Change-Id: I8a829aab012256ec196c8ec0fa298fd2bc77f2e1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change adds keyboard backlight feature for Hatch platform.
BUG=b:122799544
BRANCH=none
TEST=keyboard backlight works when EC reports correct info.
Change-Id: I29273122f061e0e442f6629351ef3670535c0507
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31175
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reconfigures the GPP_D1 GPIO pin as a no-connect. It really
doesn't go anywhere today or on previous revs of the board.
BUG=b:110614620
BRANCH=none
TEST=atlas still boots
Change-Id: Iea53cf909f8f060c4e0f14e8b4ad579b838b7caa
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This reverts commit 7696290004b6490c7ef8027d7ddf67b163e7dad8.
We're seeing trackpad problems on some units with the I2C bus running
at 1MHz but not at 400KHz. So, revert back to 400KHz until we
understand how to make 1MHz operation more robust.
BUG=b:123650686
Change-Id: Ifb06afece9eee0c153240d35e6c3001f5b74f310
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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