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2018-04-27google/kahlee: Add RW_NVRAM to FMAPMarc Jones
Add RW_NVRAM area to FMAP for VBOOT_VBNV_CMOS_BACKUP_TO_FLASH support. BUG=b:77347873 TEST=Manually clear CMOS and check coreboot restores VBNV from flash. Change-Id: Id8c6f54634b94bf6ae3755a827e80d0862a42dd2 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-27mb/google/poppy,soraka,nautilus: Enable xDCIFurquan Shaikh
This change enables xDCI controller on poppy, nautilus and soraka. BUG=b:78577893 BRANCH=poppy Change-Id: I9b0f81bda889b822479ead4d1acc2b613151a304 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25849 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26mainboard/google/kahlee: Set SPI speed in bootblockMarc Jones
Set the SPI speed for Normal, Fast, AltIO, and TPM in bootblock. This setup is needed when moving AGESA out of the bootblock. It sets the SPI bus speed of the TPM access in verstage. BUG=b:70558952 TEST=Boot with AGESA moved out of the bootblock. Change-Id: Ida77d78eb1f290e46b57a46298400ed6c8015e2c Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-26mb/google/octopus: Add dptf.asl in dsdt.aslSumeet Pawnikar
This patch enables dptf for Octopus by adding dptf.asl in dsdt.asl. BUG=b:74263914 BRANCH=None TEST=None Change-Id: I7194cdd2af88ff062ebcc92cc97b3cdc3d21ecd6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/25809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-26mb/google/grunt: Add grunt touchpad wake GPE to devicestreeDaniel Kurtz
The grunt touchpad interrupt can be used as a wake source. For grunt, the touchpad interrupt uses GPIO5 which corresponds to GEVENT7. BUG=b:77602771 TEST=In OS: # cat /proc/acpi/wakeup => D015 S3 *enabled i2c:i2c-ELAN0000:00 TEST=powerd_dbus_suspend, touching touchpad (> 1 sec) wakes from S3. Change-Id: I510642108a1257f6601f18c77cf3107573427f39 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25827 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26mainboard/google/kahlee: Enable EC wake on GPIO24Daniel Kurtz
The grunt EC uses GPIO24 (EC_PCH_WAKE_L) to signal wake-up events to the AP. On Stoney, GPIO24 maps to GEVENT (GPE) 15. The kahlee EC uses GPIO2 (EC_PCH_WAKE_L) to signal wake-up events to the AP. On Stoney, GPIO2 maps to GEVENT (GPE) 8. BUG=b:78461678 TEST=powerd_dbus_suspend, tap any key on keyboard wakes from S3. TEST=sign in, EC: lidclose, EC: lidopen => system wakes from S3. Change-Id: Ib1809740837e686992ff70b81933159a5dff7595 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-04-26mainboard/google/kahlee: Fix EC_SMI_GPIDaniel Kurtz
On the kahlee variant, EC_SMI_ODL is connected to GPIO6, which uses GEVENT 10 (GPE10). Fix this up, and also clean up the EC_*_GPI definition format a bit to match the format in the baseboard/gpio.h. BUG=b:78461678 TEST=build coreboot for kahlee Change-Id: I9445efbc02559c2a7c90f67bcb0154b04b03a1aa Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-04-25mb/google/octopus: Disable PCIE NPK deviceShaunak Saha
This patch sets the NPK device off for octopus. BUG=b:76115112 TEST=Build for Octopus and check that the logs do not report "PCI: 00:00.2 not found, disabling it". Change-Id: I3ac01f90cf946b019a6604a38dd1d6782f8d5759 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25801 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-24mb/google/kahlee/variants/baseboard/gpio.c: move all non-critical gpiosRichard Spiegel
When GPIO tables were created, there was no study on which pins had to be programmed ASAP and which could be programmed later. Execute such study and move all non-critical gpios from reset to late. BUG=b:76097508 TEST=Build and boot grunt to OS, test OS for lost functionality (WIFI, video playback, track pad, keyboard). Change-Id: Icbc9370050d619800026035caaac3e89536a460a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-24mb/google/cyan/spd/spd.c: Fix module part number transferRichard Spiegel
With the increase of dimm->module_part_number size from 19 to 21 (commit 35b273eea3) "include/memory_info.h: Change part number field from 19 bytes to 21", this code is now advancing outside DDR3 SPD designated space. The correct size is already defined as LPDDR3_SPD_PART_LEN, use it. Also make sure to 0 terminate the string. BUG=b:77943312 TEST=Build cyan. Change-Id: Iba0ef4149acfc09b7672fce079df06bf1a01dff6 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-24mb/google/poppy/variants/nami: Add keyboard backlight supportZhuohao Lee
This change adds keyboard backlight feature for Nami platform BUG=b:78360907 BRANCH=none TEST=keyboard backlight works when EC reports correct info. Change-Id: I3fceb83e155032b6e9f1763c4e2a29e7521269d2 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/25782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-23mb/google/poppy/atlas: Enable trackpadCaveh Jalali
This enables the i2c trackpad on atlas. BUG=b:75454415 TEST=able to move pointer using trackpad Change-Id: If4a82aa605ec68fd38e52c13406eaf803f9e86cc Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/25759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-21mb/google/bip: Add GPIO configuration settingsShamile Khan
These settings are identical to yorp settings except overrides are not provided for sleep_gpio[] table which is currently empty for yorp and cros_gpios[] table which is not expected to change for bip. BUG=b:77869623 BRANCH=none TEST=Build coreboot for bip. Change-Id: Icc205f576691427d78c9159dfdbced87e41a0517 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-20pci: Move inline PCI functions to pci_ops.hPatrick Rudolph
Move inline function where they belong to. Fixes compilation on non x86 platforms. Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25720 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-20soc/amd/stoneyridge/include/soc/southbridge.c: Rename gpio structureRichard Spiegel
The GPIO definition structure has evolved to a point where it's no longer specific to stoneyridge, though probably still specific to AMD. Therefore, rename the GPIO declaration structure removing stoneyridge from it. BUG=b:72875858 TEST=Build kahlee, grunt, gardenia. Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25726 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-19mb/google/octopus: Select DRIVERS_I2C_HIDFurquan Shaikh
This change selects DRIVERS_I2C_HID which is required for adding SSDT node for digitizer. BUG=b:78099046 Change-Id: I526c0ac7b88dec7b2b22d022d911840555f15cde Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-18soc/amd/stoneyridge/include/soc/gpio.h: Remove vendor code referenceRichard Spiegel
With the exception of code that deals directly or indirectly with AGESA, all other code should be independent of vendor code reference. Therefore, remove vendor code reference from any GPIO code. BUG=b:77999987 TEST=Build and boot grunt. Change-Id: I9ba78767a269ad6b9b06fa11993d8a12350e4bad Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25695 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-18mb/google/kahlee/variants/kahlee/gpio.c: Convert GPIO to new formatRichard Spiegel
As part of preparing to make GPIO code independent of vendor code references, convert GPIO table format using newly defined macros. BUG=b:77999987 TEST=Build and boot kahlee. Change-Id: I0af768bb4dbcbfef0d2d08ffe869c1dfb6827974 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-18mb/google/poppy/variants: Set VmxEnable to 1Furquan Shaikh
This change sets VmxEnable to 1 to match the kernel setting. If this feature is enabled at the kernel level and not in FSP, then there is an issue where FSP expects it to be disabled so it forces a cold reboot on every warm reboot. BUG=b:78129261 BRANCH=poppy Change-Id: Idedbde1d8eb0c9e959733b7b50e5dec804d61cae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25698 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-17mainboard/google/kahlee: Add EC back into grunt devicetreeMartin Roth
The EC code should not have been removed from devicetree when moving over from grunt. This was causing various bewildering issues that would happen on the first boot but not on subsequent reboots. BUG=b:73235377 TEST=Grunt powers off and stays powered off at dev screen. Change-Id: I225138fede66c6e189e0e79d1261d0d579f7cbdc Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-04-17mainboard/google/kahlee: Update EC pins from GPIOs to GPEsMartin Roth
The EC pin definitions are GPEs, not the GPIO numbers. BUG=b:74022675 TEST=Power status updates immediately when power is inserted. Change-Id: Icc8330a606f7a85e72b65094462a684927986829 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25689 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-17mb/google/poppy/variants/nami: Update GPIOsShelley Chen
Updating some GPIOs based on changes in the latest schematics. Also renaming signals to match that of latest schematics. BUG=b:73749640 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Make sure different SKUs still boot. Change-Id: I7d912f4bc6765f065c75c68a45bdf9ee844e0c1d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/25646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-17mb/google/octopus: Enable Yorp EC software syncJustin TerAvest
With one additional EC change, Yorp is able to flash the EC as part of software sync and successfully boot. This change is only made for Yorp as we want this disabled for Bip bringup. BRANCH=none BUG=b:77874283 TEST=Successful flash and boot on Yorp with this change TEST=Checked GBB flags on Yorp and Bip images with gbb_utility CQ-DEPEND=CL:1014397 Change-Id: I4969b254c6a58fba9dd8d2f31feb25b55c7a0c65 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25692 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-17cbfs: Add cbfs_boot_load_file()T Michael Turney
Generalize cbfs_boot_load_struct() by passing in CBFS type Change-Id: I6e5f845cb4ce5b00f01a39619919f85e39028f19 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-17mb/google/poppy/variants/nami: Enable DPTF and configure DPTF parametersFrank Wu
The commit enables DPTF function. The DPTF parameters are provided by thermal team. BUG=b:72974136 BRANCH=poppy TEST=emerge-nami coreboot then check the parameters in DPTF ui tool Change-Id: I9b7ae34ee64f19ef783a8c1571831b2293105a18 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16mb/google/octopus: Add Write Protect GPIO to cros_gpiosHannah Williams
This will enable crossystem to access WP GPIO BUG=b:78009842 TEST= wpsw_cur in crossystem reads the correct gpio Change-Id: Iedd0057d6bdfd5a666ff282bc784f7b98e8c96e8 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16mb/google/poppy/variants/nami: Add SPD file for PantheonChris Zhou
Add SPD file for sdp hynix_dimm_H5AN8G6NCJR-VKC (ram id: 15). BUG=b:77893710 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: I434d42ff12e6dae39e5676f36ba6cf00b3a48b06 Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16mb/google/poppy/variants/nami: Add SPD file for PantheonChris Zhou
Add SPD file for sdp micron_dimm_MT40A512M16LY-075E (ram id: 14). BUG=b:77930401 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: Ia44e70948e57c2f19664d874ae005ac39d748f92 Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16google/kahlee: Resume on AC insertionMarshall Dawson
The EC should wake the system from S3 when the AC connector is plugged. BUG=b:77602394 TEST=verify resume on insert with Grunt Change-Id: I4bcaef2fe75283aaa6260b5b9efd408ff4b05f4c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16mb/google/kahlee: Select BT I2S PAD on ACP_BT_UART muxAkshu Agrawal
bt-pad-enable property is used by kernel driver to set BT I2S PAD on ACP_BT_UART_PAD_SEL mux, for those platforms which use these pins for BT I2S. By default the pins are set for UART. BUG=b:72360151 TEST=Tested playback and capture on audio device connected to BT I2S Change-Id: Id76bfa1fa1dde904f02a03b0c15986ecb1bbcc97 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/25653 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16Revert "mb/google/reef/sand: Override USB2 phy settings"Katherine Hsieh
This reverts commit aef0d6b0a7ec867ee29acf9e1c695be27626f239. This commit can only pass far-end USB eye diagram but will fail on near-end. Confirmed with Intel we should revert it. Change-Id: I2eb1d5ddb05ca6bbf6512edf48e3e0d8396ce6a7 Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/25651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-13src/mainboard/kahlee: Turn on keyboard backlight on gruntMartin Roth
Turn on keyboard backlight in romstage to indicate that the system is booting. BUG=b:77921345 TEST=Boot grunt, keyboard backlight comes on. Change-Id: Ib215b19ebdee2f8c4f431af775905eca42436d1c Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25636 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13Revert "mb/google/reef: Override USB2 phy settings"Tim Chen
This reverts commit 70ba1b7e78930acca578114cdadcbcec367730e8. This commit can only pass far-end USB eye diagram but will fail on near-end. Confirmed with Intel we should revert it. Change-Id: I6de44d5240393409d9ec5835a9de0c23453300f7 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25630 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13mb/google/kahlee: Fix IRQ routingRichard Spiegel
ACPI interrupt routing file routing.asl is not reflecting AGESA settings to the NB Interrupt Routing Registers. The AGESA settings are: Device self INTA INTB INTC INTD GPP 0 23 0 1 2 3 GPP 1 24 8 9 10 11 GPP 2 25 16 17 18 19 GPP 3 26 24 25 26 27 GPP 4 23 3 0 1 2 HDA none 22 23 20 21 GBIF none 6 7 4 5 Fix the routing table, considering that NB IOAPIC starts at interrupt 24. BUG=b:74104946 TEST=Build and boot to a modified grunt board to enable the emmc. Then used "cat /proc/interrupts" to get active interrupts. Also checked IOAPIC redirection registers, which are now being programmed. Change-Id: I60847c46f3f938f9e97d7b323b27d20e36aa2d02 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-13Revert "mb/google/coral: add usb2 phy setting override for some variants"Tim Chen
This reverts commit 06e3e1f055593bd2e2906f43040a703bc471cde4. This commit can only pass far-end USB eye diagram but will fail on near-end. Confirmed with Intel we should revert it. Change-Id: Ie987061e27996b0acc8345bf9aadb42d2c940808 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25629 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-12mb/google/octopus: Configure SMI for ESPIShaunak Saha
This patch enables EC SMI when ESPI is enabled. BUG=b:77857802 TEST= SMI is working in depthcharge. Change-Id: I52726194b8346488e5ad781e78e33c5d286d132f Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25569 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11mb/google/octopus: enable MRC recovery cacheAaron Durbin
Enable the recovery cache to speed up recovery flows. Also enable clearing of the normal mrc cache on recovery forced retrains. BUG=b:77871444 TEST=went into recovery twice. 2nd time it boots faster. Change-Id: Idfce42ac835637fa521545fadfedecd65df91d4c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-11mb/google/octopus: Select DRIVERS_SPI_ACPIFurquan Shaikh
This change selects DRIVERS_SPI_ACPI which is required to add SSDT node for SPI TPM. BUG=b:75306520 BRANCH=None TEST=None Change-Id: I0728062dae017522ba91a4b5cb16acf9f6bf4f28 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG)Jonathan Neuschäfer
Fixes: 2269a3c328 ("soc/amd/stoneyridge: Add functions for GPIO interrupts") Change-Id: I5730259bc6819defc482d31644e1f476679257b2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25588 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11mainboard/google/kahlee: Enable Keyboard backlight for GruntMartin Roth
Grunt supports a keyboard backlight, so enable the ASL code. BUG=b:77455525 Test=Boot Grunt, verify that the string 'KBLT' is in the DSDT. Change-Id: Idf0f23581bcba0b035c126c68fb167274d7c698a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25470 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10mb/google/octopus: Capitalize MB part nameJustin TerAvest
This is for consistency with other platforms. BUG=b:77494826 BRANCH=None TEST=Sucessfully rebooted, saw updated name in SMBIOS Change-Id: I83d9075931d51b3aef8076e4567a85a808ee5047 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25591 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10mainboard: Make OemCustomize.c available at romstageRichard Spiegel
As part of moving AGESA calls from bootblock to romstage, OemCustomize.c of all boards using stoneyridge must be available at romstage. BUG=b:74236170 TEST=Build grunt and kahlee, actual test will be performed at a later patch. Change-Id: Ide9efdbff6a07c670034391c0d62e8b74fa5c02b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25528 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10mb/google/poppy/atlas: Fix SPD index in commentJonathan Neuschäfer
Fixes: ba49c09b2f ("mb/google/poppy: Add variant for Atlas") Change-Id: I9c5c10abf8129ff61b97312a70ed4749606a3090 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25556 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10mb/google/poppy: Disable rear camera for all vayne skuAmanda Huang
Since there are two cameras on Nami and only one camera on Vayne. We need to disable rear camera on all Vayne sku. BUG=b:75073617 BRANCH=master TEST=Verify if only front camera shown on Vayne Change-Id: I6e7c1e8791462f00ad8336372954ee0a9465d9b8 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-09mb/google/octopus: Enable EC wakeShaunak Saha
This patch sets the wake for EC to proper gpios. BUG=77605178 TEST=Test that lidopen wakes up the system from S3. Change-Id: Icbf30007403191005396027e74b9b6fb7319e006 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25539 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09mb/google/octopus/variants/baseboard: Add DPTF parametersSumeet Pawnikar
This patch adds the DPTF parameters for Octopus baseboard. These parameters are copied from reef/coral as initial reference values. BUG=None BRANCH=None TEST=Build coreboot for Octopus board. Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: I069bae8c9ef43ebd1ee20945ef34a7f51991f621 Reviewed-on: https://review.coreboot.org/25339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-06mb/google/octopus: Edge trigger cr50 interruptJustin TerAvest
Interrupts from cr50 are edge-triggered, not level-triggered. This change updates the GPIO configuration accordingly. BUG=b:75306520 BRANCH=None TEST=None Change-Id: I0c5fb4495b404412a78965c2de7f00248d0c684b Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25538 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06mb/google/octopus/variants/baseboard: Enable DPTF supportSumeet Pawnikar
This patch enables DPTF support for Octopus baseboard. BUG=None BRANCH=None TEST=None Change-Id: I88a94c73ef0c9da708c0440f7edadd85488edfdb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/25342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-05mb/google/poppy/variants/nami: Add SPD file for Vaynechriszhou
Add SPD file for sdp hynix_dimm_H5AN8G6NAFR-UHC (ram id: 6). BUG=b:77290144 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: I33503de21c9fc14537c00c092986fd4d2998dace Signed-off-by: chriszhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Shelley Chen <shchen@google.com>
2018-04-05mainboard/google/kahlee: Update WP to active lowMartin Roth
The WP signal to the AP isn't inverted as it is on other platforms, so it was reporting incorrectly. Change the ACPI table to be active low, and invert the signal when reporting it to everything else. BUG=b:74946358 TEST=Boot grunt with battery inserted, WP signals both report 1. Remove battery, WP_CUR reports 0, WP_BOOT still reports 1. Change-Id: Ic1369dbda609e34b308af308880449643be6af39 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-04mb/google/octopus/variants/baseboard: Set PL1 and PL2 valueSumeet Pawnikar
This patch sets PL1 value to ~6W. Here, 8W setting gives a run-time 6W actual measured power. Also, this patch sets PL2 value to 15W. BUG=None BRANCH=None TEST=Build and read the MSR 0x610. Change-Id: I2439a49b9917db0d9b05f333ce1c35003da493f6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/25341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-03mainboard/google/zoombini: Enable HAVE_ACPI_RESUMEVaibhav Shankar
This patch selects `HAVE_APCI_RESUME` to enable S3 resume. This has a dependency on EC to store the hash. BUG=b:72472969 TEST=suspend and resume from S3 should work. Change-Id: I9de84dfd450936b3bc08e016bec6cf5ae88eab3d Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/25390 Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-02mb/google/octopus: Fix Trackpad interrupt GPIO configHannah Williams
BUG=b:73137125 TEST= tested trackpad on Octopus Change-Id: Icc416e7be4e42bda188f74c69db150ba42562128 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-02mb/google/octopus: Make PMC I2C pads IOSTANDBY_IGNOREHannah Williams
This fixes wake from S0ix Change-Id: I3b340deafccbf909ec1f4b11ba9a77c6b13a89fd Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-01mb/google/octopus: update SSP port and DMIC 4CH nhlt supportM Naveen
Patch corrects SSP configuration to enable audio on GLK boards. Octopus variant board uses max98357a speaker codec and 4CH DMIC, Select the appropriate NHLT blob to be packaged in CBFS. Change-Id: I101ed80f4421925120116b018424ef19d95a2a3a Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/25387 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.corp-partner.google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-30mb/google/octopus: Enable i2c4 which is the root port for audio codecShamile Khan
BUG=None BRANCH=None TEST=On octopus, "aplay -l" shows the Audio codec. Change-Id: I5d837d62f00d34edf28fd472ae0dbe7c0d94447a Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-30mb/google/poppy: Add variant for AtlasDuncan Laurie
Add a new variant of Poppy for the Atlas board. BUG=b:75454415 TEST=tested on a P0 board. System boots and is mostly functional, though some peripherals are not ready so there are no touchpad/touchscreen devices configured yet. Change-Id: I5a0bccd1bda0134aa51885ac2c6e7bb5b45de924 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-29mb/google/octopus: Fix wifi configurationFurquan Shaikh
This change updates devicetree and GPIO configurations to match the schematics: 1. pcie_rp...[2] is the one being used for wifi, thus, clk_req and deemphasis_enable for [2] need to be set instead of [0]. 2. WLAN power enable, wifi disable and PERST# GPIOs need to be configured correctly. BUG=b:76180142 TEST=Verified that wlan0 scan works. Change-Id: Ic51a94902e2cac3491081ade32079e5b88719f45 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-03-28soc/intel/skylake: Limit xDCI feature when VBOOT is enabledDuncan Laurie
Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. To make the SOC behavior consistent the XdciEnable config option is removed in favor of direct control by devicetree.cb and the mainboards that had defined it were adjusted accordingly. This was tested on an Eve board with xDCI enabled in devicetree.cb to ensure the xDCI device is enabled in developer mode and disabled in normal mode. Change-Id: Ic3c84beac87452f17490de32082030880834501d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25365 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-28sb/intel/common: Add common code for SMM setup and smihandlerArthur Heymans
This moves the sandybridge both smm setup and smihandler code to a common place. Tested on Thinkpad X220, still boots, resume to and from S3 is fine so smihandler is still working fine. Change-Id: I28e2e6ad1e95a9e14462a456726a144ccdc63ec9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-03-28mainboard/google/meowth: Disable debug consent and enable S0ixVaibhav Shankar
This patch disables debug consent in the devicetree. When debug consent is set to DBC by default, it prevents some clocks from turning off during S0ix. This blocks S0ix entry. This patch also enables S0ix from the devicetree. BUG=b:76163091 TEST=enter S0ix and check if slp_s0 is asserted Change-Id: I05001a41b13e7784c34fa8f1f773fb94bbdcd01f Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/25312 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-28mb/google/poppy/variants/nami: Add SPD file for sona.Van Chen
Add SPD file for sdp samsung_dimm_K4A8G165WC-BCTD (ram id: 8). BUG=b:76086834 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: I49fa114f07ad2eef10f18de9f6c3380173681bdd Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25379 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-27mainboard/google/poppy: Add SPD for Hynix H9CCNNNCLGALAR-NUDDuncan Laurie
Add an SPD for this particular Hynix memory type to the poppy board so it can be used by poppy variants. BUG=b:75454415 Change-Id: I2249c7a4f2c83ec2b3266047a74b9bc22dad43be Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/25368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-27mb/google/octopus: Remove emmc tuning parameters from devicetreeFurquan Shaikh
Current emmc tuning parameters for octopus were copied over from other boards and result in failure to boot from emmc. This change gets rid of the emmc tuning parameters in devicetree. Once emmc tuning tests are run for octopus, these parameters can be added back. BUG=b:75986903 BRANCH=None TEST=Verified that octopus boots from eMMC without any errors in depthcharge. Change-Id: I7ac44a54afd1ecfe355a9654ac8e92133b67637f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-26mb/google/poppy/variant/nautilus: Turn off MIPI camera in PMOF methodSeunghwan Kim
This change remove work-around code for the power issue of MIPI and USB cameras on previous board revision. With the work-around code, PMOF ACPI method cannot turn off MIPI camera. So we need to remove it. BUG=b:74214248 BRANCH=poppy TEST=emerge-nautilus coreboot Change-Id: I7becaf61de364f82976ec0be7f8c9e4ef1a7aedd Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/25337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-26mainboard/google/cheza: Add support for ChezaT Michael Turney
TEST=build Change-Id: I32d185741ce20a3a82e6895de3026ade52d0bcc8 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-03-26mb/octopus: Set PNP config to PNP_PERF_POWERShaunak Saha
This patch sets the PNP config value to PNP_PERF_POWER. The config values for soc can be found in chip.h TEST = Build for octopus. Change-Id: I2239aa70cb708e6e1c06339ca9d517e7eaa198ed Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25310 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-24mb/google/octopus: Select TPM options only if mocktpm is not selectedFurquan Shaikh
This change adds a new Kconfig option for mainboard octopus "HAS_TPM" that auto-selects all TPM related options only if VBOOT_MOCK_SECDATA is not selected. BUG=b:76203913 TEST=Compiles fine with mocktpm. Change-Id: Ib28fc47a70be58cd9a9ec65ce3b1cda68d558437 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25340 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-23mb/google/zoombini: always report EC is in RO modeNick Vaccaro
Always report that EC is in RO mode. This is a temporary workaround for a hardware issue that is causing EC to appear to be in RW mode when it is not. This change will be reverted once transition is made to newer hardware. BUG=b:74215817 BRANCH=master TEST=Verify meowth can boot to recovery's insert screen. Change-Id: Ib3705bba0bb1f351da79e599566fbffab94428f3 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/25298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-22mb/google/zoombini: Enable NVMeNick Vaccaro
BUG=b:72120814 BRANCH=master TEST=none Change-Id: I64ab38dda78345c1f3d7d3f2bf3cb04c19290ceb Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/25256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-22mb/google/octopus: Add CLKREQ and de-emphasis settings for PCIe Wi-FIShamile Khan
BUG=b:73292699 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: Ic73ad38ad9a12bec614e530f7f35619246b9f57f Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25288 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-21mb/google/fizz: Enable I2C bus 2Zhongze Hu
I2C bus 2 goes to the custom add-in card slot and it was disalbed cuase it was idle. Google CFM add-in card is going to use this I2C bus so it needs to be re-enabled. BUG=b:73006317 TEST=Tested with add-in card on fizz hardware and verified I2C bus 2 is working properly. Change-Id: I2c9b5a9323fd51872e340c35005c4a3432716808 Signed-off-by: Zhongze Hu <frankhu@chromium.org> Reviewed-on: https://review.coreboot.org/25258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-03-21mb/google/octopus: Re-size flash WP_RO segmentSrinidhi N Kaushik
Update the size in WP_RO segment of the flash to accommodate builds using debug FSP. Change-Id: I0a0d1d0121b503ff390adf3ce25973d72e59fdeb Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/25253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-21mb/google/octopus: Create bip variantJustin TerAvest
This creates a bip variant for octopus. Nothing is set in the variant files here-- everything is picked up from baseboard. BUG=b:75976864 TEST=None Change-Id: I7a8ac3d8bb71416f05ef1a605684d92d5902abda Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25285 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-21mainboard/google/kahlee: Update GPIOs based on board IDMartin Roth
BUG=b:73078053 TEST=build & boot Grunt Change-Id: I2d4ba197b19c4948b867a61575e858b2a826a286 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-21mb/google/poppy/variants/nami: change type of board_sku_id() to uint32_tZhuohao Lee
Tools/scripts, like mosys/arc-setup, use int (4 bytes) to read the sku id. In order to support "-1", we need to use uint32_t (4 bytes) instead of using uint16_t (2 bytes) data type. Otherwise, tools/scripts will read 65535 instead of -1. Another reason to change this is that sku_id can be supported by ec up to 4 bytes. BUG=b:73792190 TEST=mosys output "Platform not supported" for -1 sku id arc-setup read -1 sku id Change-Id: Ib3baa8419f138abeb412ac09c2e7dc608e3b758b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/25252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-21mb/google/octopus: Enable TPM on GSPIRavi Sarawadi
BUG=b:73133848 BRANCH=None TEST=Build coreboot for Octopus board. Tested the GSPI interface with a SPI EEPROM and got correct response to a RDID command Change-Id: Ia10ab9da0055b54a96134a6e4c51b2a229a6fecf Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/24907 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-21mb/google/poppy/variant/nautilus: Enable CABC feature as defaultSeunghwan Kim
This change configures GPP_E22 to GPO_HIGH to enable CABC feature on nautilus board. BUG=b:68789889 BRANCH=poppy TEST=emerge-nautilus coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: Ifed0d37bf8147aa1b580f594f36f186051c2eb52 Reviewed-on: https://review.coreboot.org/25120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-21mb/google/kahlee: Add register address mapping for FCH MISCAkshu Agrawal
Audio machine driver will enable/disable clock by making it as a CCF clock in kernel. BUG=b:74570989 TEST=cherry-picked https://patchwork.kernel.org/patch/10291875/ on 4.14 kernel aplay -vv <file> check register to see clock enabled kill aplay check register to see clock disabled Change-Id: Ia553e55ffb358415067000d2d2d2744322d1c4db Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/25263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-20mainboard/google/kahlee: Initialize EC earlier in the bootblockMartin Roth
Set up the EC communication a little earlier so we can read the board ID before programming GPIOS. BUG=b:73078053 TEST=Build & Boot grunt, board_id() now gets ID correctly Change-Id: Icf3f598824cfed69fa03ba2bb86503bb3c3699a5 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25286 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-19mb/google/octopus: Configure PERST_0 pinJustin TerAvest
According to the schematic, Octopus boards have WLAN_PE_RST connected to GPIO_164. This change configures that properly in devicetree. BUG=None TEST=None Change-Id: I2ba4839e036f02c5e0316d08599894879133894a Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25248 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-19mb/google/octopus: Fix GPIO config for DRAM_IDsJustin TerAvest
The GPIO pad configurations for GPIO68-71 are incorrectly configured as outputs. This change corrects them to be inputs. BUG=b:74932341 TEST=None Change-Id: I319f8a64d83c29ed150316c15a8d429cc7c024f3 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25217 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-19mb/google/poppy: Config GPIO for DMIC by different sku idamanda_hwang
BUG=b:74177699 BRANCH=poppy TEST=Verify audio recorder function by different SKU ID Change-Id: Ic6570703f6ab4a1b03cbba8370fc0f597ab6bcf2 Signed-off-by: amanda_hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-19mb/google/octopus: Configure PCH_WP_OD early.Justin TerAvest
The GPIO for EEPROM write-protect should be configured early, before romstage. This change configures that pad earlier. This pad is the same on the existing Octopus schematics. BUG=None TEST=None Change-Id: Idf296ba6aad75b890afabd6f7c7c51fbaf911214 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-19mb/google/fizz: Enable VMXShelley Chen
We are enabling at the kernel level, but that is triggering an issue where FSP expects it to be disabled so it forces a cold reboot on every warm reboot, clearing the ramoops logs. Enabling in BIOS so it matches what the kernel expects. This is the same change that were done for eve: https://review.coreboot.org/#/c/22449/ BUG=None BRANCH=None TEST=echo PANIC > /sys/kernel/debug/provoke-crash/DIRECT check for /dev/pstore/console-ramoops Change-Id: Icd0bd01f5aee4c89f503eebba0808a1f3059e739 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-19soc/amd/stoneyridge/southbridge.c: Remove configure_stoneyridge_uartRichard Spiegel
The GPIO programming of configure_stoneyridge_UART() can be done by the early GPIO table, AOAC enabling was already removed. So configure_stoneyridge_uart() became redundant. Remove procedure configure_stoneyridge_uart(). BUG=b:74258015 TEST=Build and boot kahlee, observing serial output does not changes from previous serial output. Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25192 Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-17mb/google/octopus: Do not configure GPIO_149 as GPOFurquan Shaikh
GPIO_149 is used as ESPI clock feedback and configuring it as a GPO results in EC communication failure. This change removes the configuration of GPIO_149 as GPO in ramstage so that it remains configured for ESPI (as it was when AP came out of reset). BUG=b:75348718 Change-Id: Ie4f21b12fae027cdba54ce147e6d1a88ee854792 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-16soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin arrayFurquan Shaikh
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ# from mainboards instead of defining a separate property for each root port. This allows us to use memcpy to copy the entire array into FSP params as well as new properties for PCIe root ports can be added as arrays in future CLs. BUG=b:74633273 BRANCH=reef,coral Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-16mb/google/eve: Update DPTF parametersDuncan Laurie
1) Set the critical temperature threshold to 100C to match changes on other boards. This is intended to reduce DPTF-initiated thermal shutdowns before it has had a chance to react. 2) Reduce the CPU passive threshold sample rate from 5 seconds to 1 second so DPTF will react faster to rapid temperature increases. BUG=b:67459049 BRANCH=eve TEST=manual performance/power testing on Eve hardware Change-Id: Ib660dcb25422fea0aa692fac5ba65b49808965ba Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-15mb/google/poppy/variants/nami: Add gpio-keys ACPI node for PENHShelley Chen
Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. BUG=b:73121017 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: I5d87d938ac3a4e52e676850b9d8b80e83726275d Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-15mb/google/poppy/variants/nami: Use GPP_B4 as Touchscreen Power EnableShelley Chen
Touchscreen power enable for Nami has moved from GBB_C22 to GPP_B4 in the latest schematics. BUG=b:74347464 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: I3b1794d44f25c0d42d082d63b9e3ec3dfcef7528 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25154 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-15mb/google/octopus: Enable audio components.Shamile Khan
Octopus uses MAX98357A speaker amplifier and DA7219 codec. Add device tree entries and Kconfig settings for these components. BUG=b:73292699,b:73230879 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I27b5113677a8bd44dbbae587e27616d9e0b90d7f Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25117 Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-14mb/google/poppy/variants/baseboard: Add gpio-keys ACPI node for PENHNicolas Boichat
This change uses gpio_keys driver to add ACPI node for pen eject event. BUG=b:74413116 TEST=Verified using evtest that pen eject event results in events as expected. Change-Id: I6019d633f4337137bb9fbba770040cb5b30da773 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://review.coreboot.org/25147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-14mb/google/zoombini/variants/meowth: Make FPMCU interrupt level-triggeredVincent Palatin
Fix the IRQ configuration: it must be level-sensitive not edge-sensitive (and match the GPIO configuration). BUG=b:71986991 BRANCH=none TEST=on Meowth, /proc/interrupts shows 'IO-APIC 46-fasteoi chromeos-ec' then run 'ectool --name=cros_fp fpmode fingerup' and see the number of interrupts incrementing and the MKBP event happening. Change-Id: Iba8cff21d637fe6bf4ef5152fc01aaf98906477d Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/25110 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-14mainboard/google/meowth: Enable System Agent dynamic frequencyLijian Zhao
Enable System Agent dynamic frequency support by default. BUG=None TEST=Build and flash with debug version FSP, check SaGv in serial print to be set to "4". Change-Id: I7dd29db206b06e600407bb0b1d0bc7530f4ac93e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25093 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-13mb/google/octopus: Add yorp variantJustin TerAvest
This creates a yorp variant for octopus; nothing too interesting now, just picks up values from the baseboard. BUG=b:74443669,b:74067452 TEST=Build Change-Id: I55af8f02d33138a3b6bab7860a665e3deb5595c2 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25086 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-13mb/google/poppy/variants/nautilus: Enable SAR configsFurquan Shaikh
This change enables SAR configs when building with CHROMEOS option. BUG=b:74439919 Change-Id: I11a8fa04a77f688ed288780f2c605b8ac701f5a9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-13mb/google/poppy/variants/nami: Use internal pulldown for MEM_CONFIG_4Furquan Shaikh
Since nami proto did not have any external pull on MEM_CONFIG_4, use a weak internal pull down before reading it. BUG=b:74420123 TEST=Verified that the value read for MEM_CONFIG_4 is correct on nami. Change-Id: I45989d2ca35b863f391baba9e2f2e602033217d4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-12mb/google/octopus: Fix lpddr4 skusJustin TerAvest
The current lpddr4 skus entries do not match the RAMID table in the schematic. This commit updates that so they are consistent. Thankfully, the values are the same as for glkrvp, so I just copied from there. BUG=b:74392818 TEST=None Change-Id: I2e63ea0b27ef58038e5a37949c31a808989c98c2 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 17:24:42 +0000