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BUG=b:305793886
TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku
Change-Id: I167a02bf2219c6ef8e0093956a649305c8e8f76b
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add I2C config based on Deku schematics.
TPM is connected to I2C 4
BUG=b:305793886
TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku
Change-Id: I496e236531b2b59b320c77c36f542f4fa80a51a1
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78449
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add RAM id for:
MT62F2G32D4DS-026 WT:B (Micron)
BUG=b:305793886
TEST=Run part_id_gen tool without any errors
Change-Id: If2ed2bdcee44f6dbbda51a3ff484edaf3df4830d
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Now VBOOT is always assumed to run after romstage and be linked inside
romstage. This currently is the case but for flexibility reasons (e.g.
linking romstage into bootblock or having a verstage before romstage)
this could be more precise.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I361731c930a35e12245153920df1b6884d47064c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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A .data section now exists.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic1510221582aca91c814d43f522a8fb6cba05921
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78937
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove space to improve compatibility with OS drivers and various
tools, and to be consistent with other device names with the 360
suffix.
TEST=build/boot Windows/Linux on Akali360, verify audio functional.
Change-Id: Ib9b909dba939f726e6fbe71f5b4956b432086029
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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1.In contrast to the MediaTek Wi-Fi module, the Intel Wi-Fi module needs to load a SAR table.
2.Describe the FW_CONFIG probe for the settings on marasov.
- WIFI_SAR_ID_0 for MTK Wi-Fi module MT7921L
- WIFI_SAR_ID_1 for Intel Wi-Fi module AX211NGW
BUG=b:300045956
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Change-Id: I5b5c6bea6c2c916fb682044218ec7b3a5d2659f6
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77789
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Enable FW_CONFIG for corsola so that the information can be passed to
payloads via coreboot tables.
BUG=b:157692450
TEST=emerge-corsola coreboot
BRANCH=none
Change-Id: I6c12041d3666907c884f5a50a12c1433c2085961
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Currently, there are 3 separate settings for DPTF which are not always
in sync:
- the enabled/disabled state of the devicetree PCI device
- the 'dptf_enable' register, which sets the ACPI device status via GNVS
- the 'DptfDisable' register, which sets the FSP UPD of the same name
To make things sane, drop the two chip registers, and set the GNVS
variable and FSP UPD based on the enabled/disabled status of the DPTF
PCI device in the mainboard's devicetree.
TEST=build/boot google/cyan (edgar). Verify that the PCI and ACPI
devices are present/enabled when DPTF is enabled in devicetree, and not
present/disabled when disabled in devicetree.
Change-Id: I8fc1b63eda0dc2e047d9cb1e11a02d41ab8b2ad7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Change the LAN/WiFi device types from PCI to generic, so that the bogus
PCI device and function values don't end up in coreboot's internal
device tree. The presence of these bogus PCI devices cause the LPI
constraint generator to create a reference for an ACPI device which does
not exist (SB.PCI0.RP{xx}.MCHC). The invalid reference(s) cause a
Windows BSOD (INTERNAL_POWER_ERROR).
TEST=build/boot Win11 on google/puff (wyvern). Verify LAN/WLAN devices
function correctly under Windows and Linux.
Change-Id: Ibc5f96250edb358d0517bd3840bf5604defe0b39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned, and devicetree does not currently support this (it
disables all probed devices when fw_config is unprovisioned).
BUG=b:305887856
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I5993049ac63520c4dfd057c38b566fc69502d825
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change the dGPU/LAN/WiFi device types from PCI to generic, so that the
bogus PCI device and function values don't end up in coreboot's
internal device tree. The presence of these bogus PCI devices cause the
LPI constraint generator to create does a reference for an ACPI device
which does not exist (SB.PCI0.RP{xx}.MCHC). The invalid reference(s)
cause a Windows BSOD (INTERNAL_POWER_ERROR).
TEST=untested
Change-Id: Ic997b5ad893853b99ae53a2e5c7acf58467ea4f1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78873
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add fingerprint SPI, and power off FPMCU during romstage.
BUG=b:305860604, b:306320063
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot, measure evtest can detect and check device probed in kernel log
Change-Id: Ic7b9e29ca3cb9352fe098156924fde2719399a79
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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On guybrush, keyboard presses are signaled by the EC via eSPI virtual
wire. The interrupt is shared with others and should be active low.
From 74bce48f1d4 ("mb/google/{zork,guybrush,skyrim},soc/amd/espi: Fix vw_irq_polarity"):
> The default state for the IRQ lines when the eSPI controller comes
> out of reset is high. This is because the IRQ lines are shared with
> the other IRQ sources using AND gates. This means that in order to
> not cause any spurious interrupts or miss any interrupts, the
> IO-APIC must use a low polarity trigger.
Setting `vw_irq_polarity` in the device tree provides an option to
invert interrupts from the eSPI controller, but the register is
initialized from verstage which is baked into RO.
As a workaround, the necessary interrupts on the EC have been
reconfigured to be active low, and we can modify the IO-APIC
accordingly.
EC related CL here: https://crrev.com/c/4891663
BUG=b:218874489
TEST=-`emerge-guybrush chromeos-ec coreboot chromeos-bootimage`
-Flash new RW fw and verify keyboard is functional
-`suspend_stress_test -c 1` and verify i8042 irq is removed as a
wake source
-`echo mem > /sys/power/state`. Press key and verify system wake
from i8042.
Cq-Depend: chromium:4891663
Change-Id: I7d093d94a666263684645ef724e945069c68c806
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Change the WiFi device type to generic, so that the LPI constraint
generator does not create a reference for a device which does not
exist in ACPI (SB.PCI0.RP14.MCHC). The invalid reference causes
a Windows BSOD.
TEST=build/boot Win11 on google/hatch (akemi)
Change-Id: Ieab0722a81f0952bb5b6df8e60c4d684ff455418
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78543
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds the required FMD changes to support the change
in cse_lite 'commit Ie0266e50463926b8d377825 ("remove
cbfs_unverified_area_map() API in cse_lite")' for CBFS verification.
With the change in cse_lite the ME_RW_A/B blobs are now part of
FW_MAIN_A/B and corresponding entries in FMD can be removed for boards
that currently use them.
BUG=b:284382452
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I3ca88fee181f059852923d50292b24c0e5b9fd6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Enable FW_CONFIG for geralt so that the information can be passed to
payloads via coreboot tables.
BUG=b:157692450
TEST=emerge-geralt coreboot
BRANCH=none
Change-Id: I8898143f44d2ffda3cb1708c2d7efadc289303a1
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Add data.vbt file for quandiso recovery image. Select INTEL_GMA_HAVE_VBT
for quandiso as it has a VBT file now. The VBT file is copied from
chromeos internal source and based on yaviks VBT.
BUG=b:296506936
TEST=emerge-nissa coreboot
Change-Id: Ia9f84b4f56171737a9e7a513b63549b3013775c4
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77588
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Shawn Ku <shawnku@google.com>
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The codec alc5650 has different setting from other amp codec in
depthcharge. Since nissa has a single shared depthcharge target,
add the fw_config field to allow different audio_configs.
(refer to chromium:4983866)
BUG=b:307410704
TEST=With depthcharge change, set fw_config and gbb flags on craaskana
and check beep sound on firmware screen is workable.
Change-Id: I7446fce57557204d91151f1a31755381c1813c6f
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78791
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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During warm reboot, NVMe is not detected with non-serial image
sometimes while there is no issue with serial image. This change
toggles NVMe PWR pin as soon as in early stage to make NVMe ready
sooner.
BUG=b:260547988
BRANCH=None
TEST= Build rex0 and try warm reboot from OS console. Check if
the platform with Micron SSD boots to OS again without an issue.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I2f34e3f49e7fc388198ff85c8e119cb3f242a60e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Intel has identified an idle hang issue on pre-prod silicon that will
not be fixed or root-caused. To avoid the issue, this commit sets
SaGvWpMask to SAGV_POINTS_0_1_2 in the devicetree.
Note: This change will affect system power.
BUG=b:287170545
TEST=Able to idle for more than 5+ hours without any hang on
google/screebo.
Change-Id: Id0b8db0076d983d336c3bec6d6c33614c69964d1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78794
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Windows doesn't have / will likely never have a signed driver for the
FPR, so set the device status as hidden so it will not appear as an
unknown device in Windows Device Manager. Linux does not check/care
about the ACPI device status.
TEST=build/boot Win11 on google/brya (kano), verify FPR does not show
up as unknown device under Device Manager.
Change-Id: Ie73fd9d448ecca9e9112abc0d92b4ab46ce3618d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Windows doesn't have / will likely never have a signed driver for the
FPR, so set the device status as hidden so it will not appear as an
unknown device in Windows Device Manager. Linux does not check/care
about the ACPI device status.
TEST=build/boot Win11 on google/hatch (jinlon), verify FPR does not
show up as unknown device under Device Manager.
Change-Id: Ia4a908afdabad0ae8db45c4731a00c9cb17b42bb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch disables FVM for IA and SA VRs as per the OEM requirement.
BUG=b:307237761
TEST=Able to build and boot google/screebo.
Change-Id: Icb0611331ac7090d11d646a5ad5201593a90aacb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch allows google/rex mainboard to choose between "Performance"
(PL_PERFORMANCE) and "Baseline" (PL_BASELINE) power limits (PLs).
This is important for platform to meet balance between power and
performance.
The OEM design google/screebo selects baseline power limit to maintain
the balance performance in lower power.
BUG=b:307237761
TEST=Able to build and boot google/screebo.
w/o this patch:
screebo4es-rev1 ~ # cbmem -c -1 | grep "CPU PL"
[INFO ] CPU PL1 = 15 Watts
[INFO ] CPU PL2 = 57 Watts
[INFO ] CPU PL4 = 114 Watts
w/ this patch:
screebo4es-rev1 ~ # cbmem -c -1 | grep "CPU PL"
[INFO ] CPU PL1 = 15 Watts
[INFO ] CPU PL2 = 40 Watts
[INFO ] CPU PL4 = 84 Watts
Change-Id: I43debc5442ae9c01851652beba676ffc102ca27d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Switch palkia overridetree to use chipset devicetree references.
Change-Id: Ic5fd2d139d22824d3ada09325022c37e69b5e2a9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Switch nightfury overridetree to use chipset devicetree references.
Drop USB port overrides which are identical to the baseboard.
Change-Id: I9bb028ad12b97fd4510f6d1026fdc16232c64dba
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78570
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Switch mushu overridetree to use chipset devicetree references.
Change-Id: Iac05b0b2c5785f2cb69a29aa4d4c3088f164385f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Switch kohaku overridetree to use chipset devicetree references.
Drop USB port overrides which are identical to the baseboard.
Change-Id: Idcfde6882fc433e6a248aff6baf23b1a5bf7d201
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Add a new Krabby follower 'Chinchou'.
BUG=b:307161347
TEST=make # select Chinchou
Change-Id: Ic90f85621598ab253d3ec9fe44aa076712248223
Signed-off-by: wuyang5 <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78596
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DDR interfaces emit electromagnetic radiation which can couple
to the antennas of various radios that are integrated in the system,
and cause radio frequency interference (RFI). The DDR Radio Frequency
Interference Mitigation (DDR RFIM) feature is primarily aimed at
resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies
for the Wi-Fi high and ultra-high bands (~5-7 GHz).
This patch sets CnviDdrRfim UPD and enables CNVI DDR RFIM feature
for Craask variant.
Refer to Intel doc:640438 and doc:690608 for more details.
BUG=None
BRANCH=None
TEST=Build and boot Craask.
- Verified that Wifi DDR RFIM Feature is enabled and DDR RFI table can be modified.
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: I5560bbedb26e88edd9d35f16b639fe63ef42c30e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patches privides settings based on 2+8 15w.
BUG=b:306543967
TEST=boot on rex with 2+4 SOC and power limit settings are overridden
correctly in variant_update_cpu_power_limits
Change-Id: I0560e44ce8e0d91bb5fb9c7cc9ffe68ab050bf00
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78688
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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GPP_B17 (aka. EN_WWAN_PWR) should be kept low when the device does not
have a WWAN module.
TEST=Power consumption drops to 0 in S0iX
Change-Id: I95150c20c98b037a47827a7b83e4373c6e9070e3
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78684
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Update overridetree for ILI2901 and eKTH7B18U touchscreen.
BUG=b:299284564, b:298328847, b:299570339
TEST=emerge-brya coreboot
Change-Id: Ib45f3c7c92ea525ca13a6137dd87eeb318f30384
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
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Alphabetize board entries, Kconfig selections, and config options.
Change-Id: I94e6e584809888fc9cab1b4cff6c0368803c1d47
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: I6843fd2eb752cd35d8c67ad7487f6dbb1c1afc62
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78707
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Alphabetize board entries, Kconfig selections, and config options.
Change-Id: I599eda8c136d072471f022be9397faeb0e061472
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78706
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Alphabetize entries and add consumer product names for boards where
available.
Change-Id: I22a18ba85d6ff203765f984fba51784757a2a4df
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78705
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Alphabetize board entries, Kconfig selections, and config options.
Reverse default logic of PERFORM_SPL_FUSING for simplicity / clarity.
Change-Id: Ib25bb8c7bbf994f2f0675c4599c70a7db5d9f7ef
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Alphabetize entries and add consumer product names for boards where
available.
Change-Id: I7459ee0a63025c12c7dbe75c578c7496c49fa475
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78703
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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This patch introduces a dedicated devicetree.cb file for platforms
built with pre-production SoC. This will help to keep the SoC
configuration separate for platforms with ESx and QSx silicons.
For example, the SaGv WP configuration is different between
pre-production (aka ESx) and production (aka QSx) silicon.
BUG=b:306267652
TEST=Able to build and boot google/rex4es.
Change-Id: I01b0abeeb25ce5a83882c56b30929228fcc6c95c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Mike Lee <mike5@huaqin.corp-partner.google.com>
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For variants without a digitizer, disable I2C2.
For variants without a proximity sensor, disable I2C3.
For variants without a fingerprint reader, disable SPI1.
For all variants, disable I2C5 as it is unused.
Adjust comment blocks as needed.
Change-Id: I27e9eb2b0dcc869d1964c0b17c656d6691c0f05e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78553
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Switch jinlon overridetree to use chipset devicetree references.
Change-Id: I663a1d051d287f8484c5d4d175337f4f24081044
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Switch kindred overridetree to use chipset devicetree references.
Change-Id: I2c54406948d2db53d25aa7c3dc79cfb5661c4a69
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78564
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow thermal validation, override tdp pl1 in 6w ADL_N platform to
10w and override tdp pl1 in 15w ADL_N platform to 20w.
BUG=b:307365403
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I8dd743e65b9e5fbd6aa2fd9c1b87c7bd487c8174
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78650
Reviewed-by: ChiaLing <chia-ling.hou@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
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This patch adds the required FMD changes to support the change
in cse_lite 'commit Ie0266e50463926b8d377825 ("remove
cbfs_unverified_area_map() API in cse_lite")' for CBFS verification.
These blobs were kept separate originally to avoid hash loading and
verification every time and hence save boot time.
With the change in cse_lite the ME_RW_A/B blobs are now part of
FW_MAIN_A/B and corresponding entries in FMD can be removed.
BUG=b:284382452
TEST=Build CB image for google/rex board and test CSE FW
update/downgrade with CONFIG_VBOOT_CBFS_INTEGRATION config enabled.
Also confirm there is no increase in boot time with this change.
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I56865a9e5c8b5f9e908e00e1a7e7e187d5d6a2f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Checking in gpio.c generated by arbitrage. Used this command line to
generate:
arb export-coreboot-gpio --refdes=U1 brox:proto1_20231017
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I1098bd4cfde393ed9e78cd90158c3534fdf0dc09
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78657
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Skolas is actually using the SOC_INTEL_ALDERLAKE_PCH_P config, so
fixing Brox to reflect this as it's using the same SoC.
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I632ec055d523956983d2053cd8e7000b1eaabf92
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78656
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Switch baseboard devicetree to use chipset devicetree references.
Drop any devices whose status (on/off/hidden) matches the default
in the chipset DT.
TEST=build/boot google/hatch (akemi)
Change-Id: I5954c304f3c0e04be7e061c1c23a278f81b6ff4d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Switch helios_diskswap overridetree to use chipset devicetree references.
Change-Id: I0a3385139c74a59c2006b8963850d00ee39f70a8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78560
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Switch helios overridetree to use chipset devicetree references.
Change-Id: If7901066a0c77231779eb298dc40962d8ac62814
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Switch hatch overridetree to use chipset devicetree references.
Change-Id: Icccb433ba3e5a1ecb192f8db830674047e801623
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Switch dratini overridetree to use chipset devicetree references.
Change-Id: I9f365077291ee9fa5f4dcf8835756f4cfd6eeab4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Switch akemi overridetree to use chipset devicetree references.
Drop USB port overrides which are identical to the baseboard.
TEST=build/boot google/hatch (akemi)
Change-Id: Ic25fbe4a634f8166047107a33c9fcee764f1159a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78552
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add FP enable/disable based on SKU ID for Morphius. This is meant
to resolve a UMA issue with Morphius devices that had the FPMCU
populated on non-fp devices. Since the FPMCU is present, and the
firmware enables the power GPIO's based on variant, not SKU, the
devices were reporting data on fingerprint errantly.
BUG=b:258040377
TEST=Flash to Morphius, test FP.
Disable test SKU, flash on Morphius, test FP.
Change-Id: If5794a9a1b7eb3daaa4cdfd1354dfb0c688624fd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78622
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Simplify audio overrides for dalboz baseboard-based variants by using
device aliases. This prevents duplicate ACPI devices from being
generated for the ChromeEC i2s tunnel (which causes Windows to BSOD
with an ACPI_BIOS_ERROR).
TEST=build/boot Win11 on google/zork (vilboz), dump ACPI tables
and verify only one EC tunnel device in SSDT.
Change-Id: I56aa2f761843aa269620f7e8c89ae9c0f205f349
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78509
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is only a single i2c tunnel bus for audio from the EC, so all
attached devices need to exist under a single device attached to that
bus. This change will facilitate cleanup/simplification using device
aliases in a subsequent commit.
TEST=tested with rest of patch train
Change-Id: Ie09c682a7419868d39421574568dff1a651fa0dc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78626
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move all security patch level (SPL) related Kconfig options to the
common AMD PSP Kconfig file. Commit 4ab1db82bb30 ("soc/amd: rework SPL
file override and SPL fusing handling") already reworked the SPL
handling, but missed that another Kconfig option
SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL controlled if the PSP mailbox command
to update the SPL fuses was sent by the code that got added to the build
when PERFORM_SPL_FUSING was selected.
To make things less unexpected, rename PERFORM_SPL_FUSING to
SOC_AMD_COMMON_BLOCK_PSP_SPL since it actually controls if the SPL
support code is added to the build and also rename
SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL to PERFORM_SPL_FUSING. This changes
what PERFORM_SPL_FUSING will do from including the code that could do
the fusing if another option is set to being the option that controls if
the fusing mailbox command will be set. All SoCs that support SPL now
select SOC_AMD_COMMON_BLOCK_PSP_SPL in their Kconfig, which won't burn
any SPL fuses.
The logic in the Skyrim mainboard Kconfig file is reworked to select
PERFORM_SPL_FUSING for all boards on which the SPL fuses should be
updated; on Guybrush PERFORM_SPL_FUSING default is changed to y for all
variants. The option to include the code that checks the SPL fusing
conditions and allows sending the command to update the SPL fuses if the
corresponding Kconfig is set doesn't need to be added on the mainboard
level, since it's already selected at the SoC level.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I12fd8775db66f16fe632674cd67c6af483e8d4e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Change-Id: I72ef272e48db7683a3170e157edd0a782143e8aa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Select ACP audio for kahlee since it's located on the GPU.
TEST: build/boot careena to Win10. Observe audio device shows up
Change-Id: I51527a1bfae3e12ce5cf1da8a3465bbc9ddfa76e
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78406
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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BUG=b:305793886
TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku
built without errors.
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I332e404e82a7980bb8ed1fb084fe957f526f81d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78393
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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It's not needed to put a backslash at the end of a line for quoted
multiline values. Thus, remove it.
Change-Id: I1b83d53598ba2adeed853a96d6c2c1a21f01a9f7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78576
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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For Sandy Bridge boards with MRC raminit support, migrate as much
MRC settings to devicetree as possible, to stop mainboard code from
needlessly overwriting entire PEI data structure, so they will not
interfere with upcoming transition to one standard Haswell way of
providing SPD info to northbridge.
Some exceptions allowed are described below and in code comments.
SPD-related items are kept out of devicetree for now. They will be
migrated (with a different representation) with the Haswell SPD
transition.
google/{butterfly,link,parrot,stout} have max DDR3 frequency set in
pei_data to 1600 (2*800), but in devicetree to 666. The reason for the
difference seems to be problems with native raminit code. These are
converted into ternaries tied to CONFIG_USE_NATIVE_RAMINIT, with an
added "fix me" tag. asus/p8x7x-series also needs the same treatment,
based on testing various memory on p8z77-m hardware.
TEST=Builds on all affected boards. asus/p8z77-m still works with multiple RAM modules tested.
Change-Id: Ie349a8f400eecca3cdbc196ea0790aebe0549e39
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Adjust the STT settings.
BRANCH=none
BUG=b:270112575
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the thermal team has verified.
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I1df9bbf820b5a760007dcfd7bceb21063fc24696
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78523
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Replace all remaining numeric references to PCI devices with their
aliases in chipset.cb.
Change-Id: I636f04c06c250639867c770511095773cb0c5205
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Utilize the SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF to provide the Windows
driver with information on backlight settings.
TEST: Boot google/careena to Win10. Observe display brightness controls
functional after driver loads (immediately with patched driver,
30 minutes with unpatched).
Change-Id: I6792a91f26a5f6e4dc478cdde776ff749f08946f
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78429
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Default SD card interface (PCI 14.5) to off in the baseboard, and have
all variants which use it enable it in their override tree. This will
allow for simplification when moving to using the chipset devicetree
references in a later patch.
Change-Id: I6e1230045f54e0fee376f5eeeca9da4fb9d5f6c4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Yuchen He <yuchenhe126@gmail.com>
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Default I2C3 (proximity sensor) to off in baseboard, since all variants
which use one already enable it in their override tree. This allows
variants which do not use it (the majority) to drop it from their
override trees.
Change-Id: If17cb4538a7f64d019e4e28285fb8977de72252f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Yuchen He <yuchenhe126@gmail.com>
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Default I2C2 (digitizer) to off in the baseboard, since all variants
which use one already enable it in their override tree. This allows
variants which do not use it (the majority) to drop it from their
override trees.
Change-Id: Ife42a6b849278362c1951b80b7a95363e68a2541
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78548
Reviewed-by: Yuchen He <yuchenhe126@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
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Default GSPI1 (fingerprint reader) to off in baseboard, since all
variants which use one already enable it in their override tree.
This allows variants which do not use it to drop it from their
override trees.
Change-Id: I07979e35b67635ceadd3906e37de177dd081d35a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78547
Reviewed-by: Yuchen He <yuchenhe126@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This signal gets deasserted by the WWAN modem to reactivate the PCIe
link when in low power mode. In order to handle this efficiently, the
kernel needs to set up an interrupt.
BUG=b:301150499
TEST=Compiled and tested on google/redrix
Signed-off-by: Paweł Anikiel <panikiel@google.com>
Change-Id: I37f6836aefe4a374eaff3e4bc11358be274cf563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78416
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Vendor DRAM Part Name Type
MICRON MT62F512M32D2DR-031 WT:B LPD5
HYNIX H9JCNNNBK3MLYR-N6E LPD5
HYNIX H9JCNNNCP3MLYR-N6E LPD5
MICRON MT62F1G32D4DR-031 WT:B LPD5
HYNIX H9JCNNNFA5MLYR-N6E LPD5
MICRON MT62F2G32D8DR-031 WT:B LPD5
SAMSUNG K3KL6L60GM-MGCT LPD5x
MICRON MT62F1G32D2DS-026 WT:B LPD5x
SAMSUNG K3KL8L80CM-MGCT LPD5x
HYNIX H58G56BK7BX068 LPD5x
MICRON MT62F2G32D4DS-026 WT:B LPD5x
SAMSUNG K3KL9L90CM-MGCT LPD5x
HYNIX H58G66BK7BX067 LPD5x
BUG=b:304920262
TEST=Run part_id_gen tool without any errors
Change-Id: I2968c2f0b9cdd55235f9833a3d3cdb3c83b8601b
Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Follow thermal team request, modify tcc_offset from 20 to 10.
BUG=b:306548525
TEST=Build and verified by thermal team
Change-Id: I7537e103be4cd1196c934ca72dbd61e064aed371
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
|
|
Some Type-C monitors do not immediately assert HPD. If we enter FSP-S
before HDP is asserted, display initialisation may fail. So wait for
HPD.
This is similar to commit b40c6009141e ("mainboard/hatch: Fix puff DP
output on cold boots") on puff, except we don't use
google_chromeec_wait_for_displayport() since that EC command was removed
for TCPMv2 (https://crrev.com/c/4221975). Instead we use the HPD signals
only. By waiting for any HPD signal (Type-C or HDMI), we skip waiting if
HDMI is connected, which is the same behaviour as puff and fizz.
BUG=b:303533815
BRANCH=dedede
TEST=On dexi, connect a display via a Type-C to HDMI dongle and check
the dev and recovery screens are now displayed correctly. Also check the
logs in the following cases:
Cold reboot in dev mode, Type-C to HDMI dongle:
HPD ready after 800 ms
Warm reboot in dev mode, Type-C to HDMI dongle:
HPD ready after 0 ms
Cold/warm reboot in dev mode, direct Type-C:
HPD ready after 0 ms
Cold/warm reboot in dev mode, direct HDMI:
HPD ready after 0 ms
Cold/warm reboot in dev mode, no display:
HPD not ready after 3000 ms. Abort.
Change-Id: Ib4fc071cac98a542072ffbeb6943bff4c988554c
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78450
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update overridetree to correct FP_MCU fw_config settings.
BUG=b:299284564, b:298328847, b:299570339
TEST=emerge-brya coreboot
Change-Id: If76dd8fa3567ed01b11a6d2ba796e8c39807816c
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78454
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update overridetree for TouchPad.
BUG=b:299284564, b:298328847, b:299570339
TEST=emerge-brya coreboot
Change-Id: I4f88fa8a34b65aaeb64746e7f02e82d9913ce21b
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78455
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Set the following register value to make SX9324 work normally
"ph0_pin" = "{1, 3, 3}"
"ph1_pin" = "{3, 2, 1}"
"ph2_pin" = "{3, 3, 1}"
"ph3_pin" = "{1, 3, 3}"
"ph01_resolution" = "512"
"ph23_resolution" = "1024"
"startup_sensor" = "1"
"ph01_proxraw_strength" = "2"
"ph23_proxraw_strength" = "2"
"avg_pos_strength" = "256"
"cs_idle_sleep" = ""gnd""
"int_comp_resistor" = ""lowest""
"input_precharge_resistor_ohms" = "4000"
"input_analog_gain" = "3"
BUG=b:295109511
BRANCH=None
TEST=emerge-nissa coreboot chromeos-bootimage & Check sar sensor data
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: Ib15f12d754fec8b379afd702b27d0701fac78072
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Use human readable properties as upstream driver support.
BUG=b:297977526
TEST=Able to get sensor values changed w/wo a hand covering the device.
before this CL , SSD.dsl of STH9324
Package (0x02)
{
"semtech,ph0-pin",
Package (0x03)
{
Zero,
Zero,
Zero
},
...
Package (0x02)
{
"semtech,ph23-resolution",
Zero
},
Package (0x02)
{
"semtech,startup-sensor",
Zero
},
....
after this CL , SSD.dsl of STH9324
Package (0x02)
{
"semtech,ph0-pin",
Package (0x03)
{
One,
0x02,
0x02
},
...
Package (0x02)
{
" semtech,ph23-resolution",
0x0400
},
Package (0x02)
{
"semtech,startup-sensor",
One
},
Change-Id: Ie0d929228f4510f33b07d9c4cfdfcd2a9a437c27
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78174
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
|
|
Update Goodix touchpad HID to GDIX0000 for GXTP7288 and GXTP7863.
BUG=b:305118852
BRANCH=firmware-dedede-13606.B
TEST=Build and touchpads are workable
# evtest for GXTP7863
No device specified, trying to scan all of /dev/input/event*
Available devices:
/dev/input/event0: Lid Switch
/dev/input/event1: Power Button
/dev/input/event2: AT Translated Set 2 keyboard
/dev/input/event3: cros_ec_buttons
/dev/input/event4: Elan Touchscreen
/dev/input/event5: GDIX0000:00 27C6:0D51 Mouse
/dev/input/event6: GDIX0000:00 27C6:0D51 Touchpad
# evtest for GXTP7288
No device specified, trying to scan all of /dev/input/event*
Available devices:
/dev/input/event0: Lid Switch
/dev/input/event1: Power Button
/dev/input/event10: GDIX0000:00 27C6:01F5 Touchpad
/dev/input/event11: sof-da7219max98360a Headset Jack
/dev/input/event12: sof-da7219max98360a HDMI/DP,pcm=2
/dev/input/event13: sof-da7219max98360a HDMI/DP,pcm=3
/dev/input/event14: sof-da7219max98360a HDMI/DP,pcm=4
/dev/input/event2: AT Translated Set 2 keyboard
/dev/input/event3: cros_ec_buttons
/dev/input/event4: ELAN900C:00 04F3:2E5D
/dev/input/event5: ELAN900C:00 04F3:2E5D UNKNOWN
/dev/input/event6: ELAN900C:00 04F3:2E5D UNKNOWN
/dev/input/event7: ELAN900C:00 04F3:2E5D Stylus
/dev/input/event8: ELAN900C:00 04F3:2E5D Stylus
/dev/input/event9: GDIX0000:00 27C6:01F5 Mouse
Change-Id: Id2a6223bdbb2f0693149136baa853ca2efb57815
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Enable RO verification by GSC and RO/RW CBFS verification.
BUG=b:277087492
TEST=Build and boot to OS in Myst with CBFS verification enabled using
PSP verstage.
Change-Id: I2dd3ce59f331f89660185309ccf60c53d50e4fad
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78235
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
This reverts commit 55b7dee2784e9fe80870c6c33ba91b98021df8b5.
Reason for revert: accidentally submitted out of order / breaks tree
Change-Id: Ic15d0e3688cd54f7d678998341263e7bd30e75f2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78525
Tested-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Enable sending EOP from payload
BUG=b:279184514
TEST=Verify sending EOP from depthcharge on google/rex
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I5eda0a5c6d4c34cfcc2de898adde0b005d6edc1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74768
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable EC keyboard backlight for dochi.
BUG=b:299284564
TEST=FW_NAME=dochi emerge-brya coreboot chromeos-bootimage
Change-Id: I1b640c576fcdd368110b88cba6f969f10dfc15f1
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
GPP_H04/GPP_H05 doesn't use for I2C usage, remove I2C2 "on" settings.
BUG=b:294155897
TEST=Check ap firmware log, i2c2 is disabled
Change-Id: I0124fd108fbbd87507d252e9caab4dfc16aceddb
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78339
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update SaGv gears and frequency values as per recommendation
from power and performance team. This change doesn't cause
negative impact on firmware boot time performance.
BUG=b:274137879
TEST=Verified the settings on google/rex using debug FSP logs.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ie8a81c05f25b1cdab1008d09c606d1debea6e6e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Windows does not use these devices for audio. Hide these so they don't
clutter device manager.
Change-Id: Ic85eff7f7ff68e25cc005bbb822bf99374c96532
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78418
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use 2 gpio for stylus detect and wake function.
GPP_E04 is the IRQ source, and GPP_E09 is the wake source.
BUG=b:304680060
TEST=Build and test on karis, stylus detect function works
Change-Id: I7a83326f76932c8e501e6369bb845fc7236291b4
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78336
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use runtime detection for touchscreens.
BUG=b:289962599
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Ia43ada8b3b6dbee95dbadacc353106e0f8f37549
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Based on schematics and confirm with EE to remove TOF function.
BUG=b:290891557
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I1ae6a6562d87f8da5f41691a7606a1aa10989443
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78147
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enabling support of WiFi SAR table for all rex variants by
setting the option at baseboard level.
BUG=b:290689824
TEST=emerge-rex coreboot
Change-Id: I17709cb5d75b56c6c1f386ab527c5c8730011bed
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78308
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Sync'ing Karis' FW_CONFIG definitions stored in CBI,
```
_FW_MASKS = struct(
DB_USB = 0x00000003, # bit1~bit0
STYLUS = 0x00000004, # bit2
AMP = 0x00000038, # bit5~bit3
FAN = 0x000000C0, # bit7~bit6
MIPI_CAM = 0x00000300, # bit9 ~ bit8
FP_MCU = 0x00000C00, # bit11 ~ bit10
KB_TYPE = 0x00001000, # bit12
WIFI_TYPE = 0x00002000, # bit13
)
_FW_CONFIGS = struct(
DB_USB_UNKNOWN = hw_topo.make_fw_config(_FW_MASKS.DB_USB, 0),
DB_USB4_ANX7452 = hw_topo.make_fw_config(_FW_MASKS.DB_USB, 1),
STYLUS_ABSENT = hw_topo.make_fw_config(_FW_MASKS.STYLUS, 0),
STYLUS_PRESENT = hw_topo.make_fw_config(_FW_MASKS.STYLUS, 1),
AUDIO_ALC5650 = hw_topo.make_fw_config(_FW_MASKS.AMP, 0),
FP_MCU_ABSENT = hw_topo.make_fw_config(_FW_MASKS.FP_MCU, 0),
FP_MCU_NUVOTON = hw_topo.make_fw_config(_FW_MASKS.FP_MCU, 1),
FP_MCU_ELAN = hw_topo.make_fw_config(_FW_MASKS.FP_MCU, 2),
WIFI_TYPE_CNVI = hw_topo.make_fw_config(_FW_MASKS.WIFI_TYPE, 0),
WIFI_TYPE_PCIE = hw_topo.make_fw_config(_FW_MASKS.WIFI_TYPE, 1),
MIPI_UF_CAM_HI556 = hw_topo.make_fw_config(_FW_MASKS.MIPI_CAM, 0),
)
```
BUG=b:290689824
TEST=emerge-rex coreboot
Change-Id: I1e4965c009edc595f24c04ac82d81aa0e723bbf3
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78261
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
WiFi SAR table for karis will be place into the CBFS later on and
as a result adding the hook in coreboot to make use of the SAR
table once the table is available.
BUG=b:290689824
TEST=emerge-rex coreboot
Change-Id: Ic989024ab9eb0fc439fc701c335a85986c4cfec5
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78260
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update default fan settings(FAN_SETTING_1) in FAN field.
Bit 6-7, FAN, 0 --> FAN_SETTING_1
BUG=b:290689824, b:294155897
TEST=Dump ssdt table and check fan settings is existed
Change-Id: Id69ec67202b5d769cd3a9a68344a6d8913ebd78b
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Commit 9b230ae2955 introduced a redefinition of the config option
`BOARD_GOOGLE_BROX`, which is already defined in Kconfig.name
accordingly and thus causing a Kconfig warning. Fix that by removing the
type redefinition.
Change-Id: Iea6219a686a23d8d48a0bfb6ac642efd482fded9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78394
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Configure GPIOs according to schematics revision 20231013.
BUG=b:299284564, b:298328847, b:299570339
TEST=emerge-brya coreboot
Change-Id: I1ccab46b9f622fb98920d316c31800f39dc8ff95
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78384
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Create the anraggar variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:304920262
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_ANRAGGAR
Change-Id: I95e72188679fc825c94c4043ed02b0aad310c6a3
Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Disable SD card GPIO with fw_config for quandiso units without SD
card and pull GPP_H12 to high to match the spec.
BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Iad6789d42b9a3f9b979fd481a88cc7d69db2dcfe
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Shawn Ku <shawnku@google.com>
|
|
When battery level is below critical level or battery is not present,
cpus need to run with a power optimized configuration to avoid platform
instabilities. This will check the current battery status and configure
cpu power limits properly.
BUG=b:296952944
TEST=Build rex0 and check cpu power limits are configured with
a performance efficient configuration and the platform boots to OS if
battery level is above the critical level. And check cpu power limits
are configured with a power optimized configuration and boots to OS
without an issue if battery is not present or battery level is at or
below critical level.
Change-Id: I12fd40abda76c8e7522b06a5aee72665f32ddec8
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78322
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This CL is just getting the initial brox framework to get the
baseboard building. Copied files from brask baseboard and tried to
remove contents of some files like the device tree and memory IDs.
Added support for memory part "MT62F512M32D2DR-031 WT:B", mapped to
DRAM ID 0.
BUG=b:300690448
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_BROX -x -a
Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
BUG=NONE
TEST=Tested on Rex, touch over SPI works properly.
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: If339f7a010fa51bf73b8898a55643b5e921d93b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
