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Skolas baseboard needs to set BOARD_ROMSIZE_KB_32768, so this change
sets it.
BUG=b:239628052
BRANCH=firmware-brya-14505.B
TEST="emerge-brya coreboot" and verify that the following configs
are set as:
CONFIG_BOARD_ROMSIZE_KB_32768=y
CONFIG_COREBOOT_ROMSIZE_KB_32768=y
CONFIG_COREBOOT_ROMSIZE_KB=32768
CONFIG_ROM_SIZE=0x02000000
Change-Id: I0846b8e69c8b65e010eef9a8f4a88606197cd0c6
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Because 0 and 1 are the only possible values,
1. Change input argument "enable" of mainboard_enable_regulator to bool.
2. Change return value of mainboard_regulator_is_enabled() to bool.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Iae09c5fedf8f7394bfbb677e5aee37ed061304fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65997
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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From comments of CB:65875, we replace *_vol to *_voltage.
s/mainboard_set_regulator_vol/mainboard_set_regulator_voltage/
s/mainboard_get_regulator_vol/mainboard_get_regulator_voltage/
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Iadf0408e8914d6e32915464f93979978c4634eaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I71cc69c74dd618f441140790af351095ead3f6f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65759
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Ti50 hasn't implemented version reading yet. To avoid the confusing
error message
Did not recognize Cr50 version format
enable TI50_FIRMWARE_VERSION_NOT_SUPPORTED to make clear that this
feature is not supported.
BUG=b:234533588
TEST=emerge-corsola coreboot
BRANCH=none
Change-Id: I18dd4b5bc05c2af06627275968e49aba048ba05e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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This patch moves the early GPIO programming from
`bootblock_mainboard_init` to `bootblock_mainboard_early_init`.
It will help to get the early debug prints as below.
TEST=Without this CL the initial report platform information
was missing as below:
[DEBUG] VBOOT: Loading verstage.
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x1c04000.
[DEBUG] FMAP: base = 0xfe000000 size = 0x2000000 #areas = 33
[DEBUG] FMAP: area COREBOOT found @ 1c09000 (4157440 bytes)
[INFO ] CBFS: mcache @0xfef84a00 built for 18 files, used 0x414
of 0x2000 bytes
[INFO ] CBFS: Found 'fallback/verstage' @0x24d240 size 0x133d0 in
mcache @0xfef84d50
With this CL the complete bootblock serial msg is coming.
[NOTE ] coreboot-.mtl.po.ww29.5 Fri Jul 15 21:47:36 UTC 2022
bootblock starting (log level: 8)...
[DEBUG] CPU: Genuine Intel(R) 0000 @
[DEBUG] CPU: ID a06a0, MeteorLake A0, ucode: f0270108
[DEBUG] CPU: AES supported, TXT supported, VT supported
[DEBUG] MCH: device id 7d14 (rev 00) is MeteorLake P
[DEBUG] PCH: device id 7e01 (rev 00) is MeteorLake SOC
[DEBUG] IGD: device id 7d55 (rev 00) is MeteorLake-P GT2
[DEBUG] VBOOT: Loading verstage.
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x1c04000.
[DEBUG] FMAP: base = 0xfe000000 size = 0x2000000 #areas = 33
[DEBUG] FMAP: area COREBOOT found @ 1c09000 (4157440 bytes)
[INFO ] CBFS: mcache @0xfef84a00 built for 18 files, used 0x414
of 0x2000 bytes
[INFO ] CBFS: Found 'fallback/verstage' @0x24d240 size 0x133d0
in mcache @0xfef84d50
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3e092cd749359e54fe518de21671275af4b03062
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65986
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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The generic wifi driver currently contains a lot of intel specific
functionality that results in it not working properly on AMD platforms.
This commit updates the base device tree to use the generic PCIe driver
instead.
BUG=none
TEST=Ran on nipperkin device, dumped SSDT and checked wakeup sources
Change-Id: Iafbc68c1ae33ccc260889f0b39fc5fe8a59d7aca
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65990
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The generic wifi driver currently contains a lot of intel-specific
functionality that interferes with enabling wake-on-lan. This commit
changes the device tree to use the generic PCIe driver which better
supports this functionality.
BUG=b:237682766
TEST=Booted on skyrim device and verified that wake on LAN works
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I5d15d33fd0a152eb3bf2bfe78e802483a701e750
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65800
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust I2C speed for codec, TPM, touchpad.
BUG=b:237691531
TEST=Built and verified adjusted I2C speed < 400KHz
Change-Id: I203d137d61019235ddf38ef74607427db2a7e975
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Prepare platforms for linking romstage code in the bootblock.
Change-Id: Ic20799b4d6e3f62cd05791a2bd275000a12cc83c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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BUG=b:238571507
BRANCH=None
TEST=emerge-herobrine coreboot
Change-Id: Ie596e5c4b72de84d16571043db4291bbd0825c78
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Bob Moragues <moragues@chromium.org>
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Skyrim uses second SPI pads for ESPI. Switch to it initialize ESPI in
verstage.
BUG=b:217414563
TEST=Build Skyrim BIOS image. Ensure that ESPI init is successful in PSP
verstage.
Change-Id: I6e3462e95c50d256b6c159ae1d854dd69a538bb0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Now that the speed is limited to 5500 Mbps for all memory parts used in
Skyrim, regenerate the part IDs. Remove any custom generated part IDs
and the associated SPDs.
BUG=b:238074863
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I6d8326208580a971e781887a7ec83355bb085c7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65709
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The agah EC code includes a driver to keep track of the current D Notify
level that the GPU should be at. When it changes, it will send a host
event to the ACPI FW, which will then pass that Notify on to the kernel
driver. This patch adds support for that feature, which is described in
the Nvidia Software Design Guide.
BUG=b:229405562
TEST=add Printf() calls to the ACPI, and work through the various
scenarios on the EC that will cause D Notify levels to change; this
will cause the Printfs() to show up in the kernel log.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I5cd8bd7d177ea10a165613ed0726a6d6fd86c226
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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BUG=b:236175568
TEST=Build and test on MB, system can boot to OS.
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I779355dcc69eed08703bcb8bb943dcfeeb1fdea1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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For brya/skolas, I2C1 is cr50, and I2C3 is Touchscreen
BUG=None
BRANCH=firmware-brya-14505.B
TEST=None
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I4058e0f33b2bb6227a0af92941ed4e2eb56ba542
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This change adds memory part used by variant beadrix to
mem_part_used.txt and generates DRAM ID allocated to the part.
BUG=b:236750116
BRANCH=None
TEST=Run part_id_gen to generate SPD id
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I3f29609d9fe5143b0bfe4b78279d0780cd7e5097
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This patch tries to simplify the baseboard/variant GPIO programming
starting with Google/Rex. The idea is to let each variant maintain
its own complete GPIO PAD configuration table instead of having a
back-and-forth call between baseboard and variants.
With this patch coreboot performing GPIO programming is now much
simpler where the common code block calls into respective variants
and gets the gpio table prior to the pad configuration.
BUG=b:238165977 (Simplify baseboard/variant GPIO programming starting
with Google/Rex)
TEST=Able to build and boot the Google/Rex board.
AP firmware log with DEBUG_GPIO kconfig lists the early GPIOs being
configured from the `rex0` variant.
gpio_padcfg [0xd3, 08] DW0 [0x44000300 : 0x40000400 : 0x40000400]
gpio_padcfg [0xd3, 08] DW1 [0x00000020 : 0x00000000 : 0x00000020]
gpio_padcfg [0xd3, 08] DW2 [0x00000000 : 0x00000000 : 0x00000000]
gpio_padcfg [0xd3, 08] DW3 [0x00000000 : 0x00000000 : 0x00000000]
gpio_padcfg [0xd3, 09] DW0 [0x44000300 : 0x40000400 : 0x40000400]
gpio_padcfg [0xd3, 09] DW1 [0x00000021 : 0x00000000 : 0x00000021]
gpio_padcfg [0xd3, 09] DW2 [0x00000000 : 0x00000000 : 0x00000000]
gpio_padcfg [0xd3, 09] DW3 [0x00000000 : 0x00000000 : 0x00000000]
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8ec5c6991ec90a3884464e7f15f33327bfe4839a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Set USB3 port2 tx_de_emp 0x2B by "11th Gen Intel Core Processors for
IoT Platforms EDS Addendum_rev1.6" then fix the USB3 port2 Gen2 RX
failed.
BUG=b:236661824
TEST=emerge-brask coreboot and check USB3 port2 RX pass
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I7a5add20f055a8d871c6b4f33734fb8a397cba76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65848
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This allows the mainboard code to change FSP-M parameters depending on
parameters that are only known at run time and not at build time.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3e0e196a5d861acd7635c59db44ecf1970b73ce2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Add support for hardware watchdog event logging
BUG=b:221393157
TEST=Validated on qualcomm sc7280 development board by manually
triggering watchdog event and event was logged at next bootup.
Signed-off-by: Kshitiz Godara <quic_kgodara@quicinc.com>
Change-Id: I94971ab583f49c8a5ac232833215dbdad3a4d272
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65528
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Add wifi sar table for osiris
2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
BUG=b:234951991
TEST=build FW and checked SAR table can load by WiFi driver.
Cq-Depend: chrome-internal:4871098
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I301dce3229a24dd72b12b84d9eb7606abe10cbba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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For brya, I2C1 is cr50, and I2C3 is Touchscreen
BUG=None
BRANCH=firmware-brya-14505.B
TEST=None
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Id564d5ede43e745c607ddfd851ff03557d76ddec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Pujjo only support RTL1019 amp device, remove MX98360A device setting
BUG=b:238716919
TEST=Build and boot on pujjo
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I92ba66e8656ea36511f88cf867f51ba95168592e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Since ASPM is not verified as fully functional yet, and the board is
still in development, this patch disables ASPM for the dGPU.
BUG=b:236676400
TEST=boot to OS in agah, lspci -vvv shows ASPM is disabled
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I525eeb18c57d45fd55335b63a59262066afc9567
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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init overridetree.cb based on the latest schematic.
BUG=b:237628218
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I22778cc2582abdc2e62d98c6b049a0fa4dd467e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Update DDR4 SPDs to Eldrid to include the following:
DRAM Part Name ID to assign
H5AG36EXNDX019 0 (0000)
BUG=b:236739240
BRANCH=Volteer
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: I2c372fa40899aa750d335825cf3880bc52a612a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65819
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow latest schematic to add EC_IN_RW_OD.
BUG=b:238786599
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I701a940992895b2058b8ddfc444a2e7b7b9531ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Add SSD power sequence and remove the redundant weak.
BUG=b:238786597
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I0c1ce311d54fb92b27b17f50beda813fe66ad118
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Add module MT62F1G32D2DS-026 WT:B and assign RAM code.
BUG=b:238674174
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I811e1bbb985efe4198928f30ff6396a5b4368856
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65796
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is an ongoing effort to deprecate VBOOT_VBNV_CMOS, and replace it
with VBOOT_VBNV_FLASH [1]. Since SOC_INTEL_BROADWELL doesn't support
flash writes in early stages (BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES),
drop vboot as well as ChromeOS support for all broadwell boards,
including auron, jecht and wtm2.
[1] https://issuetracker.google.com/issues/235293589
BUG=b:235293589
TEST=./util/abuild/abuild -t GOOGLE_GUADO -a
TEST=./util/abuild/abuild -t GOOGLE_BUDDY -a
Change-Id: I002ab0f5f281c098afba16ada3621f1539c66d6b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Configure the I2C bus timing for all enabled I2C buses.
BUG=b:237751906
TEST=Verify the build for volmar board and measure the freq
is under 400KHz
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: Iffa128146f5d8bec6dd3d5c2d1e7efd96895dc6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65604
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable the support for providing a MAC address
for a dock to use based on the VPD values set in the platform.
BUG=b:235045188
TEST=tested on Brya by setting VPD values and observing the string
returned by the AMAC() method:
> vpd -i RO_VPD -s "dock_mac"="BB:BB:BB:BB:BB:BB"
> echo 1 > /sys/module/acpi/parameters/aml_debug_output
[acpi.aml_debug_output=1]
ACPI Debug: "Found VPD KEY dock_mac = BB:BB:BB:BB:BB:BB"
ACPI Debug: "MAC address returned from VPD: BB:BB:BB:BB:BB:BB"
ACPI Debug: "AMAC = _AUXMAC_#BBBBBBBBBBBB#"
Signed-off-by: Franklin Lin <franklin_lin@wistron.corp-partner.google.com>
Change-Id: I61b2a5e18bc17abeea0846f17e9be343e852c2b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65603
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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pujjo support FM101 WWAN, use wwan_power.asl to handle the
power off sequence
BUG=b:238281124
TEST=Build and boot on pujjo
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I53cd45c8030855c267d870d68d009c454350621e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
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This patch adds chip config entries for EC host cmd and memory map
ranges.
BUG=b:224325352
TEST=Able to build Google/Rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I84a3b128a05c013d659e490a01198955ef383f83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
+-------------+----------------+------------+
| USB 2.0 | Connector Type | OC Mapping |
+-------------+----------------+------------+
| 1 | NC | NC |
+-------------+----------------+------------+
| 2 | Type-C | OC_0 |
+-------------+----------------+------------+
| 3 | NC | NC |
+-------------+----------------+------------+
| 4 | Type-C | NA |
+-------------+----------------+------------+
| 5 | WWAN | NA |
+-------------+----------------+------------+
| 6 | Camera | NA |
+-------------+----------------+------------+
| 7 | NC | NC |
+-------------+----------------+------------+
| 8 | DCI | NA |
+-------------+----------------+------------+
| 9 | Type-A | OC_3 |
+-------------+----------------+------------+
| 10 | BT | NA |
+-------------+----------------+------------+
+---------------------+-------------------+------------+
| USB 3.2 Gen 2x1 | Connector Details | OC Mapping |
+---------------------+-------------------+------------+
| 1 | Type-A | OC_3 |
+---------------------+-------------------+------------+
| 2 | DCI | NA |
+---------------------+-------------------+------------+
+------+-------------------+------------+
| TCPx | Connector Details | OC Mapping |
+------+-------------------+------------+
| 1 | Type C port 0 | OC_0 |
+------+-------------------+------------+
| 3 | Type C port 1 | NA |
+------+-------------------+------------+
BUG=b:224325352
TEST=Able to build Google/Rex and boot to emulator.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iecab1318f683e3b53441cafe909bcfd978ee126b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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|
+-----------+-------------+------------------+
| INTERFACE | PCI (B:D:F) | DEVICE |
+-----------+-------------+------------------+
| GSPI-0 | 0:0x1e:2 | NA |
+-----------+-------------+------------------+
| GSPI-1 | 0:0x1e:3 | Finger Print MCU |
+-----------+-------------+------------------+
| GSPI-2 | 0:0x12:6 | NA |
+-----------+-------------+------------------+
BUG=b:224325352
TEST=Able to build Google/Rex and boot to emulator.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4b20e342cbca60821f82c07f72328cf63c0e5404
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch ensures LPSS UART 0 is used for the AP serial console as
per Rex Proto 0 schematics dated 07/05.
+-----------+-------------+-------------+
| INTERFACE | PCI (B:D:F) | DEVICE |
+-----------+-------------+-------------+
| UART-0 | 0:0x1e:0 | For AP UART |
+-----------+-------------+-------------+
| UART-1 | 0:0x1e:1 | NA |
+-----------+-------------+-------------+
| UART-2 | 0:0x19:2 | NA |
+-----------+-------------+-------------+
BUG=b:224325352
TEST=Able to get AP UART over LPSS UART0 using emulator.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ice0c81607c758e94d15ea19e346877776a3de7dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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+-----------+--------------------+-------------+--------+
| INTERFACE | PCI Number (B:D:F) | DEVICE | Speed |
+-----------+--------------------+-------------+--------+
| LPSS I2C0 | 0:0x15:0 | WFC | 400KHz |
| | +-------------+--------+
| | | AUDIO_DB | 400KHz |
+-----------+--------------------+-------------+--------+
| LPSS I2C1 | 0:0x15:1 | Touch Panel | 400KHz |
+-----------+--------------------+-------------+--------+
| LPSS I2C2 | 0:0x15:2 | NC | NC |
+-----------+--------------------+-------------+--------+
| LPSS I2C3 | 0:0x15:3 | Touch Pad | 400KHz |
+-----------+--------------------+-------------+--------+
| LPSS I2C4 | 0:0x19:0 | TPM | 400KHz |
+-----------+--------------------+-------------+--------+
| LPSS I2C5 | 0:0x19:1 | UFC | 400KHz |
| | +-------------+--------+
| | | SAR1 | 400KHz |
| | +-------------+--------+
| | | SAR2 | 400KHz |
| | +-------------+--------+
| | | HPS | 400KHz |
+-----------+--------------------+-------------+--------+
BUG=b:224325352
TEST=Able to build Google/Rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I76a28f175372542d441c787deb2a096382658ace
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch drops redundant cpu_cluster definition from mainboard
specific devicetree.cb as soc chip config (chipset.cb) already
has the required entry.
BUG=b:224325352
TEST=Able to build Google/Rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iad42985ead7269eaa739c31bede5948c2e25c67c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch adds initial PCI device entries into the override
devicetree.
BUG=b:224325352
TEST=Able to build Google/Rex and verified on MTL emulator.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I16326747df46769f93813ce322ed8045449ffa85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch adds initial PCI device entries into the baseboard
devicetree.cb.
BUG=b:224325352
TEST=Able to build Google/Rex and verified on MTL emulator.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I944b03a6b3c9c592c09984dde483c855f1a2cd32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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GPIO_GPU_NVVDD_EN is incorrectly (duplicately) assigned to GPP_A19 in
power.asl, but a double check of the schematic shows that the actual pad
is GPP_A17, so this patch fixes that.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4432b50c737508b7e0d595423d614a723d2499c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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I misread my notes when writing the code for the GC6I/GC6O Methods, and
accidentally included NV_33 in the GC6 sequence, which is incorrect
(confirmed in the Hardware Design Guide). This patch removes the code
that brings NV_33 up and down during the GC6 sequences.
BUG=b:236676400
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iaa6c5ef3d7b1edbe13257f99013ab0e4382bdbf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65565
Reviewed-by: Robert Zieba <robertzieba@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Variants of brya that have a dGPU also need to perform a special
shutdown sequence in the _PTS ACPI Method.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib760fa65e6e021c0949187f13f038d3e952e5910
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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The _ON and _OFF methods for the root port's power resource were
calling the _ON and _OFF in the PEGP namespace, which was the
incorrect method, it should have been NPON/NPOF, so this patch
updates that.
BUG=b:236676400
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia3653996329473f133e3f0d53306882dc3213b6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65487
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The preferred way of polling in ACPI I've seen is usually to just
divide the sleep into N chunks, and ignore the time taken in between.
This works in practice (validated with Timer calls before and after).
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4a2cd82cea05c539eff30b9b9d6ef18550d17686
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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The NBCI "get callbacks" _DSM subfunction should utilize the same "get
callbacks" subfunction from the GPS _DSM subfunction; this patch adds
that Method call into the ACPI code.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Idf2f148b5a95acccb02f47cba1ef33a9fc16bcd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
To avoid extraneous calls from the kernel to _ON or _OFF, keep track
of the power state of the GPU in an integer and exit _ON and _OFF
routines early when attempting to enter the current state.
BUG=b:236676400
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie874fcdc7022c4fde6f557d1ee06e8392ae3d850
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Modify USB2.0 port[6] setting for WFC camera support
BUG=b:235182560
TEST=Build and boot on pujjo
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I78dad102be2d915a251f6528eef07f2056001b0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65777
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Move audio codec item from fw_config to SSFC.
BUG=b:238353613
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I361ef54cd2ee3e0a423ed5086184936d6f09e099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
Add usb host function support.
TEST=read usb data successfully.
BUG=b:236331724
Signed-off-by: Shaocheng Wang <shaocheng.wang@mediatek.corp-partner.google.com>
Change-Id: I52174306eb0c87c6e5a3665051099b5c0e8f45a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65755
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Remove the pad configuration for GPP_B11
as this is not used in Nereid/Nivviks
BUG=b:227694137
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I3a213ffece75b9a706b96dc142a7e35c8b5973f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
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Google uses two digit GPIO pad numbers for internal GPIO references
and Intel has updated their GPIO naming schemes too (see the GPIO
implementation worksheet #641238) so use double digit GPIO pad numbers.
Format -
"GPP_%c%02d", gpio_group, gpio_pad_num
e.g.
GPP_A0 -> GPP_A00,
GPP_V2 -> GPP_V02,
GPP_C9 -> GPP_C09 etc.
BUG=b:238196741
TEST=Able to build meteorlake based google/rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ieb7569c1a35b08c0970a604ec7b4b91e6179dd28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65719
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Based on latest schematic:
Set GPP_S2 DMIC1_CLK/ GPP_S3 DMIC1_DATA to NC.
BUG=b:235303242
BRANCH=dedede
TEST=build
Change-Id: I4044cb7ba963153e1e478294dbf960fb79b97b5c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
|
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Agah doesn't support TBT interface so disable it in devicetree, for
fitimage configuration is at chrome-internal:4846869.
BUG=b:224423318
TEST=Build and check DUT boots.
Change-Id: I1eb43e86de5debf24ebde6eace14fe04bad5e5b1
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65699
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update the VR domain settings based on the request of internal team.
- IA ac_loadline from 2.3mOhms to 2.4mOhms.
- IA dc_loadline from 2.3mOhms to 2.28mOhms.
- GT ac_loadline from 3.2mOhms to 3.13mOhms.
- GT dc_loadline from 3.2mOhms to 2.94mOhms.
BUG=b:237044562
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I665665ab8e3bcd6d4643f8b954b86fad3ef78ccd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Override tdp pl1 value to 30W in CPU MSR.
BUG=b:238268367
TEST=Boot to Chrome OS and check cpu log show "CPU PL1 = 30 Watts".
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ibbd5ecc4b87ede5a62799020c741e5bff2952144
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
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Based on comments on CL:65534, update the non-early GPIO table.
These are cases where Arbitrage wasn't able to find a useful
heuristic, or the memory straps, where Arbitrage sees them as NC in
the schematic.
BUG=b:234626939
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I6e00892243cd6af99dc1921ee3fc712f6cbb58c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65710
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Customize brya baseboard early GPIO table to add mem straps for
ghost4adl, change I2C bus for TPM to pins H6/H7, and remove pins which
are not used on ghost4adl (E16, H13).
BUG=b:234626939
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I126a66fc5d24fbefec99abf87862c55b50c5e398
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65534
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I19cd9360a2571e8b88b1ed1005ce8564bdacb297
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Use USB4 fw_config to enable TBT PCIe RP0.
BUG=b:237619214, b:237623610
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ie3e51a0f30e0c9d20127c017436813d4ede95639
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65696
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
On nissa, WLAN should be a wake source, so don't put it into D3cold
during suspend.
BUG=b:233325709
TEST=Wake-on-WLAN works on nereid
Change-Id: Iddd5fa8db05b85d2c799f679d664876109187d0c
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
This patch enables Cnvi BT Audio Offload feature and also
configures the virtual GPIO for CNVi Bluetooth I2S pads.
BUG=b:233834597
TEST=Verified BT offload feature on Nivviks P1.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Iffbd08351d083d2b550f309994af931bceb257d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
Configure the unused virtual CNVi BT GPIOs to NC since we
are using BT over USB mode for Nissa.
BUG=b:233834597
TEST=Verified BT offload feature on Nivviks P1.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Id84823b9ad921ebd7ff773d6cce581563613745f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65669
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
Disabling the Package C-state demotion feature for nissa baseboard
as a work around to the S0ix issue and also this doesn't have any
impact on the power and performance measured and verified by the
PNP team.
This feature will be enabled after its functionality is verified with no
issues and also based on its impact on PNP.
BUG=b:235005582
TEST=Boot and verify that S0ix issue is resolved.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I4d586b962c27b86ee75651dcd655bc0868504646
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65664
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Based on latest schematic to update the PCIE and USB setting.
BUG=b:237659398
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I97989b7a8d9104379ffb0b454d7248d49855f680
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
|
|
DPTF Policy and temperature sensor values from thermal team.
BUG=b:237640264
TEST=USE="project_crota emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: I43340bd1acfe6ec2036ea80339dbf896615a456a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65563
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Enable SaGv support for Kinox
BUG=b:238153479
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Id4646f1621a414a1ec4e272c826b0baea2bb4e19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Modify ddi_ports_config based on schematic.
DDI_PORT_A = DP
DDI_PORT_B = HDMI
DDI_PORT_1 = Type-C DP
DDI_PORT_3 = HDMI
BUG=b:237419696
TEST=Boot to Chrome OS and check all display port working
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I7c0458f0dbd4637b91af9e01664073e1f8a7a614
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Currently the EC's MKBP interrupt line is programmed as dual-routed to
both SCI and IOAPIC. The brya EC will pulse the MKBP GPIO and also
send a host event when there is an MKBP event for host to service.
This causes an extra SCI to be generated, and the kernel will respond
to each MKBP event with an extra unnecessary host command. Changing
the pad configuration for the MKBP GPIO to APIC only fixes this issue.
BUG=b:236706977
BRANCH=firmware-brya-14505.B
TEST=excess GET_NEXT_EVENT host commands are gone from EC log
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic7dd596987f6d34c69d46674bdd07785235e2d4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65480
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The EEs have observed the ramp down delay on this signal in more detail
and 40 ms can still meet the sequencing requirements.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I49ef801f7a3fd7945ded63da1399eaf57fd6aef0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Since the GPU will be left powered on, the kernel has the opportunity to
save context and this method to save the BARs is not required.
BUG=b:233959099, b:236289930
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I19cf12426361a53e3672c1e05aa6d68d5dd6627c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Initialize NOR-Flash in the bootblock.
TEST=read nor flash data successfully.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I8ee24b5b24643bce57eb29682d6d0234a6fe8641
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65622
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Configure TDC current for VR domains.
+-----------+-------+-------+---------+-------------+----------+
| Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time |
| |(mOhms)|(mOhms)| (A) | (A) | (msec) |
+-----------+-------+-------+---------+-------------+----------+
| IA | 2.8 | 2.8 | 80 | 43 | 28000 |
+-----------+-------+-------+---------+-------------+----------+
| GT | 3.2 | 3.2 | 40 | 23 | 28000 |
+-----------+-------+-------+---------+-------------+----------+
- IA TDC current from 20A to 43A.
- GT TDC current from 20A to 23A.
- Others comes from 'commit c6d716694272 ("soc/intel/alderlake: Configure the SKU specific parameters for VR domains")'
BUG=b:237230877
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ie9cf8975309b57b4189e2b50f37bd61ac0105e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65659
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable DPTF oem_variables and override based on charger type.
BUG=b:230803675
TEST=1. With 90W adapter, check ACPI object ODVX and oem_variable[0]=1
Name (ODVX, Package (0x06)
{
0x00000001,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000
})
2. With 65W adapter, check ACPI object ODVX and oem_variable[0]=0
Name (ODVX, Package (0x06)
{
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000
})
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I78929ecbc9db56aa234b3f46c641d1f2f3b7cba8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
agah proto boards with i7 silicon face boot issues due to high power
consumption during MRC training.
This patch is a temporary WA to run in SAGV disabled mode while the
thermal issue is being investigated.
BUG=b:234402102
BRANCH=firmware-brya-14505.B
TEST=Build CB image and boot on agah board.
Change-Id: I431d233b23fb4f5c68117ea380fdec5646b88346
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65300
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
There is a new ground rule, variant should honor baseboard lock gpios.
Thus, lock the gpio which is locked in baseboard.
BUG=b:216671701
TEST=build passed.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ia087b62904fd515bf73960a188b225f1d49197dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65646
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Alder Lake-N based nissa boards use compressed ME_RW blobs for CSE FW
Update. Choose SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE Kconfig to perform
CSE FW sync in ramstage.
BRANCH=firmware-brya-14505.B
TEST=Perform CSE FW upgrade/downgrade on nivviks.
Change-Id: I00630096c52434f44914f3ae82ff043ecf77b80d
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65368
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
There is a new ground rule, variant should honor baseboard lock gpios.
Thus, lock the gpio which is locked in baseboard.
BUG=b:216671701
TEST=build passed.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I9f0fcf52b6b7d622e4fd182e007de6401856c7fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65645
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Set tcc_offset value to 0 in devicetree for Thermal Control Circuit
(TCC) activation feature. This value is suggested by Thermal team.
BUG=b:236294162
TEST=emerge-brask coreboot
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I8d4c631e07873923226683c8aa0cf36cb872e2d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
There is a new ground rule, variant should honor baseboard lock gpios.
Thus, lock the gpio which is locked in baseboard.
BUG=b:216671701
TEST=check gpios are locked in pinctrl dump.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ieed2d40b0222d8c8c193e0590131f83a5d96add9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
There is a new ground rule, variant should honor baseboard lock gpios.
Thus, lock the gpio which is locked in baseboard.
BUG=b:216671701
TEST=check gpios are locked in pinctrl dump.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I61931b0b2f1f936a672e72c98b83d66ba0059bf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for primus board. Please refer Intel doc#723158 for
more information.
BUG=b:237725329
TEST=Verify the build for crota board
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I6dde74c098ba57b7cd66ce7b9ee941b8961ad20c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cyan Yang <cyan.yang@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Modify GPIOs according to SOC_GPIO_Table_0629.xlsx.
- GPP_A21 from TCP_DP1_CTRLCLK to NC
- GPP_A22 from TCP_DP1_CTRLDATA to NC
- GPP_E20 from NC to TCP_DP1_CTRLCLK (Native Function 1)
- GPP_E21 from NC to TCP_DP1_CTRLDATA (Native Function 1)
BUG=b:237468533
TEST=emerge-brask coreboot
Change-Id: I8e7d343731efbfc04304d52a3493ab30b8a739b0
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
|
|
There is a requirement that the TPM RST signal cannot be asserted by
software. On nissa this is PLT_RST_L, so lock this pin to prevent it
being reconfigured as a GPIO.
BUG=b:216671701
TEST=Try to change GPP_B13 from the kernel:
$ echo 677 > /sys/class/gpio/export
$ echo out > /sys/class/gpio/gpio677/direction
$ echo 0 > /sys/class/gpio/gpio677/value
$ echo 1 > /sys/class/gpio/gpio677/value
GSC console doesn't show "PLT_RST_L ASSERTED" / "PLT_RST_L DEASSERTED"
Change-Id: Id5d64b4b028e4f63c4acb05cd8632d0642866688
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65591
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Add G2 touchscreen support for craaskvin.
BUG=b:235919755
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I7ade3ac1d135b8b21b09ef335ab7b30ae7a5e2c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
Set the GPIO configuration of joxer
BUG=b:237628218
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I1f7529342fc0800878f875d3641a2f93fbe6009a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
This patch uses ACPI _PLD macros to add custom values for USB ports.
C0 A2 A3
+----------------+
| REAR |
| |
| |
| |
| FRONT |
+----------------+
A1 A0
BUG=b:232419500
TEST=emerge-brask coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I5ada4e9b25102a9cfd3b02a2abcd956f6cbc5619
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Won Chung <wonchung@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).
This CL also includes changing Chromium OS to ChromiumOS as well.
BUG=None
TEST=N/A
Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for kano board. Please refer Intel doc#723158 for
more information.
BUG=None
TEST=Verify the build for kano board
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I19430a68e1e847e71382781563200a4c88f37a59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
|
|
Fill GPIO table for Pujjo.
BUG=b:235774770
TEST=emerge-nissa coreboot
Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I307b8460632f1feae9591200057c0e6471cbab24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65104
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This updates the ACPI locations of Type-C ports.
BUG=b:232806406
TEST=none
Change-Id: Ia15e09a58c731a1364a994fadf8df39115fbe7c4
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Add mainboard folder and drivers for new reference board 'Geralt'.
TEST=saw the coreboot uart log to bootblock
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I5e437d46097369bef535ff64e6a693b7cf67f2f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65586
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
|
|
This patch ensures AP UART messages are coming over LPSS UART 0 hence,
select required kconfig and program both early and late UART
RX/TX GPIOs accroding to the rex schematics dated 06/27.
BUG=b:224325352
TEST=Able to see AP UART log over LPSS UART0.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7daa8200d1a7cf825dfdfed538573efd57ab2d97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65454
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add the support LP5 RAM parts for rex:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
BUG=b:224325352
TEST=emerge-rex coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibcd25ae80d625b623b9a78ff2cd4447e85831cc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65476
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add memory init with placeholder to fill in required memory
configuration parameters. DQ map and Rcomp can be auto probed by
the FSP-M hence, kept it as default.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Able to boot till FSP-M/MRC using MTL simics.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5baa87411c28a20602eb5a7077f00664ccab3ade
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64850
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add SMI handler implementation to manage power cycle,
power state transition and Chrome EC events.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I10aab8257fce92aaf913a53c0c9fb6c1a4f5dea6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64623
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable building for Chrome OS and add associated ACPI configuration.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I75cb2d30d699166a056ed9d3c0779816b733b0d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64621
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Perform EC initialization in bootblock and ramstages. Add associated
ACPI configuration.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2ea934f32b34bc43650e20dd2736f4e652004dc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64622
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
