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2024-07-04mb/google/lotso: Add hid report address for gt7986uKun Liu
Add hid report address for gt7986u. BUG=b:342932183 BRANCH=None TEST=Verify touchscreen work normal. Change-Id: I464c2691505083314528519f608108c8a31e6cc0 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83201 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-04mb/google/nissa/var/domika: Create a domika variantWisley Chen
This patch creates a new domika variant which is a Twin Lake platform. This variant uses Yavilla board mounted with the Twin Lake SOC and hence the plan is to reuse the existing yavilla code. BUG=b:350399367 BRANCH=firmware-nissa-15217.B TEST=build, and boot into OS Change-Id: I42c56770f8b8d6018592253d2bb16b8166eb5719 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-04mb/google/brya: disable early EC sync for orisaAmanda Huang
Disable VBOOT_EARLY_EC_SYNC for all trulo boards. BUG=b:345112878 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I10b027d19dedbb190fc960b949017f9e4830d52a Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83303 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-03mb/google/rex: Set cnvi_wifi bluetooth companion deviceJeremy Compostella
To publish the Bluetooth Regulator Domain Settings under the right ACPI device scope, the wifi generic driver requires the bluetooth companion to be set accordingly. BUG=b:348345301 BRANCH=firmware-rex-15709.B TEST=BRDS method is added to the CNVW device and return the data supplied by the SAR binary blob Change-Id: I7f56ab8ac88c1fbc0b223b4286d2a998e424a46e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83299 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03mb/google/geralt: Replace GERALT_USE_MAX98390 with FW_CONFIG for TAS2563Rui Zhou
Use FW_CONFIG to differentiate MAX98390 and TAS2563. Since config GERALT_USE_MAX98390 is no longer needed after using FW_CONFIG, we remove GERALT_USE_MAX98390 from Kconfig. BUG=b:345629159 BRANCH=none TEST=emerge-GERALT coreboot TEST=Verify beep function through deploy in depthcharge successfully. Change-Id: Ie9f0cbc30dd950b85581fc1924fa351efe1e0aab Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-07-03mb/google/ovis/variants/deku: Add K3KL9L90CM-MGCT to RAM ID tableTony Huang
Add RAM ID for K3KL9L90CM-MGCT 0 (0000) BUG=b:320203629 BRANCH=firmware-rex-15709.B TEST=Run part_id_gen tool without any errors Change-Id: Icb84838a6964b9318ded0573ad58a4fd1221867f Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83300 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03mb/google/brox/var/lotso: Tune I2C frequency for 400 kHzJing Tong
Before: I2C0 - 401kHz I2C4 - 405kHz After: I2C0 - 392kHz I2C4 - 395kHz HW: Change R8409/R8411 to 33ohm. BUG=b:349743464,b:349735055 TEST=emerge-brox sys-boot/coreboot Test pass by EE Change-Id: I985837b1b80e973f148529b446905580c0f95e98 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83290 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
2024-07-01mb/google/corsola/var/wugtrio: Add LCE_LMFBX101117480 MIPI panelYang Wu
Add LCE_LMFBX101117480 MIPI panel for Wugtrio. Datasheet: LMFBX101117480-10.1-TLCM-24.05.20-2.pdf BUG=b:331870701 TEST=emerge-staryu coreboot chromeos-bootimage BRANCH=corsola Change-Id: I863e172400ffb26b5c9c240a21d15c6a2240b4ad Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-06-29tgl mainboards: Move audio related settings into hda device scopeFelix Singer
Change-Id: I1992c20dcdc5e974143690d44ee199d7c3394cfd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-06-29tgl mainboards: Move genx_dec settings into eSPI device scopeFelix Singer
Change-Id: I6d7bcd298408e15677f27d1a9797a490c57c9fc9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-06-29tgl mainboards: Move usb{2,3}_ports settings into XHCI device scopeFelix Singer
Change-Id: Ide5126c6e642ca16249efeaf46321724f2ddce9a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-06-28tgl mainboards: Drop disabled audio settings from dtFelix Singer
Configuring them to 0 is equal to not configuring them at all. So remove them to clean up a bit. Change-Id: I9a9eb370e8e9e8874ad8b4b8ac0f43d61c1a4b9b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-06-28tgl mainboards: Move SATA related settings into SATA device scopeFelix Singer
Change-Id: I03508c50fe56fd85f8bf89f724863e546d4140e9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-06-28mb/google/volteer/baseboard: Drop disabled SATA settings from dtFelix Singer
Configuring them to 0 is equal to not configuring them at all. So remove them to clean up a bit. Change-Id: I18134ac784fffb703e1fe513e5914f05faa749c9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83248 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28mb/google/brox/variants/brox/fw_config.c: Remove unused macroElyes Haouas
Change-Id: I8ce94c8bc7ed137eaace12d6cb0befa6c0d39a37 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82925 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-28mb/google/nissa/var/nivviks: Disable CNVi Bluetooth based on fw_configPoornima Tom
When CNVi based Wifi6 is disabled, CNVi based Bluetooth must be turned off, based on fw_config. Otherwise, when device boots without the cbi settings for wifi6, boot may fail with assertion error for line 817 & 819 of file 'src/soc/intel/alderlake/fsp_params.c'. BUG=b:345596420 BRANCH=NONE TEST=Dut boots fine with both Wifi6 & Wifi7 based cbi settings, along with enumeration of corresponding BT device. Change-Id: I03fde02fa4b36f4e47d6f0e95675feddb3bee7cd Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-28mb/google/nissa/var/nivviks: Enable PCIe Wifi GPIOs based on fw_configPoornima Tom
PCIe based GPIOs of Wifi7 module are enabled based on firmware config. BUG=b:345596420 BRANCH=NONE TEST= Based on fw config configured, wifi6 or wifi7 along with bluetooth ports are detected. Change-Id: If0584e91b5143c6df742961657d242c046409b3a Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-28mb/google/nissa/var/nivviks: Enable Bluetooth for PCIEPoornima Tom
PCIe based Bluetooth is on port8. This cl enables bluetooth for PCIe based Wifi7 module. BUG=b:345596420 BRANCH=NONE TEST=With proper FW config enabled, BT gets detected on port8 Change-Id: I989cf6122f2555cc89f622e4ce5d21b574d0458e Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83076 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28mb/google/nissa/var/nivviks: Enable wifi7 on pcie root portPoornima Tom
Enable pcie based, discreete wifi7 on root port4. BUG=b:345596420 BRANCH=NONE TEST=Verified Wifi7 module detection based on cbi settings Change-Id: I8c2f4a750a1cb00c587bce21bc83ee583d0f4341 Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83075 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28mb/google/nissa/var/nivviks: Add fw_config fields for wifi6 and wifi7Poornima Tom
Add a new fw config field for wifi category as WIFI_6, which is CNVi based and WIFI_7, which is PCIe based. Also, enable WIFI_6 for existing CNVi based wifi port as well as bluetooth port. BUG=b:345596420 BRANCH=NONE TEST=Verified Wifi6 module detection Change-Id: I4b218f772405bdb1b741b4d5e640d7b4f145cd76 Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83074 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-28mb/google/nissa/var/nivviks: Update config for CNViPoornima Tom
Add wake configuration and set 'add_acpi_dma_property'=true for CNVi. Also, add "set 'add_acpi_dma_property' to true to tell the OS to enforce DMA protection for this device. BUG=b:345596420 BRANCH=NONE TEST=SSDT dump showed below: Scope (\_SB.PCI0.RP01.WF00) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x23, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } Change-Id: If04539fe8dceb5c2edfc06a324ede11147b78b6d Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83138 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-27mb/google/brask/var/bujia: Configure Serial IO UARTs ModeShon Wang
This patch configures Serial IO UARTs mode as below. UART0 and UART1 in PCI mode and keep UART2 disable as per hardware design. BUG=b:338917836 BRANCH=firmware-brya-14505.B TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: I5617331aaf505b97e25a717b145fb70dc53f5a38 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83205 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-27mb/google/brox/var/lotso: GPP_B14 used for buzzerJing Tong
ALC257 does not supoort built-in digtal buzzer, So use external pwm to PCBEEP for beep sound. BUG=b:346956771 BRANCH=None TEST=emerge-brox coreboot sys-boot/chromeos-bootimage firmware-shell: devbeep -> can output beep normally. Change-Id: If924f9f27f229420e78015f418a97b2d5daf62e5 Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-06-26mb/google/fatcat: Add minimal code support for fatcatSubrata Banik
This patch adds initial code block required to build google/fatcat board with Intel Meteor Lake Silicon. Later after the initial board power-on is successful, we shall switch to Panther Lake silicon to build the google/fatcat reference design. BUG=b:347669091 TEST=Able to build the google/fatcat and able to hit power-on reset using Intel Meteor Lake SoC platform. Change-Id: Iad78aec51b2f0f240991c9c35842764a60be988e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-06-26mb/google/trulo/var/orisa: Add STORAGE_NVME in fw_config storage fieldAmanda Huang
Follow nissa baseboard setting for storage field. option STORAGE_EMMC 0 option STORAGE_NVME 1 option STORAGE_UFS 2 BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I75b4b3037c245f7d517cb33d487f71da98f6c4e8 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-26mb/google/brox/lotso: Add Fn key scancodeWen Zhang
The Fn key on Lotso emits a scancode of 94 (0x5e). BUG=b:322721490 TEST=Flash Lotso, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: I999627f0ea9db1d79376150a04920ac877a48447 Signed-off-by: Wen Zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83204 Reviewed-by: Dengwu Yu <yudengwu@huaqin.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-06-26mb/google/brox: Disable Touchscreen for hardware board version 1Karthikeyan Ramasubramanian
On board version 1 and later, touchscreen is not stuffed. Hence configure the relevant GPIOs as not connected, disable the concerned I2C bus in the devicetree as well as SoC chip config for board version 1. BUG=b:347333500 TEST=Build Brox BIOS image and boot to OS. Ensure that there are no peripherals detected in I2C 1 bus through i2cdetect tool. Ensure that no touchscreen devices are exported through ACPI SSDT table. Ensure that other I2C peripherals - eg. Trackpad and Ti50 are functional. Ensure that the device is able to suspend and resume for 25 cycles. Change-Id: Ia0578b90b0e8158ae28bcc51add637844ba6acf6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83199 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-26mb/google/brox: Add default ACPI brightness levelsKarthikeyan Ramasubramanian
Kernel need the default brightness steps. Otherwise following error messages are observed in the kernel: [Firmware Bug]: ACPI(GFX0) defines _DOD but not _DOS ACPI BIOS Error (bug): Could not resolve symbol [^^XBCL], AE_NOT_FOUND ACPI Error: Aborting method \_SB.PCI0.GFX0.LCD0._BCL due to previous error (AE_NOT_FOUND) BUG=b:346807006 TEST=Build Brox BIOS image and boot to OS. Ensure that the concerned error messages are resolved. Ensure that the backlight controls are functional. Change-Id: Icd569b0efef31908edb1b7dc384e60a16fc5bd0c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-06-26skl mainboards/dt: Move SATA related settings into SATA device scopeFelix Singer
Change-Id: I50706d7a077767d2295d6d5f209c30109d607277 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83179 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-26skl mainboards/dt: Move genx_dec settings into LPC device scopeFelix Singer
Change-Id: Iecb4851bedb7c9ed7793763d80acbcbb068e8832 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83172 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-26skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scopeFelix Singer
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-06-25lotso: Update board type to BOARD_TYPE_ULT_ULXKun Liu
Update board type to BOARD_TYPE_ULT_ULX BUG=b:348147663 BRANCH=none TEST=Built and compare the results of command 'dmidecode --type 17 | grep Speed' [Before] Speed: 8400 MT/s Configured Memory Speed: 6400 MT/s [After] Speed: 8400 MT/s Configured Memory Speed: 5200 MT/s Change-Id: I049d7c19424f41e83480f4b80bafd6ef8b9e30f6 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
2024-06-25mb/google/dedede/var/kracko: Add LTE only daughterboard supportRobert Chen
Add FW_CONFIG for no port LTE skus, and probe LTE port in devicetree. BUG=b:339534479 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage flash and check boot log on DUT. Change-Id: I5235df33a36f3b9472ee8b615e4622f6ee3fb1a4 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-25mb/google/trulo/var/orisa: Fill in ec.hAmanda Huang
Fill in ec.h according to schematic_20240614. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ie1edf655fd20c0c1baee01fa90ed03501e3fe161 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83154 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-25mb/google/trulo/var/orisa: Fill in gpio.hAmanda Huang
Fill ec pins in gpio.h and configure GPE0 DW2 in overridetree according to schematic_20240614. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I9de842a8a66632314d5fdf6444005d34338a1100 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83155 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2024-06-24mb/google/brox: Add support for batteryless bootingShelley Chen
Set PsysPL2 and PsysPL3 in addition to making adjustments to PL2 and PL4 in order to prevent brownouts when we don't have a battery or have an empty battery at boot time. BUG=b:335046538,b:329722827 BRANCH=None TEST=flash Able to successfully boot on a SKU1 with 45W, 60W+ adapters and SKU2 with a 60W or higher type C adapter. 30W is still being worked on. Change-Id: Ie36f16b2c938dce29cd2130a86fc8c08f5ba0902 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-06-24mb/google/brya: Create tereid variantSowmya V
This patch creates a new tereid variant, which is a Twin Lake platform. This variant uses Nereid board mounted with the Twin Lake SOC and hence the plan is to reuse the existing nereid variant code. BUG=b:346442939 TEST=Generate the Tereid firmware builds and verify with boot check. Change-Id: I052c3ba93d00e2df7e205c3127210bacaa956ca0 Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83145 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-24skl mainboards/dt: Drop SataPortsEnable[x] setting if disabledFelix Singer
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: Icdf58a85bbde0dcb4e555df68cd20eade241dde3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83176 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
2024-06-24skl mainboards/dt: Drop SataSalpSupport setting if disabledFelix Singer
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: Icb41f0a9baded01267410bd4c9458ab4bfb82b70 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83175 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
2024-06-24skl mainboards/dt: Drop ScsEmmcHs400Enabled setting if disabledFelix Singer
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: I1239132d5f25345ebb051d216e9187f3d2250339 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83174 Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-24skl mainboards/dt: Drop SsicPortEnable setting if disabledFelix Singer
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: Ic16d568c38d708da27efa7229e23019e71c0019b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-24mb/google/trulo/var/orisa: Configure SEN_MODE_EC_PCH_INT_ODL as inputAmanda Huang
Configure GPP_R2 as input, no pull according to schematic_20240614. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Ic678b77e5489f56d8ff92b265a6ca5852c0f7e8d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-23skl mainboards: Move cpu_cluster device to chipset devicetreeFelix Singer
Change-Id: I7114612e686a0bf3cfc241f45fa62077fad16f5a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-21mb/google/brask/var/constitution: Generate SPD ID for supported partsMorris Hsu
Add supported memory part in mem_parts_used.txt, then generate. H54G56CYRBX247 BUG=b:199645942 TEST=run part_id_gen to generate SPD id Change-Id: I2169d71695d8d133d26cafe5c7be33b976dd8603 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83127 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-20mb/google/nissa/var/sundance: Increase I2C1 hold time to 126nsRoger Wang
According to the vendor spec, I2C1 hold time needs > 100ns. System needs to adjust the I2C1 sda_hold value from 7 to 13, the system will change the I2C1 hold time from 70ns to 126ns. BUG=b:347157276 TEST=built bootleg and verified test result by EE team Change-Id: I722ec93177b6debf6b4c99de2df68c942560a3ff Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83080 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-20mb/google/brox/var/lotso: enable CNVi bluetoothJing Tong
Lotso's WIFI_BT is same design as brox, copy from brox. BUG=b:339612353 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I030e306dc5d9d3fcb6314bc491dbf5c9ae60bcb7 Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83126 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
2024-06-19mb/google/brox/var/lotso: Update devicetree settingJian Tong
Based on schematics NB7228A_LOTSO_INTEL_MB_PROTO_20240521A_BOM.pdf update devicetree settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: Ic9a7a9062f5c6e45c5bd9617f3b2a0634b8dc1db Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83051 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-19mb/google/brox/var/lotso: Update verb table from ALC256 to ALC257Jing Tong
Update verb table provided by Realtek on 20240614. BUG=b:344471736 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Device list: cat /sys/bus/hdaudio/devices/ehdaudio0D0/chip_name ALC257 cat /sys/bus/hdaudio/devices/ehdaudio0D0/vendor_name Realtek Headphone detection: Event: time 1718633617.056092, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 1 Event: time 1718633621.471708, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 0 Event: time 1718633623.898046, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 1 Event: time 1718633625.743663, type 1 (EV_KEY), code 115 (KEY_VOLUMEUP), value 1 Event: time 1718633625.743678, type 1 (EV_KEY), code 115 (KEY_VOLUMEUP), value 0 Change-Id: Idde8963de9302849f87b7c262f17d9c9d99b46dc Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83109 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-18mb/google/nissa/var/riven: Disable unused GPIOs based on fw_configDavid Wu
Disable LTE, stylus and WFC related GPIOs based on fw_config. BUG=b:337169542 TEST=Local build successfully. Change-Id: I91adc4e70d0d23b737d4fa6725cd96e63108f874 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-18mb/google/nissa/var/sundance: disable pcie port7Roger Wang
Disable pcie port7 to prevent s0ix issue when run the FAFT sleep test. BUG=b:328147465 TEST=Build and check S0ix function and verify FAFT sleep funciton. Change-Id: I53f704ed11a5c63b5c079c6e60ce2fa32bbd8b1a Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-18mb/google/nissa/var/pujjoga: disable pcie port7Roger Wang
Disable pcie port7 to prevent s0ix issue when run the FAFT sleep test. BUG=b:335312655 TEST=Build and check S0ix function and verify FAFT sleep funciton. Change-Id: I7918e26fe382d4d9992a0e2744a2f8894a070e36 Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-18mb/google/nissa/var/pujjoga: Update DPTF parametersRoger Wang
Adjust settings as recommended by thermal team. Update DPTF parameters based on b:346930334 BUG=b:346930334 TEST= built bootleg and verified test result by thermal team Change-Id: I363eaa72b5190212b014fe4e2c2fca10e2a3f408 Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83079 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-18mb/google/nissa/var/sundance: Update DPTF parametersRoger Wang
Adjust settings as recommended by thermal team. Update DPTF parameters based on b:346932306 BUG=b:346932306 TEST= built bootleg and verified test result by thermal team Change-Id: I6a529365249a5372dd87ef28cb9ea8d540b9cac0 Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83078 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-06-17Revert "mb/google/brox/var/lotso: enable CNVi bluetooth"Matt DeVillier
This reverts commit 0e0bc618e3ed1888ac140010057dc7485443c3c2. Reason for revert: Merged out of order, breaks tree Change-Id: I22bd85a2008db471177257a8b779c06898b1010c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83105 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-06-17mb/google/nissa/var/riven: Disable storage devices based on fw_configDavid Wu
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:337169542 TEST=Local build successfully. Change-Id: I3d71a35e9c0a33b72720b093b5a05eb69d5bb9f8 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83060 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-17mb/google/nissa/var/riven: Add initial override devicetreeDavid Wu
Add initial override devicetree for riven based on the latest schematic (Riven(ZDK)_MB_Proto_0601.pdf). 1. Add eMMC DLL tuning value (copy from craask) 2. Configure I2C frequency (copy from craask) 3. Add audio codec and speaker amp settings 4. Add Elan touchscreen settings (copy from craask) 5. Add WFC and usb settings (copy from craask) 6 Add Elan and Synaptics touchpad settings (copy from craask) 7. Add WIFI6(CNVI) and WIFI7(PCIE) configuration 8. Add LTE settings (copy from craask) BUG=b:337169542 TEST=Local build successfully. Change-Id: I1dda3557edb44dda9c3a1efaf98437352978561c Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83059 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-17mb/google/drallion: Set touchpad IRQs as wake sourceAngela Czubak
Elan touchpad driver in newer linux kernels (>= 5.15) no longer explicitly configures the touchpad as a wakeup source for devices not using device tree. It is now assumed this information should be extracted from ACPI, therefore we need to update drallion's devicetree so that the device regains its lost capability. TEST=update drallion FW and verify touchpad can cause wake up from suspend Change-Id: Iff21afda144cc11a013cb72816064df1c9eb21ae Signed-off-by: Angela Czubak <aczubak@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83070 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-17mb/google/brya/base/nissa: Add default GMA panelMatt DeVillier
Enables ACPI brightness controls to be generated, and display brightness controls to be functional under Windows. TEST=build/boot Win11 on google/brya (craaskin), verify display brightness controls present and functional. Change-Id: I821b912cf52b5b89c5c9d831a5a15566b1b31639 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-17mb/google/brya: Add default ACPI brightness levelsMatt DeVillier
Boards using the brya baseboard already generate ACPI brightness controls via their use of the gfx/generic driver, but need the default brightness steps in order for display brightness control to be functional under Windows. TEST= build/boot Windows 11 on banshee, verify brightness controls functional. Change-Id: I03bb7a7309476839c49d2e862a036d9e89800605 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70372 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-17mb/google/brox/var/lotso: enable CNVi bluetoothJian Tong
Lotso's WIFI_BT is same design as brox, copy from brox. BUG=b:339612353 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I3946297db7f10a31570f773bdc5665f9f472c9fe Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83053 Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-17mb/google/trulo/var/orisa: Configure GPIO settingsAmanda Huang
Configure GPIOs according to schematic_20240607. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I760a7a234df43db3a557b3be9e20ff7aa5f80b72 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82661 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-17mb/google/nissa/var/riven: Use unified AP FW for UFS/Non-UFS SKUsDavid Wu
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS which intends to achieve a unified AP firmware image across UFS and non-UFS skus. BUG=b:328580882 TEST=Local build successfully. Change-Id: Ifcee68a3492ab4606819de0be41701f803151f66 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83061 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-14mb/google/brya/var/xol: Turn off camera power during s0ixSeunghwan Kim
Turn off camera power during s0ix to improve power consumption. BUG=None BRANCH=brya TEST=built and verified GPP_A17 went to low during s0ix with a scope. [Measurement of s0ix power consumption - 1 hour avg] Before this: 301.4 mW After this: 299.8 mW Change-Id: Iae02d06e9f5a5988563b2b7ae36d153aecedb9d7 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83029 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
2024-06-12mb/google/volteer/var/drobit: Update boot resolution in VBTMatt DeVillier
Enable the fixed boot mode option in the VBT and set it to 1920x1080, so that drobit boards equipped with 4K screens are legible at boot. TEST=build/boot drobit w/4K screen using edk2 payload, verify boot resolution set to 1080p and UEFI menus readable without a magnifying glass. Change-Id: If1f9e36d9bbdc2955ba890e2832aa64af9ba8f73 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-12mb/google/brox: Generate RAM IDsKun Liu
Generate RAM IDs for K3KL6L60GM-MGCT H9JCNNNBK3MLYR-N6E K3KL8L80DM-MGCU MT62F1G32D2DS-023 WT:C H58G56BK8BX068 BUG=b:333494257 BRANCH=None TEST=Run part_id_gen tool without any errors Change-Id: I7a240a263816193b9f3d418385c1673e9d3f89db Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
2024-06-12mb/google/brox/var/lotso: Update gpio settingJian Tong
Based on lotso EVT schematics update gpio settings. GSPI0_CS0_L -> NF7 GSPI0_MISO -> NF7 GSPI0_MISO -> NF7 GPP_F18 -> EDGE_SINGLE BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I12d84538566c4d51fe346eb5609e55d91ddafbea Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
2024-06-12mb/google/nissa/var/pujjoga: Add WWAN power off sequenceLeo Chou
Pujjoga support EM060 WWAN, use wwan_power.asl to handle the power off sequence. BUG=b:346479638 TEST=Build and boot on pujjoga Change-Id: I1273d09385c661835d741691b3c4af26e72a9f86 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83042 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-12mb/google/nissa/var/pujjoga: Tune SX9324 registers settingLeo Chou
Currently, the P sensor does not work. So add SX9324 registers settings based on tuning value from SEMTECH. BUG=b:340749850 TEST=Check i2c register settings on Pujjoga and confirm P sensor function can work by kernel 6.6 driver. Change-Id: I205c1f5228d792afc763a06f74a8744918e2da75 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82689 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-12mb/google/nissa/var/sundance: Add wifi sar tableLeo Chou
Add AX211 wifi sar table for sundance wifi sar config. Use fw_config to separate different wifi card settings. WIFI_SAR_TABLE_AX211: 0 BUG=b:332978681 Test=emerge-nissa coreboot Change-Id: Ide84996da567e4f866a2a1309a6976ed8df635a6 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83044 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-12mb/google/nissa/var/sundance: Add FW_CONFIG probe for WWAN devicesLeo Chou
Add FW_CONFIG probe based on sundance boxster of below devices: WWAN Schematic version: NEC_SHIKIBU_ADL_N_MB_EVT_20240330 BUG=b:332978681 TEST=Boot to OS and verify the WWAN devices is set based on fw_config. Change-Id: I14339201d8ee21c85fefa96a49323e0c25cb8eca Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83041 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-12mb/google/trulo/var/orisa: Disable storage devices based on fw_configAmanda Huang
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned. BUG=b:345112878 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I1e5e49c1baa8d2b00134c26cc3b69aa15712b512 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-12mb/google/trulo/var/orisa: Enable HDA Codec ALC256Amanda Huang
We use ALC256 as HDA codec on orisa. Add verb table and the related device tree changes for HDA related registers. BUG=b:338523452 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I92051886341bd317cce6061ece83439d156b0f90 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82719 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-12mb/google/trulo/var/orisa: Add overridetreeAmanda Huang
Add override devicetree based on schematic_20240607. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id3ceff41fdb8e4a57bd6dab6247b622a5d13587d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-11mb/google/trulo/var/orisa: Add memory configAmanda Huang
Fill in memory config based on the the schematic_20240607. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I1456f7385e092b606fc0a35b25f3454600af8b23 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82662 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-10mb/google/nissa/var/riven: Add GPIO tableDavid Wu
Refer to the reference board of nivviks, and update GPIO settings based on latest schematic (Riven(ZDK)_MB_Proto_0601.pdf). BUG=b:337169542 TEST=Local build successfully. Change-Id: Ic43c743fcc2ec89b5a9e2fbe1a87b833d59f1e74 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82973 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-08mb/*: Remove old USB configurations from SNB/bd82x6x boardsKeith Hui
Remove USB configurations and data structures from northbridge devicetree (SNB+MRC boards) and bootblock/romstage C code (native-only SNB boards). All USB configurations are drawn from southbridge devicetree going forward. Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81882 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-08mb/*: Add consolidated USB port config for SNB+MRC boardsKeith Hui
For each sandybridge boards with option to use MRC or native platform init code, add a copy of the board's USB port config, consolidated between both code paths, into the southbridge devicetree, using special values allocated for this consolidation. These get hooked up in a separate patch. Change-Id: I53efca3d29b3c5d4d5b7e3d6dc3e6ce6c34201e6 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81880 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07mb/google/brya/var/xol: add support for wifi sar tableYH Lin
Add wifi sar table support for xol. Bit 31 in CBI/FW_CONFIG is used to select different sar table (index 0 or 1) but only 0 is in used at the moment. BUG=b:344274789 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Change-Id: Id4dc74c4f2a807d2e531b419ecb7b590d4c32ac2 Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-07mb/google/brox/var/brox: update thermal settings to start fan earlySumeet Pawnikar
Current existing temperature thresholds of TSR1 sensor are set at 60C to start fan. Due to this CPU gets hot and temperature goes over 80C. In this situation, fan does not even start to lower down CPU temperature. With updated new settings based on tuning from thermal team, start fan early at 40C for TSR0 and TSR1 so the CPU temperature stays below 80C. BUG=b:339493551 TEST=Built and tested on google/brox board Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: I4765c13c10e436733d8c9d017085968daa561ccc Reviewed-on: https://review.coreboot.org/c/coreboot/+/82784 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-06-07mb/google/rex0: Restore SSD power sequencing GPIOs in ramstageSubrata Banik
This change restores the EN_PP3300_SSD GPIO configuration in the ramstage for the Rex0 variant. This is necessary to enable testing of RO lockdown scenarios on FSI'ed Screbo devices, where bootblock changes are not applicable. Additionally, ensures locking the GPIO PAD from getting misconfigured after booting to OS. BUG=b/337971452 BRANCH=firmware-rex-15709.B TEST=Able to boot google/rex with RO locked to an older version without SSD GPIO refactored, and RW is with the latest revision. Change-Id: Ia7564b14a20d00e9bb2c9466b7a737dd97f01351 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-07mb/google/nissa/var/pujjoga: Add wifi sar tableLeo Chou
Add AX211 and AX203 wifi sar table for pujjoga wifi sar config. Use fw_config to separate different wifi card settings. WIFI_SAR_TABLE_AX211: 0 WIFI_SAR_TABLE_AX203: 1 BUG=b:336167281 Test=emerge-nissa coreboot Change-Id: If0f542cb13e93e99960bf65d616b26cee7617a43 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-06-07mb/google/nissa/var/pujjoga: Add FW_CONFIG probe for WWAN devicesLeo Chou
Add FW_CONFIG probe based on pujjoga boxster of below devices: WWAN Schematic version: 500E_GEN4S_ADL_N_MB_0418 BUG=b:336167281 TEST=Boot to OS and verify the WWAN devices is set based on fw_config. Change-Id: I94cb9ffe47888a8b7b5c6837ddfc390a1d2e77d1 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-07mb/google/dedede/var/boten: Add new supported memory partLeo Chou
Add bookem new supported memory parts in mem_parts_used.txt. Generate SPD id for this part. Zilia SDVB8D8A34XGCL3N3T BUG=b:344482259 TEST=Use part_id_gen to generate related settings Change-Id: I1cbf641e2bbe4fd4eea02a1bfa3d6b3c06e567e4 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82783 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-07mb/google/brask/var/bujia: fix type-c USB2 problemShon Wang
Enable type-c port 0 USB2 function. BUG=b:327549688 TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: I0d7adc329a8c26941957d7a7472a5166b07bda5b Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82903 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07mb/**/hda_verb: Use `AZALIA_PIN_CFG_NC(0)`Angel Pons
Replace `0x411111f0` with `AZALIA_PIN_CFG_NC(0)`, which evaluates to the same value and conveys additional information to the reader. Done with a bulk search and replace operation. Change-Id: Ibd84daec017bc1ab1ee4edd906fda80231c134cc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-06mb/google/brox/var/lotso: Add dq map settingJian Tong
Based on lotso EVT schematics add dq map settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I4f03e8a90522cbf2fe06f4160414202dcc4a2199 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82600 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Dengwu Yu <yudengwu@huaqin.corp-partner.google.com>
2024-06-05mb/google/brox/var/lotso: Update gpio settingJian Tong
Based on lotso EVT schematics update gpio settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I13485cc7ccd8b15352f5e21ad9336aa2b3d35749 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82573 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com>
2024-06-05mb/google/trulo/var/orisa: Configure TPM IRQ for orisaAmanda Huang
Set GSC_SOC_INT_ODL to GPP_A17 instead of GPP_A13. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I065fdf2a66036c6df1e16dda3b2a684b5202cccc Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82717 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-04mb/google/brya/var/xol: Enable FSP UPD LpDdrDqDqsReTrainingSeunghwan Kim
Set LpDdrDqDqsReTraining to 1 for xol. Value 0 will cause black screen issue. Reference: https://review.coreboot.org/c/coreboot/+/79527 > FSP default value for LpDdrDqDqsReTraining is 1. For boards > that didn't set LpDdrDqDqsReTraining to any value, 0 was being > assigned and it caused black screen issue. BUG=b:332980211 BRANCH=brya TEST=Built and verified there is no black screen issue during power on/off test for over 100 cycles. Change-Id: Ia346ce559b4509ea1a63abe28b12ad909f9b7b0d Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82778 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-04mb/google/brask/var/bujia: change ALC5650 to ALC5682I-VSShon Wang
Due to system spec change, change audio codec ALC5650 to ALC5682I-VS BUG=b:329787697 TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: I38e5c58b3ef3fbe709b98601975ae3821bb77213 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-31mainboard/google/rex: Enable Rex64 build configurationSubrata Banik
- Add Rex64 board to Kconfig menu - Enable building for Rex64 with x86_64 support Change-Id: I02e2c49b4aeb2cb98d9d0cb66717db18c3f96d45 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82625 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-31mb/google/brya/var/nova: Update USB ports settingKenneth Chan
Update used USB port[2][3](type-a) setting for nova. BUG=b:328711879 TEST=emerge-constitution coreboot chromeos-bootimage Change-Id: I63cf97b23627feac05743f2a6e514a33fcaf7dff Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82703 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2024-05-31mb/google/trulo: Support OCP fault on A0/1 portsPranava Y N
The devicetree entry and gpio.c updated as per the schematics of Trulo to map the OC fault signals from A0/A1 USB ports. BUG=b:335858378 TEST= Able to build google/trulo Change-Id: Ic17debc5eecebca8c000c43a660e1b52d2932f2a Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82637 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-05-29mb/google/nissa/var/sundance: Add WWAN power off sequenceLeo Chou
Sundance support FM101 WWAN, use wwan_power.asl to handle the power off sequence BUG=b:343139385 TEST=Build and boot on sundance Change-Id: I82085172db370ab5a6c0f77afe6042c53b89e43e Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-29mb/google/nissa/var/pujjoga: Update touchscreen IC settingsRoger Wang
Modify the Goodix touchscreen from new vendor and remove 3 unused touchscreens. According to the information provided by the key-part team. BUG=b:340689681 TEST=Build and check Goodix touchscreen can work. Change-Id: I1e6349e80431aadf27cd72b8439b01f95348071d Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82427 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-29mb/google/nissa/var/sundance: Update eMMC DLL settingsRoger Wang
Currently Samsung eMMC (KLMBG2JETD-B041) can't power on to OS nomally. According to Intel provides eMMC DLL delay patch that tuning on each Sundance different eMMC system to modify some system can't boot to OS problem. BUG=b:342057438 TEST=Build and check each SKU eMMC can work. Change-Id: I29d4305bbe5f91d822d947cae942b654e80a8a57 Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82602 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-29tree: Remove unused <string.h>Elyes Haouas
Change-Id: I9ed1a82fcd3fc29124ddc406592bd45dc84d4628 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-29tree: Use <stdio.h> for snprintfElyes Haouas
<stdio.h> header is used for input/output operations (such as printf, scanf, fopen, etc.). Although some input/output functions can manipulate strings, they do not need to directly include <string.h> because they are declared independently. Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-28mb/google/brox: Add romstage early graphicsSowmya Aralguppe
Select MAINBOARD_USE_EARLY_LIBGFXINIT for brox to enable SOL image. This patch enables Sign of Life image during MRC training. BUG=b:335369811 TEST=Able to boot to ChromeOS with SOL image. CPU log: [SPEW ] bootmode is set to: 0 (boot with full config) [0.384818] DP PHY mode status not complete [0.388911] DP PHY mode status not complete [0.393197] DP PHY mode status not complete [0.397484] DP PHY mode status not complete [0.401771] DP PHY mode status not complete [0.406057] DP PHY mode status not complete [0.410345] DP PHY mode status not complete [0.414632] DP PHY mode status not complete [0.418916] DP PHY mode status not complete [0.423203] DP PHY mode status not complete [0.427491] DP PHY mode status not complete [0.431777] DP PHY mode status not complete [INFO ] Informing user on-display of memory training. [DEBUG] FMAP: area COREBOOT found @ 1877000 (7901184 bytes) [WARN ] CBFS: 'preram_locales' not found. [ERROR] ux_locales_get_text: preram_locales not found. [DEBUG] FMAP: area RW_ELOG found @ f20000 (16384 bytes) [INFO ] ELOG: NV offset 0xf20000 size 0x4000  elogtool list: 0 | 2024-05-10 02:26:07-0700 | Log area cleared | 4088 1 | 2024-05-10 02:26:07-0700 | Early Sign of Life | MRC Early SOL Screen Shown 2 | 2024-05-10 02:26:51-0700 | Memory Cache Update | Normal | Success 3 | 2024-05-10 02:27:09-0700 | System boot | 4 4 | 2024-05-10 02:27:09-0700 | Firmware Splash Screen | Enabled 5 | 2024-05-10 02:27:11-0700 | System Reset 6 | 2024-05-10 02:27:11-0700 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown 7 | 2024-05-10 02:27:18-0700 | ACPI Enter | S5 8 | 2024-05-10 02:27:36-0700 | System boot | 5 9 | 2024-05-10 02:27:36-0700 | Firmware Splash Screen | Enabled 10 | 2024-05-10 02:27:37-0700 | System Reset 11 | 2024-05-10 02:27:37-0700 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown Change-Id: I1d4795825960bc58f8f7ef494b01aa975f3bc346 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
2024-05-28mb/google/trulo: Add initial devicetree.cbSubrata Banik
This patch adds initial PCI device entries into the baseboard devicetree.cb. TEST=Able to build google/trulo. Change-Id: I6ec25b98379cf7c8cbdb5be94d9f3ea43878620c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 11:44:23 +0000