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2021-10-21mb/google/guybrush/var/nipperkin: Override GPIO configurationKarthikeyan Ramasubramanian
SOC_PEN_DETECT_ODL, SOC_SAR_INT_L and WWAN_AUX_RESET_L are not connected in nipperkin. Override those GPIO configurations. BUG=None TEST=Build and boot to OS in Nipperkin. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7e497f83593472ecf4927e5379e1dd7786e77e62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
2021-10-21mb/google/guybrush: Add PCIe Reset GPIO18 to PCIE WWAN DXIO DescriptorKarthikeyan Ramasubramanian
WWAN_AUX_RST_L is asserted during S0i3 entry. But it needs to be de-asserted before PCIe link training during S0i3 resume. Otherwise the concerned gpp_bridge_2 PCIe device is not enumerated on Soi3 resume. This change feeds in the WWAN_AUX_RST_L GPIO in the DXIO descriptor so that SMU de-asserts this reset on S0i3 resume. BUG=b:199780346 TEST=Build and boot to OS in Guybrush. Perform suspend/resume cycles for 500 iterations. Ensure that the PCIe devices enumerate fine. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I588c490bf3f8a7beffefc3bfd8ca5167fcbcb9a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-21mb/google/guybrush: Make DXIO Port Descriptor configurableKarthikeyan Ramasubramanian
Instead of a const port descriptor, make it configurable. This will help to avoid adding duplicate tables for every minor configuration updates. BUG=None TEST=Build and boot to OS in Guybrush. Perform suspend/resume, warm and cold reboot cycles for 10 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If616a08ba54fddab25e5d0d860327255dfd43cbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/58378 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-21mb/google/brya/var/kano: Enable BT offload supportDavid Wu
Enable the CnviBtAudioOffload UPD and program the corresponding BT VPGIOs. BUG=b:202913826 TEST=emerge-brya coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Id81cba82742f552c098ec3719a0b453b752dc5c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21mb/google/trogdor: determine which panel to use by panel_id for quackingstickSheng-Liang Pan
panel_id 6 for AUO B101UAN08.3. BUG=b:201263032 BRANCH=none TEST=make Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I076ded9300c2ec1704a566722870bd0d1a20e9d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58363 Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-21mb/google/dedede/var/bugzzy: Add LTE power off sequenceSeunghwan Kim
This change adds LTE power off sequence for bugzzy. BUG=None BRANCH=dedede TEST=FW_NAME=bugzzy emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I6be0e23b9c2c2bed9745011920394006fdaabae6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-21mb/google/dedede/var/bugzzy: Enable/disable LTE function based on FW_CONFIGSeunghwan Kim
Enable/disable LTE function based on DB_PORTS field of FW_CONFIG. - GPIO control - USB port setting BUG=None BRANCH=dedede TEST=FW_NAME=bugzzy emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I8363f8e7052ff9cfa423063a7e8f5a0f9ce1df2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20google/trogdor: Support Parade ps8640Philip Chen
Support Parade ps8640 as the second source edp bridge for some trogdor board variants/revisions. BUG=b:194741013 BRANCH=trogdor TEST=verified firmware screen works on lazor rev9 Change-Id: Iae5ccd8d9d33d60e4c37011ecffdd7a05af59ab2 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-20mb/google/brya/var/redrix: Enable bt_offload supportMac Chiang
Enable CnviBtAudioOffload UPD and program the corresponding VGPIO pins BUG=b:191931762 TEST=emerge-coreboot Signed-off-by: Mac Chiang <mac.chiang@intel.com> Change-Id: I81bae537d52592e878db56343970de6fc488950f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20mb/google/brya/anahera: Add two thermal sensor settingWisley Chen
Anahera has 4 thermal sensors, so add the missing sensors settings. BUG=b:203187535 TEST=build and verified by thermal team. Change-Id: I0e5c0d9c09c88cc95fdfd77b96800a0f4929d7d2 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20mb/google/brya/anahera: Update HID to MX98360AWisley Chen
Because of a change in the chromium OS kernel machine driver for the MAX98357A, a _HID that matches MAX98360A has to be used. (https://chromium- review.googlesource.com/c/chromiumos/third_party/kernel/+/3070268/) BUG=b:200778066 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: Ic68373920d9135e614ff792149079de451ec6e60 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20mb/google/taeko: enable DPTF functionality for taekoKevin Chang
Enable DPTF functionality for taeko BRANCH=None BUG=b:203035930 TEST=Built and tested on taeko board Change-Id: Ic9f3cbf5cd52ebc48b274b43fcdb57a51dcf94ec Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-10-20mb/google/brya/var/anahera: change from CLKREQ#2 to CLKREQ#6 for eMMCWisley Chen
Based on the latest schematics, change eMMC CLKREQ from CLKREQ#2 to CLKREQ#6 BUG=b:197850509 TEST=build and boot into eMMC Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I0fc87c864b62a37fc3fa7a4a9a7722bf286c007b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20mb/google/dedede/var/bugzzy: Generate SPD ID for Samsung K4U6E3S4AB-MGCLSeunghwan Kim
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL BUG=None TEST=emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I0720a51336f374f709c392c4bae4ad3e4c580a2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20mb/google/dedede/var/sasuke: Generate SPD ID for Samsung K4U6E3S4AB-MGCLSeunghwan Kim
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL BUG=None TEST=emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I91183f33b92569dd49967ef866d58043d79c287b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20mb/google/brya/var/taeko: Add fw_config probe for ALC5682-VSJoey Peng
ALC5682-VD/ALC5682-VS load different kernel driver by different _HID. Update the _HID depending on the AUDIO field of fw_config.Define fw config bit 5-7 in coreboot for codec. BUG=b:202913837 TEST=FW_NAME=taeko emerge-brya coreboot Change-Id: I635b173e0fe4c46d28f2c29fecee1998b29499b1 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19mb/google/brya/var/kano: Correct SSD power sequenceDavid Wu
M.2 spec describes PERST# should be sequenced after power enable. BUG=b:192137970 TEST=FW_NAME=kano emerge-brya coreboot and boot to OS. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I20bf5ca66c6d05229c6d72058c5a73f38a58be3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19mb/google/brya: Set same size for CSE_RW, ME_RW_A and ME_RW_BFurquan Shaikh
CSE RW firmware from ME_RW_A/ME_RW_B is copied over to CSE_RW region in case of firmware update. Ensure that the size of the regions match so that we do not have situations where ME_RW_A/B firmware grows bigger than what CSE_RW can hold. BUG=b:189177538 Change-Id: I374db5d490292eeb98f67dc684c2106d42779dac Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19mb/google/brya: Add sub-regions to SI_ME in chromeos.fmdFurquan Shaikh
This change adds sub-regions to SI_ME in chromeos.fmd. These are required to support stitching of CSE components. BUG=b:189177538 Change-Id: I4da677da2e24b0398d04786e71490611db635ead Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19mb/google/guybrush/dewatt: update DRAM tableKenneth Chan
Samsung LPDDR4X 4266 2G K4U6E3S4AB-MGCL Hynix LPDDR4X 4266 2G H54G46CYRBX267 Micron LPDDR4X 4266 2G MT53E512M32D1NP-046 WT:B Micron LPDDR4X 4266 4G MT53E1G32D2NP-046 WT:B BUG=b:203014978 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I31ec5b84b5ad2e8d0aedf41ceb56f9e5f7fa538a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58313 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-17soc/intel/skylake: switch to common GNVSMichael Niewöhner
Switch to common GNVS. No additional fields to those being present in common GNVS are used by any SKL/KBL device. Thus, they're dropped completely. Change-Id: I87ab4ab05f6c081697801276a744d49e9e1908e0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-10-17Skylake boards: Drop setting useless `IRQ_SLOT_COUNT`Angel Pons
The `IRQ_SLOT_COUNT` value is only meaningful when generating a PIRQ table. None of these boards do it, so specifying this value achieves absolutely nothing. Drop it to prevent further useless copy-pasting. Change-Id: I2d63b850c03fc1471c0eef180e8b621311b2c336 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-10-16soc/amd/stoneyridge/include/iomap: rename I2C[ABCD]_BASE_ADDRESS definesFelix Held
Picasso and Cezanne define and use APU_I2C[01234]_BASE for the base addresses of the I2C controllers, so align Stoneyridge with this. The ACPI device names aren't changed from I2C[ABCD] to I2C[0123] for now since this might change behavior in the OS and would also change the resulting binary of a timeless build. TEST=Timeless build results in identical image for Google/Treeya. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9c400c073eba5c14bd35703b717f75df89a8719d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58370 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-16mb/google/brya/var/taeko: Add fw_config probe for GL9750 and RTS5232SJoey Peng
Add support for SD card reader GL9750 and RTS5232S BUG=b:203014989 TEST=FW_NAME=taeko emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I4353a094e2035ce94b5dd1a737e7e7009ad0614e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-16mb/google/brya/variants/primus: To fine tune WWAN power sequencingAriel Fang
Follow the spec to correct the WWAN poweron and powerdown sequences. BUG=b:195625346 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: I232d283a9d6093f5da64fcdce44e5cb640e3df0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58319 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-15mb/google/brya/var/taeko: Include driver for GL9763E for eMMC boot diskKevin.Chang
Support GL9763E as a eMMC boot disk BRANCH=none BUG=b:202192686 TEST=enable DRIVERS_GENESYSLOGIC_GL9763E and check eMMC on taeko. Cq-Depend: chromium:3153210 Signed-off-by: Kevin.Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I5db2b229ce1bbea54efe15f5288f13f8d4656899 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com>
2021-10-15mb/google/guybrush/bootblock: add comment about LPC_LDRQ0_PU,PD_ENFelix Held
The definition of those bits changed between Picasso and Renoir/Cezanne so add a comment where those bit definitions are used as well. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If1cf4b06fc35f94cbd482f2869fcc64739e7d272 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15mb/google/guybrush/bootblock: drop redundant clearing of LPC decodesFelix Held
The writes were originally added due to being part of the initialization sequence in the reference code, but coreboot already has those registers cleared by the time we reach this part of the code, so we can drop these redundant writes. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I43344460e5355664841d77daf1df3fd386e047e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15mb/google/kahlee/treeya/audio: use proper I2C base address defineFelix Held
I2C_BASE_ADDRESS is the beginning of the MMIO space that contains the I2C controllers MMIO. I2C[ABCD]_BASE_ADDRESS are the base addresses of the 4 I2C controllers, so use I2CA_BASE_ADDRESS instead here. TEST=Timeless build results in identical image for Google/Treeya. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie8d6a438f76cd33929f5070f9ec6b2f280f471a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: This CL did not handle Intel GPIO correctly. We need to add GPIO_EC_IN_RW into early_gpio_table for platforms using Intel SoC. Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57951 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-15mb/google/dedede/var/corori: Configure I2C times for TouchpadIan Feng
Configure I2C high / low time in the device tree to ensure Touchpad I2C CLK runs accurately between 380 kHz and 400 kHz. Measured I2C frequency just as below after tuning: Touch Pad CLK: 389.2 KHz BUG=b:202787528 TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz Change-Id: I0f9d062fc611de0062a39849aee1174268391682 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-15mb/google/dedede/var/sasukette: Add PIXA2635 touchpadZhi Li
Add PIXA touchpad into devicetree for sasukette. BUG=b:202796169 BRANCH=dedede TEST=built sasukette firmware and verified touchpad function Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: I5bc8353692a753ec9254ab02b4ff0481386624b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-15mainboard: Drop invalid `VGA_BIOS_FILE` defaultsAngel Pons
If the VGA BIOS file path for `VGA_BIOS_FILE` in a mainboard's Kconfig does not exist in the coreboot tree (including submodules), drop it. These files should be stored in the `site-local` subdirectory and the paths specified for each board in `site-local/Kconfig`. For example: config VGA_BIOS_FILE default "site-local/x200_vbios.bin" if BOARD_LENOVO_X200 Note that this is just an example. There are better ways to structure one's `site-local` subfolder. Using the `CONFIG_MAINBOARD_DIR` option would be one of them, though variants may still need special handling. Also, update autoport to not generate `VGA_BIOS_FILE` defaults. Change-Id: I1b5dfba035a42d7943f270f95fb7d32b285584d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-10-14mb/google/guybrush: Fix variant_has_pcie_wwan helperKarthikeyan Ramasubramanian
variant_has_pcie_wwan helper returns true if gpp_bridge_2 PCIe engine is enabled. On some variants, this engine is used by storage controllers. Fix it by adding a weak override that returns no PCIe WWAN by default. BUG=None TEST=Build and boot to OS in Guybrush. Ensure that PCIe WWAN is enumerated on boards where it is stuffed. Change-Id: I07b9dd8fc5c8c3e1557f9268c1176d4a3cade1af Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-14mb/google/hatch/var/scout: set correct i2c configurationMatt Ziegelbaum
Scout only uses I2C 1, 2, and 3 in DVT units. This removes extraneous I2C configuration copied from Puff. BUG=b:202195805 TEST=Boot scout, verify no more errors due to missing I2C devices Change-Id: Ide70a53e83b3e14540873062e3bef24d1134d2e1 Signed-off-by: Matt Ziegelbaum <ziegs@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-14mb/google/guybrush: Disable HAVE_ACPI_RESUME / S3Rob Barnes
S3 is not currently functional on Guybrush. Remove support from ACPI. BUG=b:202401767 b:181766974 TEST=Boot Guybrush Confirm 'deep' is not in /sys/power/mem_sleep Confirm S0ix suspend/resume still works BRANCH=None Change-Id: I9ed3e051f7f2e411670649ac2528a6f40229bdc6 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-14mb/google/guybrush: Assert WWAN_AUX_RST_L on S0i3 entryKarthikeyan Ramasubramanian
Currently WWAN_AUX_RST_L is in S5 domain and does not get asserted on S0i3 entry. Based on the schematics, the pull-down on that signal leads to 10 mW power leakage on S0i3 entry. Assert the signal on S0i3 entry to achieve some power savings and de-assert it on S0i3 exit. BUG=b:195748540 TEST=Build and boot to OS in Guybrush. Ensure that the signal gets asserted on S0i3 entry and de-asserted on S0i3 exit. Trigger suspend/resume cycles and ensure that the WWAN module is enumerated after each cycle. Change-Id: I43c8655ee5209779748e4365db973e094cb08aca Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58275 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-13mb/google/brya/variants/brask: Init overridetreeAlan Huang
Init overridetree based on the schematics. Refer to brya0/overridetree.cb to update the settings of the devices including DPTF, WIFI, NAU8825 and etc. Refer to kano/overridetree.cb to update the SSD settings (pcie4_0). TODO: DPTF and USB positions will be further updated later. BUG=none TEST=Build Pass Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I30d26a47fe93736c63b578c9180b148ef73e8b9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-13mb/google/guybrush: Re-arrange override speed configKarthikeyan Ramasubramanian
Currently override speed config is applied only for non EM100 cases. For EM100 case, override speed board version defaults to 0 leading to "comparison of unsigned expression >= 0 is always true" error. Fix this error by defining the override speed config for both EM100 and non-EM100 use-cases. BUG=None TEST=Build Guybrush for both EM100 and non-EM100 cases. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Id8ee7b01c69c4555d6e6a7b0d5f095ea3aaf3405 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58309 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-13mb/google/fizz: use SaGv_FixedHighMatt DeVillier
No need for dynamic config (and the additional RAM training time) on a Chromebox; always use high power/high performance mode. Change-Id: I0295bac619af45a0d82da2bf39985c8bdcb77d5e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-13mb/google/wyvern: use SaGv_FixedHighMatt DeVillier
No need for dynamic config (and the additional RAM training time) on a Chromebox; always use high power/high performance mode. Change-Id: I8ad773d1c616b746235ec67b98b83c5910464140 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-13mb/google/guybrush: Override SPI Fast speedsKarthikeyan Ramasubramanian
Add support to override SPI fast speeds based on board version from both bootblock and verstage. Overrides apply for Guybrush only and SPI speed is overridden from 66 MHz to 100 MHz starting board version 4. This will help to improve the boot time on board version by ~60 ms and still allow the old boards to boot with 66 MHz. BUG=b:199779306 TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I5bf03ab8772f27aca346589e9c5662caf014d0d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13mb/google/guybrush/var/nipperkin: update fw_config fieldKevin Chiu
update fw_config for nipperkin BUG=b:196909635 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Icd2c5509450e70aed158f146179f3a7fa24b547a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-13mb/google/poppy: set SMBIOS enclosure type for all poppy variantsMatt DeVillier
Some poppy variants did not select a system type, which led to the default desktop type being set. Select the best fit enclosure type for each variant. Alphabetize the variant-specific options for improved readability. Change-Id: I7c23f8fa3ae1de67f7a68b8a4e9ec16c4e8044df Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-12mb/google/dedede/var/sasukette: Generate SPD ID for Samsung K4U6E3S4AB-MGCLZhi Li
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL BUG=b:202480992 TEST=emerge-dedede coreboot Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: I811f32defd50a940a09f238d38c962d2caf42855 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-12mb/google/guybrush/var/nipperkin: update MAX98360 HID to MX98360APatrick Huang
Update MAX98360 ACPI HID from "MX98357A" to "MX98360A" BUG=b:198716348 TEST=Build nipperkin, codec is functional with new machine driver. Cq-Depend: chromium:3195465 Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: I8a1155848856db0cc4f42cfee0d914f8d1186b34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-11mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO DescriptorMatt Papageorge
coreboot normally owns PCIe resets for all Cezanne based systems. However during S0i3 resume coreboot cannot intervene for S0 GPIOs (S5 carry over fine) so we needed an alternate way to de-assert this reset on guybrush. This change feeds in the given S0 reset GPIO (69 in this case) so that SMU may de-assert this reset on S0i3 resume. BUG=b:199780346 TEST=With latest FSP verify SD device trains each of 10 cycles Cq-Depend: chrome-internal:4157948 Change-Id: Ieee31651db30147fda84ee1aa31df7cb1c206356 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58198 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-11mb/google/guybrush: drop printk in bootblock_mainboard_early_initFelix Held
bootblock_mainboard_early_init gets called before console_init. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia5a1da336e8dfc451177a5319a656c407c9fef7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11mb/google/guybrush/bootblock: add comment to PM_ACPI_CONF writeFelix Held
Document what setting the PM_ACPI_S5_LPC_PIN_MODE and PM_ACPI_S5_LPC_PIN_MODE_SEL bits causes. The corresponding code will eventually be factored out and moved to the Cezanne SoC code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I10e3eee5cfc1c5ba2c88b8b7e83e96e481f787e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11mb/google/guybrush: simplify LPC_MISC_CONTROL_BITS updateFelix Held
Since the LPC_LDRQ0_PD_EN gets set right after it got cleared, we can remove the clearing of that bit. This is split off from the previous patch to be able to use timeless build to verify that the previous patch didn't change any behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieb300e7c7ce7e74c32ebdade0360ee4bd499b11a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11mb/google/guybrush: Use register and bit defines for eSPI setupRaul E Rangel
It's hard to understand what this code is doing because it uses hard coded values, so use the register and bit defines instead. BUG=none TEST=Timeless build for guybrush results in identical binary. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d74ed3b9b4984ab1e2a22c50375baf9c9589df0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-11mb/google/fizz: Drop broken USB ACPI codeMatt DeVillier
Fizz's USB ACPI code is intended to allow the OS to control port charging power, but since Fizz's ports are dumb (vs smart), it controls power to the port itself. The end result is that active ports become disabled when rebooting from Windows (10/11), and power is not restored until the device is powered down (a warm reboot is not sufficient). Subsequent Chromebox models (eg, Puff-based variants) don't bother with EC-controlled USB port power, so just drop it since it's problematic and provides no benefit. Test: boot Windows 10/11, reboot, observe active USB ports still functional (eg, USB KB still works) Change-Id: I2c13d49b3ce8de8b0a38512db3c57d0c8ecbf0ad Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-10-11mb/google/caroline: Update _HID for digitizerMatt DeVillier
Caroline uses a Wacom digitizer, so adjust the ACPI HID so that the proper drivers attach under Windows/Linux. Change-Id: I732b09001dc41a91a32a5f9260abdab435b28b8a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/google/guybrush: Build chromeos.c in verstageHsuan Ting Chen
Before attempting another commit 6260bf71 (vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main), ensure that guybrush builds chromeos.c in verstage to call get_ec_is_trusted() in vboot verstage_main(). Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Ic22519fdde1b18f6ce0237022dee02ca37181a74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/google/guybrush: Add GPIO EC in RW to early GPIO tablesHsuan Ting Chen
Before attempting another commit 6260bf71 (vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main), ensure that guybrush programs GPIO_EC_IN_RW (GPIO_91) as an early GPIO so that it can be read from in verstage. Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Ia6dcb225bbca89f3a873aad75a7d67625cdd3742 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-10-11mb/google/dedede/var/galtic: Add fw_config probe for ALC5682-VD & VSFrankChu
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:198713670 TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Iaba136a836b89f42411474ae733380e345cce687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58162 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-11mb/google/dedede/var/pirika: Add Synaptics I2C touchpad deviceAlex1 Kao
Add Synaptics touchpad device support in devicetree. BUG=b:201043984 BRANCH=dedede TEST=Touchpad device function is OK Change-Id: Ifb240d7113e401de827384697fc752a76fbf7ac7 Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-11mb/google/brya/var/redrix: select CHROMEOS_DSM_PARAM_FILE_NAMEWisley Chen
Enable CHROMEOS_DSM_PARAM_FILE_NAME to report dsm parameter file name. BUG=b:197076844 TEST=build and check SSDT. Change-Id: I726e5854bc6a8fb125cb3b7572ddedff49c3c403 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-11mb/google/dedede/var/corori: Add ssfc codec ALC5682-VS supportIan Feng
Add ALC5682-VS codec support in corori. ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO field of ssfc. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:201372531, b:194436265 TEST=ALC5682-VD/ALC5682-VS audio codec can work. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I2f3edb0b594066714b42050a411103a215e68b12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2021-10-11mb/google/guybrush/var/nipperkin: Enable RTD3 support for eMMC as NVMeKevin Chiu
nipperkin has different H/W topology to guybrush that the eMMC device is on a different GPP: guybrush: GPP3 nipperkin: GPP2 Hence we need to enable RTD3 for nipperkin additionally which refers to this one: https://review.coreboot.org/c/coreboot/+/54967 BUG=b:200246826 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage run suspend test on eMMC sku Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I1dca8f9e4739514d2d024374d8686f27b25582a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-08mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tablesTim Wawrzynczak
Before attempting another commit 6260bf71 ("vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"), ensure that brya's variants all program EC_IN_RW as an input GPIO in bootblock so that it can be read from in verstage. Change-Id: I6b1af50f257dc7b627c4c00d7480ba7732c3d1a0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
2021-10-07mb/google/brya: Disable unused i2s pins for BT offloadSugnan Prabhu S
BT offload hardware design is using only i2s0 pins. Need to disable i2s2 pins which are not used. As per the hardware spec there is an OR operation between vgpio and physical gpio pins related to i2s2. During BT offload configuring the i2s2 pins to its native function is causing offload issue on proto 2 boards. BUG=b:201736222 TEST=Verified BT offload on brya on proto 1 and proto 2. Change-Id: Ifbc53848c6ad12e537216cac3c2871088c094f3d Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-10-07mb/google/dedede/var/bugzzy: Update GPP_D5 configurationSeunghwan Kim
As we checked the panel doesn't display firmware screen if we hold GPP_D5(TOUCHSCREEN_RESET) low on bugzzy. It's because of that bugzzy uses the built-in touch screen on the panel, the panel seems like under reset state by the TOUCHSCREEN_RESET signal. This change sets default GPP_D5 level to high for bugzzy. BUG=b:None BRANCH=dedede TEST=built and verified bugzzy showed firmware screen Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I53e4fc52ceb14ba23c22d3c105f65634b09029f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Doan <edoan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-07mb/google/brya: Add PsysPmax setting to 145WRyan Lin
This patch adds the setting of PsysPmax to 145W according to the brya board design. BUG=b:195615830 TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is passed to FSP by enabling FSP log & Boot into the OS Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd Signed-off-by: Ryan Lin <ryan.lin@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-07sc7280: Add SHRM firmware supportRavi Kumar Bokka
SHRM is a system hardware resource manager. It is used to manage run time DDRSS activities. DDRSS stands for DDR subsystem. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board by trying DDR clocks which through SHRM RSI command. Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-05src/mainboard to src/security: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-04mb/google/trogdor: Add new vaviant quackingstickSheng-Liang Pan
New boards introduced to trogdor family. BUG=b:201263032 BRANCH=none TEST=make Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I8299ddda14eb82103f17f8464a14992aa757afa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-04mb/*/brya/variants/brask: Enable dynamic GPIO PMMeera Ravindranath
GPIO PM was disabled for brask to evaluate if longer interrupt pulses are required for ADL. Since ADL requires 4us long pulses (EDS:626817), GPIO PM can be enabled. This change drops the GPIO PM override and re-enables dynamic GPIO PM. TEST=Boot brask to OS, ensure no TPM errors. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b8b66b5526d8b80775cb7588ce6b12181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-10-04mb/google/brya: Enable DDR4 SODIMM for braskDavid Wu
Enable SMBus to support DDR4 SODIMM for brask. Enable 'smbus' in brask device tree and add SPD addressese for the two DIMMs. Separate the Kconfig items of brya and brask. Move HAVE_SPD_IN_CBFS and CHROMEOS_DRAM_PART_NUMBER_IN_CBI to brya and add config SPD_CACHE_IN_FMAP to brask. Add a new section RW_SPD_CACHE to fmd for caching SPD data. The renamed romstage.c is used by both brya and brask and a new function variant_get_spd_info is provided to support the different SPD source types. BUG=b:194055762 BRANCH=None TEST=build pass Change-Id: I41c57a3df127356b8c7e619c4d6144dc73aeac72 Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-04mb/google/brya/variants/kano: Correct MIPI camera infoLai, Jim
Correct OVTI2740 information for Kano: MIPI camera CIO port, HID and Link Freq BUG=b:200974074 TEST=Build and boot on Kano camera driver is not probed before, and it can now be probed properly after this change. Signed-off-by: Lai, Jim <jim.lai@intel.com> Change-Id: I4612c9d42cd59cba0991b763224f77b7af33770b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-02soc/mediatek: Fix I2C failures by adjusting AC timing and bus speedDaolong Zhu
1. The original algorithm for I2C speed cannot always make the timing meet I2C specification so a new algorithm is introduced to calculate the timing parameters more correctly. 2. Some I2C buses should be initialized in a different speed while the original implementation was fixed at fast mode (400Khz). So the mtk_i2c_bus_init is now also taking an extra speed parameter. There is an equivalent change in kernel side: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/i2c/busses/i2c-mt65xx.c?h=v5.15-rc3&id=be5ce0e97cc7a5c0d2da45d617b7bc567c3d3fa1 BUG=b:189899864 TEST=Test on Tomato, boot pass and timing pass at 100/300/400/500/800/1000Khz. Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com> Change-Id: Id25b7bb3a76908a7943b940eb5bee799e80626a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58053 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-01mb/google/dedede/var/bugzzy: Update device treeSeunghwan Kim
Update bugzzy device tree override based on the EVT schematics. BUG=b:195215785 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: Iba8e3fd24461b4228c6e6fa933c0093e3e45ee97 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-01mb/google/brask/var/brask: Configure GPIOs according to schematicsDavid Wu
Update initial gpio configuration for brask BUG=b:197385770 TEST=emerge-brask coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I71026565b876739d2a08ef79940f47c476ca70a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58041 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-01mb/google/brya: move MILLIWATTS_TO_WATTS macro in header fileSumeet Pawnikar
Move MILLIWATTS_TO_WATTS macro in power_limit header file so all other files can use the same macro. BUG=None BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Ic7ecba06b0e0a47546f7307cbfbc3ce0fc634bc3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01mb/google/brask: Correct SSD power sequenceEric Lai
M.2 spec describes PERST# should be sequenced after power enable. Follow up commit 658d7c5 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I508f7e21888cc1938aa9a6f0066c17029773974b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01mb/google/brya/var/felwinter: Correct SSD power sequenceEric Lai
M.2 spec describes PERST# should be sequenced after power enable. Follow up commit 658d7c5 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I494e0edc135d730cf7bb437f0196cdf233d970d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01mb/google/brask/var/baseboard/brask: Update GPIO GPP_B5 and GPP_B6David Wu
Update GPIO GPP_B5 and GPP_B6 based on schematics. BUG=b:197385770 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If83e02eec7c48b9ab41d346aa8baef7c0c881df1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2021-10-01mb/google/brya/var/kano: Add Synaptics touchpadDavid Wu
Add Synaptics touchpad for kano. BUG=None TEST=emerge-brya coreboot and check touchpad function work. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Iec43aaa9525309d2a0e3c9822038869786f5fe66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-30mb/google/brya/variants/gimble: Correct SSD power sequenceMark Hsieh
M.2 spec describes PERST# should be sequenced after power enable. BUG=b:201512872 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie164ddb29f947e190fa87b31165e3c84b07926e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58034 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29google/trogdor: Always initialize eDP bridge I2C QUP firmwareJulius Werner
In CB:52662 when MIPI display support was added, we accidentally changed the code flow for eDP displays such that i2c_init() will no longer be called when display_init_required() is false. This is a problem because on this platform, i2c_init() does not just prepare the I2C controller for firmware use, it also loads firmware to the controller that makes it behave like an I2C device in the first place -- a step that the kernel cannot later do on its own if the firmware didn't already do it. Skipping this initialization means the I2C controller becomes unusable to the kernel. This patch fixes the issue by making the i2c_init() unconditional again. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ie4546c31d87d91113eeef7dc7a18599a87e6d6eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58026 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29herobrine: Initialize SAR sensor QUPShelley Chen
Initializing SAR sensor (QUP2, address 0x988000) BUG=b:198456205 BRANCH=None TEST=Boot into kernel and make sure no i2c errors for 0x988000 in dmesg Change-Id: I75b0e9173d4c49b5e7308158a678964d6637b225 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-29mb/google/herobrine: Change preprocessor to C codeShelley Chen
BUG=b:182963902 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -c max -B Change-Id: I10f8a9682200b883474dc385331c5dae84cbdb08 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-29herobrine: Add fingerprint power sequencingShelley Chen
For Herobrine variants that include a finger print sensor, we will need to power sequence it. We are using the same FP sensor as trogdor, so we will follow the timings used for trogdor from CL:2695676. BUG=b:198474942 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -c max -B Change-Id: Ica6eafc47cf1b95eeb8d94c6e0a8c88519665e3f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58021 Reviewed-by: Alexandru Stan <amstan@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29mb/google/guybrush/var/nipperkin: Add ALC5682I and MAX98360 supportPatrick Huang
Add ID "10029836" for machine driver, "RTL5682" for ALC5682I and "MX98357A" for MAX98360. BUG=b:198716348 TEST=Build nipperkin, codec is functional with new machine driver. Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: Iab9d11adb7cd08effa2a9b6a627832bd89cb3cb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-29mb/google/dedede/var/boten: Add fw_config probe for ALC5682-VD & VSStanley Wu
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define SSFC bit 9-11 in coreboot for codec within ec. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:193694180 TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: Iba91b51cbbe7adc502372c9a026867de61d8035d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-29mb/google/mancomb: Delete board supportKarthikeyan Ramasubramanian
Mancomb mainboard has been cancelled. Hence delete the board support. BUG=b:190404616 TEST=None Cq-Depend: chromium:3188634 Change-Id: I3ce02efb1fa5ea488447099abe08da6051fb6fc6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-29mb/intel/adlrvp, mb/google/brya: Add ADLP 242 PLx configurationsTracy Wu
Add ADLP 242 sku PLx related settings, which follow the settings of ADLP 282 sku (both are 15w). BUG=b:201253904 TEST=USE='fw_debug' emerge-brya intel-adlfsp coreboot chromeos-bootimage Change-Id: If9b60893ab3e2c4a88e7d2cf45223c5fbce6f847 Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-29mb/google/brya: Update PCH power cycle related durationsTim Wawrzynczak
The voltage rail discharge times have been measured, so therefore the boot time on a cold boot when the CSE must go through a global reset and thus a trip to S5 can be optimized. Select the lowest applicable value for each PchPmSlp UPD that can be used with these measurements. This is programmed in the baseboard because the measured discharge times leave (what should be) plenty of margin for variants to also not violate any power sequencing guidelines from the PDG. BUG=b:184799383 TEST=verified time in S5 during a global reset is ~1s instead of 4s Change-Id: Ia373c47b3967d68ddac21707c6eb4565d9d6519e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-09-29mb/google/dedede: Remove drawcia_legacy board supportKarthikeyan Ramasubramanian
Support for drawcia_legacy board is cancelled. Hence remove the board support. BUG=b:192256341 TEST=None Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I76cd3e388439f5aee94a17fe35ae210f449cfbfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-09-29mb/google/dedede: Remove Boten_Legacy board supportKarthikeyan Ramasubramanian
Support for Boten_legacy board is cancelled. Hence remove the board support. BUG=b:192256341 TEST=None Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If26dc869ff95dff70c0f83a13f6f727aa5992dbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/57999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-09-29mb/google/dedede: Remove wheelie variant board supportKarthikeyan Ramasubramanian
Wheelie variant board has been cancelled. Remove wheelie variant board support. BUG=b:192256341 TEST=None Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I3ad5bc1c987feb55183a663937794781c7301a48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-09-29mb/google/dedede: Remove cappy variant supportKarthikeyan Ramasubramanian
Cappy variant is cancelled. Hence delete the cappy variant support. BUG=b:192256341 TEST=None Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If43188a3e6bf4f4449c7e2d08be7609efe58dca1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-09-28mb/google/brya/variants/taeko: add NVMe GPIOs to early_gpio_tableKevin Chang
NVMe needs extra time to run boot process, enable power and deassert reset for NVMe earlier in the boot flow that taeko can successfully boot into OS with non-serial coreboot. BUG=b:199969366 & b:200711149 TEST=Build FW and test with non-serial FW reboot 20 times pass. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I032c5b90fb2148c4075d6ead3e4161c0cc659b20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-28mb/google/dedede/var/magolor: Add custom Wifi SAR for magmaTyler Wang
Add wifi sar for magma. Due to fw-config cannot distinguish between magolor and magma. Using sku_id to decide to load magma custom wifi sar. BUG=b:192423859 TEST= emerge-dedede coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Iac15e958e61be6e3c136fb9be18b4695823ad1c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-28mb/google/dedede/var/galtic: Update PL1 min and max for Galith/GallopFrankChu
Update PL1 min and max values to 6 W for Galith/Gallop systems. BUG=b:201010771 BRANCH=None TEST=Build and verify on Galith/Gallop system Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I0dfda3c2c830a2ce203668431f396859e782aa3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-28mb/google/brya/primus: modify HID to MX98360A for next build phaseMalik_Hsu
For the next build phase, modify the HID of the speaker amp to MX98360A. BUG=b:199098681 BRANCH=none TEST=build coreboot without error Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I0c318464fca7d35bbffd7ea0f5694b83acedff0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-28mb/google/dedede/var/kracko: refactor DPTF section for overridesRobert Chen
Refactor DPTF section of code under the kracko overridetree. This makes kracko override dptf section of dedede/baseboard, because the DPTF tool's CRT, PSV and TSR3 settings are different than expected. BUG=b:187482019 BRANCH=dedede TEST=Built and tested on dedede system Change-Id: Iacc543f961a7f4652ee8583920b1794f916c7ec9 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-27mb/google/brya/var/kano: Move max98373 amp ACPI info to I2C0David Wu
Move max98373 amp ACPI info to I2C0 according to kano's schematics version KANO_MLB_Proto_0811. BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I8f7a7938dd407666e0104ba64b22da85216a145f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-27mb/google/brya: Correct SSD power sequenceEric Lai
SSD sometimes can't be detected in in warm/cold boot stress. M.2 spec describes SSD_PREST should be sequenced after power enable. BUG=b:199822704 TEST=SSD was always discovered in warm/cold boot stress. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If0a9e36cda4dc91bbccec02f39ccb9b658d24056 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-27mb/google/hatch/moonbuggy: Update DPTF parametersKenneth Chan
Update the DPTF parameters received from the thermal team. BUG=b:188596619 TEST=emerge-ambassador coreboot Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I081963b97ed2dae0f5d026f6443c954b52347a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57919 Reviewed-by: Joe Tessler <jrt@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-12 17:00:35 +0000