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2020-06-01mb/google/hatch: Add Noibat variantEdward O'Callaghan
A verbatim copy of variants/puff. BUG=b:156429564 BRANCH=none TEST=none Change-Id: I8c76d468177e1f3fcab53e0790599041b1a944d8 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41851 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-29mb/google/dedede: Enable Heci1 deviceAamir Bohra
Enable heci1 device from devicetree for PCI enumeration. This is required for ME status dump using HFSTSx resgisters in PCI config space. Heci1 device is later disabled through heci disable flow. TEST=Build, boot waddledoo. ME status dump is seen in console logs. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: Icb77db3f0666c2d14ebef2c3214564346d1fd3c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-29mb/google/dedede: add new SPD SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16Marco Chen
The first DRAM part supported by SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16 is NT6AP256T32AV-J2 so the SPD content is generally extracted from it's SPD. On the other hand, SPD bytes 4 / 6 / 13 were amended to follow SoC's requirement. BUG=b:152277273 BRANCH=None TEST=build the image successfully. Change-Id: If6fb0855a961d1c68315a727466bf45569cf2597 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41813 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-29mb/google/hatch: Select the fmd files for puff baseboardV Sowmya
This patch selects the fmd files based on config BOARD_GOOGLE_BASEBOARD_PUFF and also renames the files to align with basebaord name and layout size. BUG=b:154561163 TEST=Built puff and verified that it selects the right fmd file. Change-Id: Ice6196ca778c6c118ce89e1510a445339a5c3455 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-29mb/google/hatch: Select the fmd files for hatch baseboardV Sowmya
This patch selects the fmd files based on config BOARD_GOOGLE_BASEBOARD_HATCH and also renames them to add the baseboard name and layout size tags. BUG=b:154561163 TEST=Built hatch variants and verified that they select the right fmd files. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I5d99ae28cc972ffa635adf100b756c36e168a8f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-29mb/google/hatch: Select BOARD_ROMSIZE_KB_16384 by defaultFurquan Shaikh
All hatch and puff variants use 16MiB SPI flash except the legacy ones which used 32MiB flash. Kconfig.name is updated to select BOARD_ROMSIZE_KB_32768 only for the legacy variants and BOARD_GOOGLE_HATCH_COMMON selects BOARD_ROMSIZE_KB_16384 by default if BOARD_ROMSIZE_KB_32768 is not selected. TEST=Verified using abuild --timeless that all hatch variants generate the same coreboot.rom image with and without this change. Change-Id: I708506182966936ea38562db8b0325470e34c908 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41662 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-29Puff: Disable EFS1 for variantsDaisuke Nojiri
VBOOT_EC_EFS is for EFS1 and EFS1 is deprecated. Puff uses EFS2 and its variants should follow. BUG=b:157372086 BRANCH=none TEST=emerge-puff coreboot Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I581f137b506a96df45e5bed21833856bb4f6aaa3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-05-28mb/google/volteer: Add PMC.MUX.CONx devices to devicetree for VolteerTim Wawrzynczak
Volteer's MUX connections are known, and can now be described in ACPI tables. Port 1 has the only oddity, with SBU lines staying fixed in the CC1 orientation. TEST=Dump SSDT tables on Volteer, and confirm (coalesced for brevity): Scope (\_SB.PCI0.PMC) { Device (MUX) { Name (_HID, "INTC105C") Device (CON0) { Name (_ADR, 0) Name (_DSD, Package() { Package () { "usb2-port-number", 9 }, Package () { "usb3-port-number", 1 }, }) } Device (CON1) { Name (_ADR, 1) Name (_DSD, Package() { Package () { "usb2-port-number", 4 }, Package () { "usb3-port-number", 2 }, Package () { "sbu-orientation", "normal" }, ... } } } Change-Id: Id361b2df07e87ad72b6a59a686977b3f424e8ecf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-28mb/google/dragonegg: remove abandoned projectAaron Durbin
Dragonegg is no longer in development nor used. Remove it. Change-Id: Ida30dba662bc517671824f8b70b73b4856836e97 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28mb/google/zork/berknip: Replace full GPL header with SPDX linePatrick Georgi
Change-Id: I858f870db0babcb51c594570e8136436ecbb0d1d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41823 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ↵Furquan Shaikh
ports"" This reverts commit 1726fa1f0ce474cde32e8b32be34a212aff3ffba. Reason for revert: Resource allocator is split into old(v3) and new(v4). So, this change to enable hotplug resource allocator for volteer can land back. BUG=b:149186922 Change-Id: Ib6a4df610b045fbc885c70bff3698a032b79f770 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-28Remove new additions of "this file is part of" linesElyes HAOUAS
Change-Id: I6c69dcad82ee217ed4760dea1792dd1a6612cd8b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-28mb/google/volteer: Create terrador variantDavid Wu
Create the terrador variant of the volteer reference board BUG=b:156435028 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_TERRADOR Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I088861d1f8b7b4ee8de1e5ab6c7d3109ffd0531b Reviewed-on: https://review.coreboot.org/c/coreboot/+/41718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-05-28mb/google/deltaur: Remove devicetree chip drivers/netKyösti Mälkki
Change-Id: Ia56305e9554b666f8eaf590a91be84e5cac4c75c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41701 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28mb/google/hatch: Drop rt8168 Kconfigs for baseboard hatchFurquan Shaikh
This change drops rt8168 ethernet Kconfig options for baseboard hatch since it does not really support an ethernet device. Change-Id: I7c19dbeb2f64b0643b082a9c588f8b14db4dfb8a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41661 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28mb/google/hatch: Split Kconfigs into BASEBOARD_HATCH and BASEBOARD_PUFFFurquan Shaikh
mb/google/hatch supports two different reference platforms - Hatch and Puff. This change adds Kconfigs BOARD_GOOGLE_BASEBOARD_PUFF in addition to BOARD_GOOGLE_BASEBOARD_HATCH to better organize the Kconfig selections and reduce redundancy. In addition to this, a new config BOARD_GOOGLE_HATCH_COMMON is added that selects all the common configs for both baseboards. TEST=Verified using abuild --timeless option that all hatch variants generate the same coreboot.rom image with and without this change. Change-Id: I46f8b2ed924c10228fa55e5168bf4fe6b41ec36c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41660 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28mb/google/volteer: Select SX9310 driver in KconfigDuncan Laurie
There are SX9310 devices present in devicetree.cb but the driver is not enabled so it is not getting used. Change-Id: I625233013a2e14eaf758e56027774fbf5df3bc83 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41700 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28mb/google/dedede: Enable Intel Speed Shift TechnologyKarthikeyan Ramasubramanian
Enable Intel Speed Shift Technology (ISST) by default. Disable ISST in waddledee and waddledoo variants on early phases. BUG=b:151281860 TEST=Build and boot the mainboard. Ensure that cpufreq driver to configure P-states is enabled in kernel on boards where board version is provisioned. Change-Id: Id65d7981501c2f282e564bfc140f8d499d5713e8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-05-27mb/google/zork: Add Picasso based Zork mainboard and variantsRaul E Rangel
This is a copy of the mb/google/zork directory from the chromiumos coreboot-zork branch. This was from commit 29308ac8606. See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork Changes: * Minor changes to make the board build. * Add bootblock.c. * Modify romstage.c * Removed the FSP_X configs from zork/Kconfig since they should be set in picasso/Kconfig. picasso/Kconfig doesn't currently define the binaries since they haven't been published. To get a working build a custom config that sets FSP_X_FILE is required. BUG=b:157140753 TEST=Build trembyle and boot to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26mb/google/nightfury: Enable max98390 ampSeunghwan Kim
This change enables max98390 audio codec on nightfury. BUG=b:149443429 BRANCH=firmware-hatch-12672.B TEST=Built and checked audio function on nightfury Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: Ic9678583370cf5e41c87e35ba12f86572708fada Reviewed-on: https://review.coreboot.org/c/coreboot/+/41127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-26mb/google/deltaur: Update audio verb table for jack detectionJairaj Arava
Additional verb changes are needed for Headset and Mic detection to work properly. BUG=b:155360937 TEST=Headset and Mic detection is working in the UI audio tray Change-Id: I184a05949f5522e929969156b72629be3d957e3f Signed-off-by: Jairaj Arava <jairaj.arava@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41642 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26mb/google/volteer: fix some white space nitsNick Vaccaro
Convert spaces to tabs in volteer variant makefiles, and remove empty comment lines from file headers. BUG=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and verify volteer boots to kernel. Change-Id: I6c818c3adcc55ce89707efff6dd9a6bce512daa5 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41587 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26soc/intel/tigerlake: Remove MIPI clock setting from devicetreeSrinidhi N Kaushik
In Tiger Lake we have support for enabling MIPI clocks at runtime in ACPI. Hence remove setting pch_islclk from devcietree and chip.h. Also update functions which reference pch_isclk. BUG=b:148884060 Branch=None Test=build and boot volteer and verify camera functionality Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I6b3399172c43b4afa4267873ddd8ccf8d417ca16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41570 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26apollolake: update processor power limits configurationSumeet R Pawnikar
Update processor power limit configuration parameters based on common code base support for Intel Apollo Lake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on octopus system Change-Id: I609744d165a53c8f91e42a67da1b972de00076a5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41233 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26mb/google/volteer: Enable D3HotEnable and D3ColdEnable for VolteerJohn Zhao
This explicitly enables both of TCSS D3HotEnable and D3ColdEnable from Volteer devicetree.cb setting. BUG=:b:146624360 TEST=Built and booted on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I1a168ad87169c0f6633704c55c9293aa25710188 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-05-26Mushu: Enable PCIe 1d.4 to enable dgpuShelley Chen
BUG=b:147249494,b:147249494 BRANCH=None TEST=boot up mushu check cbmem -1 to make sure PCIe 1d.4 is enabled Change-Id: I36404217f0ecffb0cce1105e76f507c9062df053 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-26mb/google/volteer: Enable ELAN trackpad wake suspend functionWilliam Wei
BUG=b:156990317 TEST=emerge-volteer coreboot chromeos-bootimage Boot to kernel and check the ELAN trackpad can wake up unit from suspend. Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com> Change-Id: If4bea8a9742f7533be2e51b855cc39ca77d73608 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-26Remove MAYBE_STATIC_BSS and ENV_STAGE_HAS_BSS_SECTIONKyösti Mälkki
After removal of CAR_MIGRATION there are no more reasons to carry around ENV_STAGE_HAS_BSS_SECTION=n case. Replace 'MAYBE_STATIC_BSS' with 'static' and remove explicit zero-initializers. Change-Id: I14dd9f52da5b06f0116bd97496cf794e5e71bc37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-26cannonlake: update processor power limits configurationSumeet R Pawnikar
Update processor power limit configuration parameters based on common code base support for Intel Cannonlake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on drallion system Change-Id: Iac6e6f81343fcd769619e9d7ac339430966834f6 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-26intel/cannonlake: Implement PCIe RP devicetree updateNico Huber
Some existing devicetrees were manually adapted to anticipate root-port switching. Now, their PCI-device on/off settings should just reflect the `PcieRpEnable` state and configuration happens on the PCI function that was assigned at reset. Change-Id: I4d76f38c222b74053c6a2f80b492d4660ab4db6d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-26mb/google/foster: Remove unused 'include <memrange.h>Elyes HAOUAS
Change-Id: Ic26d03d0e695ce0823332d4c6430186c7bfbeac1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-22mb/google/volteer: Add SoundWire codecs to volteer variantDuncan Laurie
Enable drivers for SoundWire codecs and define the topology in the devicetree for the volteer variant with the SoundWire daughter board connected. +------------------+ +-------------------+ | | | Headphone Codec | | Intel Tigerlake | +--->| Realtek ALC5682 | | SoundWire | | | ID 1 | | Controller | | +-------------------+ | | | | Link 0 +----+ +-------------------+ | | | Left Speaker Amp | | Link 1 +----+--->| Maxim MAX98373 | | | | | ID 3 | | Link 2 | | +-------------------+ | | | | Link 3 | | +-------------------+ | | | | Right Speaker Amp | +------------------+ +--->| Maxim MAX98373 | | ID 7 | +-------------------+ This was tested by booting the firmware and dumping the SSDT table to ensure that all SoundWire ACPI devices are created as expected with the properties that are defined in coreboot under \_SB.PCI0: HDAS - Intel Tigerlake HDA PCI device HDAS.SNDW - Intel Tigerlake SoundWire Controller HDAS.SNDW.SW01 - Realtek ALC5682 - Headphone Codec HDAS.SNDW.SW13 - Maxim MAX98373 - Left Speaker Amp HDAS.SNDW.SW17 - Maxim MAX98373 - Right Speaker Amp BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I7782059807416369e0e1ba0d4d7c79dcab0fcbc5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40894 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-22mb/google/volteer: Add overridetree.cb for volteer variantDuncan Laurie
Instead of only using the baseboard devicetree add a placeholder overridetree for volteer and refer to it in Kconfig. This will allow us to add the volteer specific devices here instead of at the baseboard level. BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I7788a5473fc2275a9791fb27e0e4018a0efcd0f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40893 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21mb/google/volteer: set DRAM Max Cycle Time to 15Nick Vaccaro
The DRAM Max Cycle Time (tCKmax) for Samsung's K4UBE3D4AA-MGCL DRAM part should be set to 0xF. BUG=b:157178553, b:156555863 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot a SKU4 volteer to the kernel and run "memtester 6G 100" and verify it completes successfully without error and does not crash. Change-Id: Id95b19fe261e3f57a52a43055acab99af66b14ab Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41634 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21mb/google/volteer: fix error in generic SPDNick Vaccaro
The SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex SPD contained an incorrect SDRAM Max Cycle Time (0 instead of 0x0f). After fixing that error, I noticed that two generic SPDs could be collapsed into one, so I removed one of the duplicate generic SPDs (SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_16Row_DDP_4267.spd.hex), and changed Makefile to collapse volteer's DRAM ID 2 into ID 0. BUG=b:156126658, b:156058720 TEST=Flash and boot a ripto to kernel. Also verified that ripto can boot successfully to the kernel at 4267 MT/sec with FSP built in debug mode with RMT enabled. Change-Id: Ib52bf674ebf91854d3d078015aa640aa7ee98a6f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41345 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20google/trogdor: Fix ram_code and sku_id strappingsJulius Werner
I'm not quite sure what happened when we first added the code for Trogdor strappings but something clearly seems to be wrong. First of all, on newer schematics the RAM_ID_1 pin is actually pin 19, not pin 91. It only used to be 91 on rev0. Whether that was an intentional change or someone just swapped the digits on accident at some point, we're not quite sure anymore, but it seems to be 19 going forward so that is what we should be programming. (ram_code wasn't used for anything on Trogdor rev0 so we don't care about adding backwards-compatibility for that.) The sku_id pins are also somewhat out of whack: first of all, a new SKU_ID_2 pin was added for rev1 that wasn't there on rev0. Second, SKU_ID_0 is not GPIO_114. In fact, it has never been GPIO_114. I have no idea how that number got there. Anyway, fix it. (Like with the ram_code, SKU IDs were also not used for rev0 so we won't make this backwards-compatible.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia14ec74ec2f16ce2661f89d0d597a5477297ab69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-05-20mb/google/endeavour: chrontel: fix interrupt and compat stringJeff Chase
The devicetree declares the chrontel interrupt as GpioInt so the GPIO needs to be configured as such instead of routing directly to APIC. Also update the compatible string to conform to kernel standards. BUG=b:146576073 TEST=install ch7322 driver; send commands using cec-ctl and verify that the interrupt handler is called. Change-Id: I737d951db135c53deb0f3cb956f0d0f275082251 Signed-off-by: Jeff Chase <jnchase@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-20tigerlake: enable DPTF functionality for volteerSumeet R Pawnikar
Enable DPTF functionality for volteer platform BRANCH=None BUG=b:149722146 TEST=Built and tested on volteer system Change-Id: I385fb409ccd291d97369295ff99f21c9430880f9 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41427 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20soc/intel/tigerlake: Move PMC PCI resources under PMC deviceTim Wawrzynczak
Historically in coreboot, the PMC's fixed PCI resources were described by the System Agent (the MMIO resource), and eSPI/LPC (the I/O resource). This patch moves both of those to a new Intel SoC-specific function, soc_pmc_read_resources(). On TGL, this new function takes care of providing the MMIO and I/O resources for the PMC. BUG=b:156388055 TEST=verified on volteer that the resource allocator is aware of and does not touch these two resources: ("PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1") Also verify that the MEM resource is described in the coreboot table: ("BIOS-e820: [mem 0x00000000fe000000-0x00000000fe00ffff] reserved") Verified the memory range is also untouchable from Linux: ("system 00:00: [mem 0xfe000000-0xffffffff] could not be reserved") Change-Id: Ia7c6ae849aefaf549fb682416a87320907fb3fe3 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41385 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20mb/google/volteer: Fix camera dsdt config for ov2740Daniel Kang
Link frequency and a format was not correct for volteer proto 2 ov2740 user-facing camera. The link frequency is calculated in the following way. (max frame width * max frame height * max fps * data format in bps / number of lanes / data rate) + max 35% of overhead For ov2740, (1920 * 1080 * 60 * 10 / 2 / 2) = 311Mhz. 360Mhz after adding 18% of overhead. BUG=b:148428976 BRANCH=none TEST=Build and boot volteer proto 2 board. Start a camera app and check user-facing camera functionalities. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I3b51826e123dec394c1b4eb9a1c5b64b8b11459e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41157 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20mainboard/volteer: Update Aux settings for Port 0Brandon Breitenstein
On Volteer port 0 (MB PORT) does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping. This requires 2 changes setting the TcssAuxOri UPD to 1 for port 0 (Bit 0) and configuring AUXP and AUXN GPIOs to Native Function 6 so SOC can control the orientation BUG=b:145220205 BRANCH=NONE TEST=booted Volteer proto 2 and verified that the AUX channels flip when the cable is flipped Change-Id: Ic81adc24d10322cc305bf0fa4c38514468ea0942 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-05-20mb/google/volteer: Enable EARLY_EC_SYNCCaveh Jalali
This enables EC software sync in romstage. BUG=b:148259137 TEST=verified EC is updated in romstage using coreboot serial console logs. Change-Id: Ibb97c1d57220f7fd74131a5aee450b1ab4b1c982 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41078 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20mb/google/deltaur: Remove WLAN PCIE settingEric Lai
Deltaur uses CNVi WLAN module, this setting is not required. BUG=none TEST=WiFi is functional in OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idb23e271074c8d1e111c559695d4169af5e0d3cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/41495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-20mb/google/deltaur: Add tcss.aslEric Lai
Add tcss.asl to support TCSS power management. For the detail please refer cb:39785. BUG=none TEST=Check TBT PCIe root ports: 00:07.0/00:07.1/00:07.2/00:07.3 /sys/bus/pci/devices/bus:device:func/power suspend and active time can increase. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I432f3d6643de13b08c07e47f799c0ecdfe047de6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41506 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20mb/google/deltaur: Add low power idle tableEric Lai
Add low power idle table to notify EC system is entering s0ix. BUG=none TEST=Power button and keyboard backlight are off when suspending. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Icf4dffe2bd289c15854bbad914c3b34b307254ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/41494 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20mb/google/hatch: Fix Puff variants rom size from 32768 -> 16384 KBEdward O'Callaghan
Originally variants make use of a 32MB chip whereas now they use a 16MB SPI flash. Allow for the coordination of dealing with the transition between phases. V.2: Leave Puff alone at the moment due to the complexity of coordination. BUG=b:153682192 BRANCH=none TEST=none Change-Id: Ic336168ea1a0055c30f718f5540209d2cf69d029 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40897 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove unused 'include <string.h>'Elyes HAOUAS
Unused includes found using following commande: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|atol\|strrchr\|skip_atoi\|STRINGIFY' -- src/) |grep -v vendorcode |grep '<' Change-Id: Ibaeec213b6019dfa9c45e3424b38af0e094d0c51 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-05-18mb/google/{parrot,stout}: Remove unused 'include <elog.h>'Elyes HAOUAS
Change-Id: I7c6f47f03f1c83658f4364f81f6436d7b2f4f377 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-18mb/google/hatch: Add Mushu variant specific DPTF parametersJohn Su
The change applies the DPTF parameters received from thermal team. 1. Set PL1 Max to 25W 2. Set PL2 Max to 44W 3. Update Temp sensor parameters BUG=b:152011093 BRANCH=none TEST=build and verified by thermal team Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I225897832b02f9de6221053b68fbdba30f8b199a Reviewed-on: https://review.coreboot.org/c/coreboot/+/41165 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18mb/google/deltaur: Remove DSP settingEric Lai
Deltaur does not use DSP so remove the DSP setting. BUG=b:155360937 TEST=Recording and playing are working fine in OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I01c076806448fc73980ec02e7558ccf082723d92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-18mb/google/deltaur: Add audio verb tableEric Lai
Add audio verb table provided by vendor. BUG=b:156447983 TEST=Have beep sound when run "devbeep" in CLI. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I807d84de1677459ea027e645488f485b0ac7b2ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/41401 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18mb/google/deltaur: Update audio settingEric Lai
Deltaur uses HDA codec so we need to set iDisplay Audio Codec disconnection and enable HdaAudioLink, otherwise the HDA codec won't respond to commands to execute HDA verbs. BUG=b:156447983 TEST=No timeout error when run "devbeep" in CLI. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I15d2895866abcf68963c9732ed5d05f32096fc92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41397 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18mb/google/dedede: update SPD name based on DRAM characteristicMarco Chen
The index of DRAM_STRAPS indicates to a specific DRAM characteristic instead of a DRAM part number therefore update the existing DRAM SPD binary to the naming by DRAM characteristic. BUG=b:152019429 BRANCH=None TEST=build the image and verify that coreboot log shows the correct SPD info Change-Id: I8ffcf156f37a465209740c5e2a34effb5f1f5d5c Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-18skylake: update processor power limits configurationSumeet R Pawnikar
Update processor power limit configuration parameters based on common code base support for Intel Skylake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on nami system Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-18mb/ripto: Update ALC5682 headset interrupt configurationsShaunak Saha
As per schematics configure headset interrupt as edge both for ripto and volteer baseboard. BUG=b:147085988 BRANCH=none TEST=Build and boot ripto board. Test that jack functionality is working fine and also confirm with evtest. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: I8e1625140ccf55db8cb0fe3c039f1c31c01069b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
2020-05-18mainboard/*/*/*.cb: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: Ia0dbf7b946d42bda11b904a9caff5a402b553b33 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-18mainboard/*/*/Kconfig*: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I7089b29e881d74d31477e2df1c5fa043fe353343 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41358 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-16Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports"Furquan Shaikh
This reverts commit 2412924bc7646fc22b2cb1b9108413fa3e849082. Reason for revert: Resource allocator patches need to be reverted until the AMD chipsets can be fixed to handle the resource allocation flow correctly. BUG=b:149186922 Change-Id: Iea6db8cc0cb5a0e81d176ed3199c91dcd02d1859 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41411 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-15mb/google/volteer: Add delay to WWAN GPIO init sequenceAlex Levin
Based on Fibocom HW user manual RESET should be deasserted at least 20ms after the power on pin. The design for the reset pin is open drain connected to a pull up, so it is set to high-Z (configured as GPIO in) after 20ms. BUG=b:152013143 BRANCH=none TEST=traced the signals using a scope to verify timing is met. Signed-off-by: Alex Levin <levinale@chromium.org> Change-Id: I7c947d1bc4cce1f97383a2f2c254986e182661c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41356 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-14trogdor: Update pull for Sd-card detect pinShaik Sajida Bhanu
Configuring pull for SD-card detect pin. Without this SD-card detection is not working as expected Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Change-Id: I77bf355a049224784a160defa6bee66d0f9ceb75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-05-14sc7180: GPIO: Add I2S configuration for sc7180vsujithk
Configuring GPIO Pins as I2S mode for Audio speaker. Change-Id: I681aa6d0d57671b0fd9b7bc88de6f2cc202a7af0 Signed-off-by: V Sujith Kumar Reddy <vsujithk@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-05-14mb/google/deltaur: Configure GPIO B11 as PMCALERTAnil Kumar
GPIO B11 pin should be configured as PMCALERT function. This is required for the intergrated USB-C feature to work in the SOC BUG=b:154778458, b:156288164 TEST= build and boot coreboot image on deltan. Test Type-C port enumeration on Chrome OS Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I8f995901b0a50d2c74f57aba96f86134c9d569e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41378 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-14mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 portsFurquan Shaikh
This change enables PCIEXP_HOTPLUG to support resource allocation for TCSS TBT/USB4 ports. BUG=b:149186922 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I4cb820e83da40434b00198b934453805e35ef1ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/41156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-13mb/google/puff: add a region to cache SPD dataJamie Chen
This patch adds a SPI rom region RW_SPD_CACHE on Puff and it can be used on spd_cache to reduce reading SPD data from SODIMM by smbus. It's for saving the boot time and it can be used to trigger MRC retraining when memory DIMM is changed. BUG=b:146457985 BRANCH=None TEST=Build puff successfully and verified below two items. 1. To change memory DIMM can trigger retraining. 2. one DIMM save the boot time : 158ms two DIMM save the boot time : 265ms Change-Id: I8d07fddf113a767d62394cb31e33b56f22f74351 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-05-13mb/google/volteer/variants/halvor: add two SPD filesNick Vaccaro
Adds SPD_LPDDR4X_556b_1R_32Gb_8GbD_QDP_4267.spd.hex, which will be used initially for the "H9HKNNNCRMBVAR-NEH" SKhynix part as DRAM ID #0. Adds SPD_LPDDR4X_556b_1R_64Gb_16GbD_QDP_4267.spd.hex, which will be used initially for the "MT53E1G64D4SQ-046 WT:A" Micron part as DRAM ID #1. BUG=b:155423877 TEST=none Change-Id: I5580f602cd411e415dafcb36bd1ffa43c4f02f60 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41076 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13mb/google/volteer/variants/volteer: Add three generic SPD filesNick Vaccaro
- Add SPD_LPDDR4X_200b_1R_16Gb_16Row_DDP_4267.spd.hex, initially used for the SKhynix H9HCNNNBKMMLXR-NEE part with DRAM ID #2 - Add SPD_LPDDR4X_200b_2R_64Gb_ODP_4267.spd.hex, initially used for the SKhynix H9HCNNNFAMMLXR-NEE part with DRAM ID #3 - Add SPD_LPDDR4X_200b_2R_32Gb_QDP_4267.spd.hex, initially used for the Micron MT53E1G32D2NP-046 WT:A part with DRAM ID #4 BUG=b:147857288 TEST=none Change-Id: I60d8bb05a4d6d3608adc7de69efc8623d1ca610d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41126 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13src: Remove unused '#include <stddef.h>'Elyes HAOUAS
Unused includes found using following commande: diff <(git grep -l '#include <stddef.h>' -- src/) <(git grep -l 'size_t\|ssize_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\ |MAYBE_STATIC_NONZERO\|MAYBE_STATIC_BSS\|zeroptr' -- src/)|grep '<' |grep -v vendor |grep -vF '.h' Change-Id: Ic54b1db995fe7c61b416fa5e1c4022238e4a6ad5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41150 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13src: Remove unused '#include <stdint.h>'Elyes HAOUAS
unused includes of <stdin.h> found using following commande: diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|uint8_t\|int16_t\|uint16_t\|int32_t\|uint32_t\|int64_t\| uint64_t\|intptr_t\|uintptr_t\|intmax_t\|uintmax_t\|s8\|u8\|s16\| u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|UINT8_MAX\|INT16_MIN\ |INT16_MAX\|UINT16_MAX\|INT32_MIN\|INT32_MAX\|UINT32_MAX\|INT64_MIN\ |INT64_MAX\|UINT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|UINTMAX_MAX' -- src/) |grep '<' |grep -v vendor |grep -vF '.h' Change-Id: Icb9b54c6abfb18d1e263665981968a4d7cccabeb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41148 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13mb/google/volteer: move SPD files to variant directoriesNick Vaccaro
Memory SPD files for each variant are now stored in the variant's mb/google/volteer/variants/<variant_name>/spd directory instead of storing them in mb/google/volteer/spd. This change moves SPDs to where they are needed and changes the makefile to look for them in their new locations. BUG=b:156126658 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot a proto2 SKU4 to the kernel. Change-Id: I759c979027477a2a4c5489a6b12278799488d6e7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41184 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13mb/google/volteer: Enable keyboard backlight featureAngel Pons
This enables the keyboard backlight feature in ACPI for volteer. BUG=b:156326050 TEST=Verified 'KBLT' shows up in the DSDT ACPI table. Change-Id: Id1b1bb059368b0cc36cb06e6cdb8b989060a1dde Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-13mb/google/dedede/variants/waddledoo: Modify ELAN touchscreen slave addressIan Feng
Modify ELAN EKTH6918 USI touchscreen slave address to 0x10. BUG=b:152936745 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I999967b0f37c82ff7811e3b6117baab795a11195 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-13mb/google/octopus/variants/foob: Disable xHCI compliance modeTommie
When any USB image disk is connected to the DUT through HUAWEI/APPLE Dongle, press Ctrl + u on the dev screen, it cannot boot from USB. We found the SS hub cannot be enumerated. So disable xHCI compliance mode. BRANCH=octopus BUG=b:155347573 TEST=Confirm successful boot from USB Change-Id: Iea4a3df156da0627336f7d6c1e03837b6cf0e7f2 Signed-off-by: tong.lin <tong.lin@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40905 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12trogdor: Add support for rev1Julius Werner
This patch implements the pin changes needed for Trogdor rev1. Unfortunately, coreboot has to get the EC and TPM SPI busses compiled into Kconfig, so we cannot really build a single image that runs on both revisions. Introduce a Kconfig to handle this instead. Change-Id: I2e48dc4565682c12089b6cf92c29f4cef4d61bb8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11trogdor: Latch GPIO interrupt supportrbokka
Required for TPM IRQ. Change-Id: I8198213cf2808be5291620892185b1e534263e3f Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38714 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11trogdor: mainboard reference all QUPv3 FW driversT Michael Turney
Change-Id: I8ff5dd63fac28ffa558aec71e79a6de87d7885e0 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37306 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Replace BSD-3-Clause and ISC headers with SPDX headersPatrick Georgi
Commands used: perl -i -p0e 's|\/\*[*\s]*Permission[*\s]*to[*\s]*use,[*\s]*copy,[*\s]*modify,[*\s]*and.or[*\s]*distribute[*\s]*this[*\s]*software[*\s]*for[*\s]*any[*\s]*purpose[*\s]*with[*\s]*or[*\s]*without[*\s]*fee[*\s]*is[*\s]*hereby[*\s]*granted,[*\s]*provided[*\s]*that[*\s]*the[*\s]*above[*\s]*copyright[*\s]*notice[*\s]*and[*\s]*this[*\s]*permission[*\s]*notice[*\s]*appear[*\s]*in[*\s]*all[*\s]*copies.[*\s]*THE[*\s]*SOFTWARE[*\s]*IS[*\s]*PROVIDED[*\s]*.*AS[*\s]*IS.*[*\s]*AND[*\s]*THE[*\s]*AUTHOR[*\s]*DISCLAIMS[*\s]*ALL[*\s]*WARRANTIES[*\s]*WITH[*\s]*REGARD[*\s]*TO[*\s]*THIS[*\s]*SOFTWARE[*\s]*INCLUDING[*\s]*ALL[*\s]*IMPLIED[*\s]*WARRANTIES[*\s]*OF[*\s]*MERCHANTABILITY[*\s]*AND[*\s]*FITNESS.[*\s]*IN[*\s]*NO[*\s]*EVENT[*\s]*SHALL[*\s]*THE[*\s]*AUTHOR[*\s]*BE[*\s]*LIABLE[*\s]*FOR[*\s]*ANY[*\s]*SPECIAL,[*\s]*DIRECT,[*\s]*INDIRECT,[*\s]*OR[*\s]*CONSEQUENTIAL[*\s]*DAMAGES[*\s]*OR[*\s]*ANY[*\s]*DAMAGES[*\s]*WHATSOEVER[*\s]*RESULTING[*\s]*FROM[*\s]*LOSS[*\s]*OF[*\s]*USE,[*\s]*DATA[*\s]*OR[*\s]*PROFITS,[*\s]*WHETHER[*\s]*IN[*\s]*AN[*\s]*ACTION[*\s]*OF[*\s]*CONTRACT,[*\s]*NEGLIGENCE[*\s]*OR[*\s]*OTHER[*\s]*TORTIOUS[*\s]*ACTION,[*\s]*ARISING[*\s]*OUT[*\s]*OF[*\s]*OR[*\s]*IN[*\s]*CONNECTION[*\s]*WITH[*\s]*THE[*\s]*USE[*\s]*OR[*\s]*PERFORMANCE[*\s]*OF[*\s]*THIS[*\s]*SOFTWARE.[*\s]*\*\/|/* SPDX-License-Identifier: ISC */|s' $(cat filelist) perl -i -p0e 's|(\#\#*)\s*Permission[\#\s]*to[\#\s]*use,[\#\s]*copy,[\#\s]*modify,[\#\s]*and.or[\#\s]*distribute[\#\s]*this[\#\s]*software[\#\s]*for[\#\s]*any[\#\s]*purpose[\#\s]*with[\#\s]*or[\#\s]*without[\#\s]*fee[\#\s]*is[\#\s]*hereby[\#\s]*granted,[\#\s]*provided[\#\s]*that[\#\s]*the[\#\s]*above[\#\s]*copyright[\#\s]*notice[\#\s]*and[\#\s]*this[\#\s]*permission[\#\s]*notice[\#\s]*appear[\#\s]*in[\#\s]*all[\#\s]*copies.[\#\s]*THE[\#\s]*SOFTWARE[\#\s]*IS[\#\s]*PROVIDED[\#\s]*.*AS[\#\s]*IS.*[\#\s]*AND[\#\s]*THE[\#\s]*AUTHOR[\#\s]*DISCLAIMS[\#\s]*ALL[\#\s]*WARRANTIES[\#\s]*WITH[\#\s]*REGARD[\#\s]*TO[\#\s]*THIS[\#\s]*SOFTWARE[\#\s]*INCLUDING[\#\s]*ALL[\#\s]*IMPLIED[\#\s]*WARRANTIES[\#\s]*OF[\#\s]*MERCHANTABILITY[\#\s]*AND[\#\s]*FITNESS.[\#\s]*IN[\#\s]*NO[\#\s]*EVENT[\#\s]*SHALL[\#\s]*THE[\#\s]*AUTHOR[\#\s]*BE[\#\s]*LIABLE[\#\s]*FOR[\#\s]*ANY[\#\s]*SPECIAL,[\#\s]*DIRECT,[\#\s]*INDIRECT,[\#\s]*OR[\#\s]*CONSEQUENTIAL[\#\s]*DAMAGES[\#\s]*OR[\#\s]*ANY[\#\s]*DAMAGES[\#\s]*WHATSOEVER[\#\s]*RESULTING[\#\s]*FROM[\#\s]*LOSS[\#\s]*OF[\#\s]*USE,[\#\s]*DATA[\#\s]*OR[\#\s]*PROFITS,[\#\s]*WHETHER[\#\s]*IN[\#\s]*AN[\#\s]*ACTION[\#\s]*OF[\#\s]*CONTRACT,[\#\s]*NEGLIGENCE[\#\s]*OR[\#\s]*OTHER[\#\s]*TORTIOUS[\#\s]*ACTION,[\#\s]*ARISING[\#\s]*OUT[\#\s]*OF[\#\s]*OR[\#\s]*IN[\#\s]*CONNECTION[\#\s]*WITH[\#\s]*THE[\#\s]*USE[\#\s]*OR[\#\s]*PERFORMANCE[\#\s]*OF[\#\s]*THIS[\#\s]*SOFTWARE.\s(\#* *\n)*|\1 SPDX-License-Identifier: ISC\n\n|s' $(cat filelist) perl -i -p0e 's|\/\*[*\s]*Redistribution[*\s]*and[*\s]*use[*\s]*in[*\s]*source[*\s]*and[*\s]*binary[*\s]*forms,[*\s]*with[*\s]*or[*\s]*without[*\s]*modification,[*\s]*are[*\s]*permitted[*\s]*provided[*\s]*that[*\s]*the[*\s]*following[*\s]*conditions[*\s]*are[*\s]*met:[*\s]*[1. ]*Redistributions[*\s]*of[*\s]*source[*\s]*code[*\s]*must[*\s]*retain[*\s]*the[*\s]*above[*\s]*copyright[*\s]*notice,[*\s]*this[*\s]*list[*\s]*of[*\s]*conditions[*\s]*and[*\s]*the[*\s]*following[*\s]*disclaimer.[*\s]*[*\s]*[2. ]*Redistributions[*\s]*in[*\s]*binary[*\s]*form[*\s]*must[*\s]*reproduce[*\s]*the[*\s]*above[*\s]*copyright[*\s]*notice,[*\s]*this[*\s]*list[*\s]*of[*\s]*conditions[*\s]*and[*\s]*the[*\s]*following[*\s]*disclaimer[*\s]*in[*\s]*the[*\s]*documentation[*\s]*and.or[*\s]*other[*\s]*materials[*\s]*provided[*\s]*with[*\s]*the[*\s]*distribution.[*\s]*[3. ]*.*used[*\s]*to[*\s]*endorse[*\s]*or[*\s]*promote[*\s]*products[*\s]*derived[*\s]*from[*\s]*this[*\s]*software[*\s]*without[*\s]*specific[*\s]*prior[*\s]*written[*\s]*permission.[*\s]*THIS[*\s]*SOFTWARE[*\s]*IS[*\s]*PROVIDED.*AS[*\s]*IS.*[*\s]*AND[*\s]*ANY[*\s]*EXPRESS[*\s]*OR[*\s]*IMPLIED[*\s]*WARRANTIES,[*\s]*INCLUDING,[*\s]*BUT[*\s]*NOT[*\s]*LIMITED[*\s]*TO,[*\s]*THE[*\s]*IMPLIED[*\s]*WARRANTIES[*\s]*OF[*\s]*MERCHANTABILITY.*FITNESS[*\s]*FOR[*\s]*A[*\s]*PARTICULAR[*\s]*PURPOSE.*ARE[*\s]*DISCLAIMED.[*\s]*IN[*\s]*NO[*\s]*EVENT[*\s]*SHALL.*LIABLE[*\s]*FOR[*\s]*ANY[*\s]*DIRECT,[*\s]*INDIRECT,[*\s]*INCIDENTAL,[*\s]*SPECIAL,[*\s]*EXEMPLARY,[*\s]*OR[*\s]*CONSEQUENTIAL[*\s]*DAMAGES[*\s]*.INCLUDING,[*\s]*BUT[*\s]*NOT[*\s]*LIMITED[*\s]*TO,[*\s]*PROCUREMENT[*\s]*OF[*\s]*SUBSTITUTE[*\s]*GOODS[*\s]*OR[*\s]*SERVICES;[*\s]*LOSS[*\s]*OF[*\s]*USE,[*\s]*DATA,[*\s]*OR[*\s]*PROFITS;[*\s]*OR[*\s]*BUSINESS[*\s]*INTERRUPTION.[*\s]*HOWEVER[*\s]*CAUSED[*\s]*AND[*\s]*ON[*\s]*ANY[*\s]*THEORY[*\s]*OF[*\s]*LIABILITY,[*\s]*WHETHER[*\s]*IN[*\s]*CONTRACT,[*\s]*STRICT[*\s]*LIABILITY,[*\s]*OR[*\s]*TORT[*\s]*.INCLUDING[*\s]*NEGLIGENCE[*\s]*OR[*\s]*OTHERWISE.[*\s]*ARISING[*\s]*IN[*\s]*ANY[*\s]*WAY[*\s]*OUT[*\s]*OF[*\s]*THE[*\s]*USE[*\s]*OF[*\s]*THIS[*\s]*SOFTWARE,[*\s]*EVEN[*\s]*IF[*\s]*ADVISED[*\s]*OF[*\s]*THE[*\s]*POSSIBILITY[*\s]*OF[*\s]*SUCH[*\s]*DAMAGE.[*\s]*\*\/|/* SPDX-License-Identifier: BSD-3-Clause */|s' $(cat filelist) $1 perl -i -p0e 's|(\#\#*) *Redistribution[\#\s]*and[\#\s]*use[\#\s]*in[\#\s]*source[\#\s]*and[\#\s]*binary[\#\s]*forms,[\#\s]*with[\#\s]*or[\#\s]*without[\#\s]*modification,[\#\s]*are[\#\s]*permitted[\#\s]*provided[\#\s]*that[\#\s]*the[\#\s]*following[\#\s]*conditions[\#\s]*are[\#\s]*met:[\#\s]*[*1. ]*Redistributions[\#\s]*of[\#\s]*source[\#\s]*code[\#\s]*must[\#\s]*retain[\#\s]*the[\#\s]*above[\#\s]*copyright[\#\s]*notice,[\#\s]*this[\#\s]*list[\#\s]*of[\#\s]*conditions[\#\s]*and[\#\s]*the[\#\s]*following[\#\s]*disclaimer.[\#\s]*[*2. ]*Redistributions[\#\s]*in[\#\s]*binary[\#\s]*form[\#\s]*must[\#\s]*reproduce[\#\s]*the[\#\s]*above[\#\s]*copyright[\#\s]*notice,[\#\s]*this[\#\s]*list[\#\s]*of[\#\s]*conditions[\#\s]*and[\#\s]*the[\#\s]*following[\#\s]*disclaimer[\#\s]*in[\#\s]*the[\#\s]*documentation[\#\s]*and.or[\#\s]*other[\#\s]*materials[\#\s]*provided[\#\s]*with[\#\s]*the[\#\s]*distribution.[\#\s]*[\#\s]*[*3. ]*.*used[\#\s]*to[\#\s]*endorse[\#\s]*or[\#\s]*promote[\#\s]*products[\#\s]*derived[\#\s]*from[\#\s]*this[\#\s]*software[\#\s]*without[\#\s]*specific[\#\s]*prior[\#\s]*written[\#\s]*permission.[\#\s]*THIS[\#\s]*SOFTWARE[\#\s]*IS[\#\s]*PROVIDED.*AS[\#\s]*IS.*[\#\s]*AND[\#\s]*ANY[\#\s]*EXPRESS[\#\s]*OR[\#\s]*IMPLIED[\#\s]*WARRANTIES,[\#\s]*INCLUDING,[\#\s]*BUT[\#\s]*NOT[\#\s]*LIMITED[\#\s]*TO,[\#\s]*THE[\#\s]*IMPLIED[\#\s]*WARRANTIES[\#\s]*OF[\#\s]*MERCHANTABILITY.*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.*ARE[\#\s]*DISCLAIMED.[\#\s]*IN[\#\s]*NO[\#\s]*EVENT[\#\s]*SHALL.*LIABLE[\#\s]*FOR[\#\s]*ANY[\#\s]*DIRECT,[\#\s]*INDIRECT,[\#\s]*INCIDENTAL,[\#\s]*SPECIAL,[\#\s]*EXEMPLARY,[\#\s]*OR[\#\s]*CONSEQUENTIAL[\#\s]*DAMAGES[\#\s]*.INCLUDING,[\#\s]*BUT[\#\s]*NOT[\#\s]*LIMITED[\#\s]*TO,[\#\s]*PROCUREMENT[\#\s]*OF[\#\s]*SUBSTITUTE[\#\s]*GOODS[\#\s]*OR[\#\s]*SERVICES;[\#\s]*LOSS[\#\s]*OF[\#\s]*USE,[\#\s]*DATA,[\#\s]*OR[\#\s]*PROFITS;[\#\s]*OR[\#\s]*BUSINESS[\#\s]*INTERRUPTION.[\#\s]*HOWEVER[\#\s]*CAUSED[\#\s]*AND[\#\s]*ON[\#\s]*ANY[\#\s]*THEORY[\#\s]*OF[\#\s]*LIABILITY,[\#\s]*WHETHER[\#\s]*IN[\#\s]*CONTRACT,[\#\s]*STRICT[\#\s]*LIABILITY,[\#\s]*OR[\#\s]*TORT[\#\s]*.INCLUDING[\#\s]*NEGLIGENCE[\#\s]*OR[\#\s]*OTHERWISE.[\#\s]*ARISING[\#\s]*IN[\#\s]*ANY[\#\s]*WAY[\#\s]*OUT[\#\s]*OF[\#\s]*THE[\#\s]*USE[\#\s]*OF[\#\s]*THIS[\#\s]*SOFTWARE,[\#\s]*EVEN[\#\s]*IF[\#\s]*ADVISED[\#\s]*OF[\#\s]*THE[\#\s]*POSSIBILITY[\#\s]*OF[\#\s]*SUCH[\#\s]*DAMAGE.\s(\#* *\n)*|\1 SPDX-License-Identifier: BSD-3-Clause\n\n|s' $(cat filelist) Change-Id: I7ff9c503a2efe1017a4666baf0b1a758a04f5634 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11mb/google/cyan/*: fixup GPIOsMatt DeVillier
Commit 73b723d [google/cyan: Switch Touchpad and Touchscreen...] in additon to changing the touchpad/touchscreen interrupts from edge to level triggered, also marked them as maskable. This was partially reverted in a86bbea0 [google/cyan: set touchscreen GPIO to non_maskable], but did not resolve all of the issues. Additionally, 73b723d also accidentally changed the pad interrupt select from L3 to L1 for all touchscreen GPIOs. Clean up this mess by setting all touchpad/touchscreen GPIOs back to maskable, and set the pad level to L3 for all touchscreen GPIOs. Tested on several cyan variants Change-Id: I70e8e2d4ff317c3b9b4108ed6c5bc80e9b0bbc75 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-11mb/google/octopus/variants/dood: Disable XHCI LFPS power managementKenneth Chan
LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] are set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2020-05-11mb/google/kukui: fix screen scrolling on devices using anx7625Paul Ma
anx7625 enables MIPI receiver to check EOTP packet as default. If MIPI_DSI_MODE_EOT_PACKET is not set in flags, soc dsi will not send out EOTP packet and some panel models will display abnormal such as scrolling all the time. BUG=b:144824303 BRANCH=kukui TEST=boot damu board, edp panel with anx7625 as bridge boots up without scrolling. Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Change-Id: Iad651202bde2a40024af8c12153143ada2ce2439 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41161 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11mb/google/kukui: Fix backlight flash white before show logoJitao Shi
Turn backlight off before panel poweron. BUG=b:155107047 TEST=make # board = kukui BRANCH=kukui Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I0f31923bd7c1dfa26d4b1bbd0a230ae400b08ca3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41146 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11mb/google/octopus: Fix default FMDMatt DeVillier
On Apollo Lake/Gemini Lake platforms, FSP requires more than a simple RW_MRC_CACHE; without the RECOVERY and VAR cache regions, FSP-m will fail on s3 resume and trigger a full reset instead. This fixes the default.fmd for octopus to match that used for reef. Test: build/boot google/ampton, verify sleep/resume works under Linux with 5.x kernel. Change-Id: I8565aa93256df7d6e0b359d70e9305f34e5ccb60 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-10mb/google/kahlee: Hold WLAN PCIe reset low at boot for mordinKevin Chiu
gpio70 is assigned to use as WLAN rst in new schematic to fulfill RTK RTL8822CE power sequence: WLAN rst will need to be active at least 50ms after WLAN power on. Also in order to keep the rst low in consistency, override default gpio70 to low. BUG=b:154357210,b:154848243 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I98c8afe42b7f92016f83483acbb3b9ae64b159f7 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40805 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-10mb/google/kahlee: Don't reset the touchpad/screen on bootMartin Roth
touchpad & touchscreen power enable gets reset during resume causing unintended wake interrupts, causing dark resume failures. This prevents the board from being shut down after it's been suspended for a long period of time and can end up draining the battery. BUG=b:153173717 TEST=Build only - Needs to be tested by ODMs. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: If403da8853e59eaaf589062c9bd6f10deb626998 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
2020-05-10src/mainboard: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS
Change-Id: I64d9468682a4aae3084b17b8724d035f17d01dff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
Used commands: perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-08mb/google/reef: add G2 TS support for snappyKevin Chiu
Add G2 GTCH7503 HID TS support spec from G2: G7500 / Ver.1.2 (3, April, 2018) BUG=b:155827595 BRANCH=master TEST=emerge-snappy coreboot Change-Id: I151bf141148f4f00b3dadd9c44ab3a6b7731cde1 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41090 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
That makes it easier to identify "license only" headers (because they are now license only) Script line used for that: perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist... Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-06soc/intel/tgl: Synchronize GPIO ASL table with Linux kernelShaunak Saha
Kernel pinctrl driver changed for Tiger Lake and went to old scheme. Kernel patch: https://chromium-review.googlesource.com/c/chromiumos/ third_party/kernel/+/2116670 BUG=b:151683980 BRANCH=none TEST=Build and boot tgl board. In /sys/kernel/debug/pinctrl verify INTC34C5:00 listing all the pins. Cq-Depend:chromium:2116670 Change-Id: I9f1d399ff7380125ad5b935f9590a7d9cc442b04 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39801 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06mb/google/dedede: Enable PMC, P2SB and PCH SPI in the devicetreeKarthikeyan Ramasubramanian
BUG=None TEST=Build and boot the mainboard. Change-Id: I1aae4adf1c13fd4ff58aa38a877f34e142f320f1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41037 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04soc/intel/skl: always enable SataPwrOptEnableMichael Niewöhner
For unknown reasons FSP skips a whole bunch of SIR (SATA Initialization Registers) when SataPwrOptEnable=0, which currently is the default in coreboot and FSP. Even if FSP's default was 1, coreboot would reset it. This can lead to all sorts of problems and errors, for example: - links get lost - only 1.5 or 3 Gbps instead of 6 Gbps - "unaligned write" errors in Linux - ... At least on two boards (supermicro/x11-lga1151-series/x11ssm-f and purism/librem13v2) SATA is not working correctly and showing such symptoms. To let FSP correctly initialize the SATA controller, enable the option SataPwrOptEnable statically. There is no valid reason to disable it, which might break SATA, anyway. Currently, there are no reported issues on CML and CNL, so a change there could not be tested reliably. SKL/KBL was tested successfully without any noticable downsides. Thus, only SKL gets changed for now. Change-Id: I8531ba9743453a3118b389565517eb769b5e7929 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40877 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04mb/google/dedede: Read DRAM part number from CBIMarco Chen
The index of MEM_STRAPS will be migrated from per DRAM part number to per DRAM characteristic therefore one index mapped to a single SPD binary can represent to multiple DRAM part numbers as long as their characteristic is the same for DRAM controller to support. In this case, the real DRAM part number would be provisioned in the CBI instead of SPD in the factory flow. As a result, we need to extract DRAM part number from CBI. BUG=b:152019429 BRANCH=None TEST=1. provision dram_part_num field of CBI 2. check DRAM part number is correct in SMBIOS for memory device Change-Id: I40780a35e04efb279591e9db179cb86b5e907c0d Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-02mb/google/reef: Add and use VBTMatt DeVillier
Add VBT file, and override use via Kconfig since all Reef variants use the same VBT file. VBT extracted from firmware in ChromeOS recovery image. Test: built/boot google/reef w/FSP display init Change-Id: I31156ec7371c0443719fdd9ddac6ed4960c83767 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-02mainboard/google/kahlee: Add hook for early wlan rst gpio initKevin Chiu
Base on the grunt board schematic, gpio70 is an alternative way for wlan rst. Add hook for variants to override default state. BUG=b:154357210,b:154848243 BRANCH=master TEST=emerge-grunt coreboot Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Change-Id: Ic3f1c016357dd5090e6adedf96e7593abff29a0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/40944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-05-02payloads/seabios: Add Hardware IRQ KconfigMatt DeVillier
Certain boards require SeaBIOS' HARDWARE_IRQ option to be deselected in order for the platform to boot. Add a Kconfig to allow selection of HARDWARE_IRQ enablement, and write to SeaBIOS' .config file in cases where it needs to be disabled. Deselect the option for google/rambi variants so they boot with boards defaults. Test: build/boot google/clapper, verify board boots vs hanging at boot menu prompt. Change-Id: I23e9b30d2d1042c86bd10f134d6fe361edaf8cb2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-02mb/google/reef: add default non-ChromeOS FMAPMatt DeVillier
Add a FMAP which supports SMMSTORE and non-ChromeOS payloads, since Apollo Lake-based devices like Reef cannot use an automatically-generated FMAP due to strict layout requirements. Change-Id: If570f92f4f81c0e29777c87756fc5e45af549064 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01mb/google/dedede: Fix crossystem wpsw_cur errorSubrata Banik
Add GPIO_PCH_WP (GPP_C11) to associate GPP_PCH_WP with community zero. TEST=Build coreboot, flash, boot to and log into kernel, execute "wp enable" in console, execute "crossystem" at kernel prompt and verify that "wpsw_cur" shows as being "1", Execute "wp disable" in console, execute "crossystem" at kernel prompt and verify "wpsw_cur" is 0. Change-Id: Ie4ae1365a7611b8be3e795798c171e3f7ea9e417 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40744 Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>