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Both touchpads supported by zork use level-triggered wakeup signal.
BRANCH=zork
BUG=b:172846122,b:182911201
TEST=1. cros build-ap -b zork
2. both Synaptics and ELAN touchpads work fine on Vilboz
3. Wakeup source is correctly reported on Vilboz
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: Icc2b5ad3bd434c9759a0fdfc121aa3c94f46630e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52367
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on the datasheet provided by ELAN, the /INT pin is "low active"
and "indicates touchpad likes to send data to system(host) when low".
The signal is level-triggered.
BRANCH=zork
BUG=b:172846122
TEST=cros build-ap -b zork
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I1f2182aaf483932304591ab14592f35214ea6efd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52366
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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platform_descriptors.h is unrelated to the contents of baseboard/gpio.h
where it was included, so move the includes to the files where it is
actually needed.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I94e59b5aac2df834d956106ac953eebfc5cf6921
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52357
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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amdblocks/gpio_defs.h provides the definitions of GEVENT_x.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I65d398667e6777de6f1fa4e027cf1c75a3e235c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52356
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The new discovery from Google & AMD, the value currently used
STAPM Time Constant of 1640 is reducing real PPT TSP from the
target 4.8W to 4.68W.
Furthermore, when using the "default" STAPM Time Constant of 1400,
the actual real PPT TSP becomes 4.89W.
Operating at this default settings therefore uses a higher real PPT TSP,
which results in a significant performance improvement.
BUG=b:175364713,b:184902568
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test => pass
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I9cf4d51f42fe250340bcb642db07796c9a480c34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52312
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The new discovery from Google & AMD, the value currently used
STAPM Time Constant of 1640 is reducing real PPT TSP from the
target 4.8W to 4.68W.
Furthermore, when using the "default" STAPM Time Constant of 1400,
the actual real PPT TSP becomes 4.89W.
Operating at this default settings therefore uses a higher real PPT TSP,
which results in a significant performance improvement.
BUG=b:184902568
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test => pass
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I102c1c5f8215a6c5f7a4451f5731167c32e27c90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52313
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To update the sx9324 registers after RF team fine-tuned the parameters.
BUG=b:172397658
BRANCH=firmware-zork-13434.B
TEST=build coreboot and verify the sx9324 function
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ief85bc61952144a1d7a151100d89938517078ab4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51936
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When GPIO_2 was configured as PAD_NF with the WAKE_L function selected
the GPIO_2 override in soc_gpio_hook called soc_route_sci that wrote the
corresponding SCI mapping register, but didn't set up the SCI level and
trigger type, so that couldn't have worked on most of the boards. The
only boards where I think this was actually tested are the google/zork
ones and they configured GPIO_2 as PAD_SCI where the GPIO mux setting is
GPIO mode instead of the WAKE_L mode, but at least the SCI was
configured correctly. The new PAD_NF_SCI macro can configure both the
right GPIO mux setting and set up the SCI configuration correctly, so
use this new macro for the GPIO_2 pin. For test purposes I also added
the corresponding GPIO_2 configuration to amd/mandolin to see if the
affected registers end up having the expected value using the HDT
debugger to look at the registers, but didn't test the wake-up
functionality, since S3 resume isn't working on amd/mandolin yet.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: Ic069e46b759fb6746645faccd254263c49a892d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51756
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update the ACPI name from AMDP1015 to 1002105 based on b/177971830#180.
AMDI1015 -> AMD platform with RT1015
10021015 -> AMD platform with RT1015p
Reference:
https://www.spinics.net/lists/alsa-devel/msg124694.html
BUG=b:177971830
BRANCH=firmware-zork-13434.B
TEST=emerge-zork coreboot chromeos-bootimage, then verify with ALC1015 AMP
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Id8f378ad6f3328d7db949ecdb609a2f16acd3884
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52127
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Micron DDR4 memory part MT40A1G16RC-062E-B 16Gb
index was generated by gen_part_id
BUG=b:184024142
BRANCH=zork
TEST=emerge-zork coreboot
Change-Id: I890a2da38c8cd1963e9ee7c5df9410b2b2538e9f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Loading wifi_sar-vilboz-2.hex for vilboz LTE sku.
Loading wifi_sar-vilboz-3.hex for vilboz360 LTE sku.
BUG=b:183902165, b:176211194, b:183913210
BRANCH=firmware-zork-13434.B
TEST=Build coreboot and load the wifi sar table by fw_config
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I37a40456970e3f1dc8b2eed26aa23e3d75748222
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Use board id to switch acp_i2s_use_external_48mhz_osc enable.
BUG=b:181720406
BRANCH=firmware-zork-13434.B
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I085c39accd82bf72e4ebbc0394382ed4a7d4e901
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Move the eDP phy overridden to variant for WWAN SKU.
BUG=b:171269338
BRANCH=firmware-zork-13434.B
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I0400e8f78b152f260c632fba3cfa43aeca2f6776
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Move the parts of romstage.c that populate the UPD-M data structure to
the newly created fsp_m_params.c file. Since
platform_fsp_memory_init_params_cb gets called from the FSP driver and
not directly from car_stage_entry the two code parts in romstage.c
weren't directly interacting. Since soc/romstage.h only contains the
mainboard_updm_update function prototype, rename it to soc/fsp.h. This
patch also removes a few unused includes.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I52c21f13520dbdfab37587d17b3a8a3b1a780f36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Original Stamp_boost parameter will cause boost time over 2500sec(3960sec)
To pass balance performance and skin temperature test, decrease stamp_boost:
2500 -> 1640
BUG=b:182753072
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test
Change-Id: I43c104ef912aafecadf9497f9ea20c8478c0e920
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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update telemetry to improve the performance.
BUG=b:182753072
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run AMD SDLE stardust test => pass
Change-Id: I6e4d0c6fcd740d82edf073fb307aa6a6b09ec78a
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51790
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable ALC1015 driver for audio support in vilboz
BUG=b:177971830
BRANCH=firmware-zork-13434.B
TEST=emerge-zork coreboot chromeos-bootimage, then verify with ALC1015 AMP
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: If0abfd6570579fe637a7bef31de2f01d58f3bdf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Set default USB2 HS disconnect threshold to maximum to avoid false
disconnects that eventually lock up the xHCI controller
BUG=b:174538960
TEST=suspend_stress_test -c 50 on vilboz and morphius.
Sample set of USB2 HS devices connect and disconnect
successfully
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: Ic921d850a0bdd717a2a7e50e9e6f65e39e0607bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51265
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To append SSFC to top 32 bits of fw_config.
BUG=b:177971830
BRANCH=firmware-zork-13434.B
TEST=Build coreboot and get the value of SSFC.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Iab1596f1cc8fbbf45e6a9269351bf422a43f3583
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51655
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Not all of dalboz variants support the this amp. Thus, move out of baseboard.
BUG=b:182815488
TEST=builds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If708574f5fb18dd3b4f2ef978529a16a40d5dc0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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The logic behind I2C bus initialization, I2C MMIO base address getter
and setter, I2C bus ACPI name resolution are identical for all the AMD
SoCs. Hence moving all the SoC agnotic parts of the driver into the
common driver and just configure the SoC specific parts into individual
I2C drivers.
BUG=None
TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C
peripherals are detected as earlier in Dalboz. Verify some I2C
peripheral functionality like trackpad and touchscreen.
Change-Id: Ic9c99ec769d7d8ad7e1e566fdf42a5206657183d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51509
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to stardust test tracking report to adjust
telemetry setting.
VDD Slope : 30518 -> 30595
VDD Offset: 435 -> 77
SOC Slope : 22965 -> 24063
SOC Offset: 165 -> 105
BUG=b:182399760
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ie7e6af77bdaad6cc964ac206a69ccb854aae869f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Currently, if `get_wifi_sar_cbfs_filename()` returns NULL, then
`get_wifi_sar_limits()` assumes that the default filename is used for
CBFS SAR file. This prevents a board from supporting different models
using the same firmware -- some which require SAR support and some
which don't.
This change updates the logic in `get_wifi_sar_limits()` to return
early if filename is not provided by the mainboard. In order to
maintain the same logic as before, current mainboards are updated to
return WIFI_SAR_CBFS_DEFAULT_FILENAME instead of NULL in default
case.
Change-Id: I68b5bdd213767a3cd81fe41ace66540acd68e26a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51485
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 87a1bd696d47f80101e46132efae8cad8cfe5c7e.
Reason for revert: skin temperature is overheating due to boost time is too long
BUG=b:175364713
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test => pass
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I31db06f4bcb986398e7bd2ac2858ffbedb257e2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Define the 26th bit of the fw_config for the regular touchpad
and numpad touchpad selection.
REGULAR_TOUCHPAD: 1
NUMPAD_TOUCHPAD: 0
BUG=b:174964012
BRANCH=zork
TEST=build pass
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ie2055d6bb45a64bc0e59209cecc0f8a31c0f3718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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The VGA BIOS for AMD Padmelon and Google Zork are stored in `amd_blobs`.
Do not force inclusion of VGA BIOS when `USE_AMD_BLOBS` is not enabled.
Change-Id: I206e8fadc14ec0d9b162dc4d72813fdd3d43958b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add ".data_hold_time_ns" to follow I2C specification.
The adjusted result aobut 0.315us(more than 0.3us)
BUG=b:181091107
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Id92fadcb54b9722709e32ced1f0be001b8c97975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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BUG=b:182269526
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I351fb4fc493bb92b31e2c8bc946dfb048045335c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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To define Mainboard Type config, use the fw_config bit[26].
Check MB Type to modify SDLE settings for different VCORE IC.
BUG=b:177193131
BRANCH=zork
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Add the UPD updating hook in early stage for customization.
BUG=b:117719313
BRANCH=zork
TEST=build,check the hook function been executed.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4954a438a51b29b086015624127e651fd06f971b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51181
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This file is common for all the AMD platforms.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I10ee600b4bcd7aaff39bfab075eb4dbc9096b435
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51299
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update telemetry settings for vilboz.
VDD Slope : 26939 -> 27225
VDD Offset: 125 -> 187
SOC Slope : 20001 -> 26559
SOC Offset: 168 -> 89
BUG=b:177162553
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Iaf7c5083c4c5affec5ae0b5583efb5237e10d0ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: chris wang <Chris.Wang@amd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Loading wifi_sar-vilboz-1.hex for vilboz360 LTE sku for the present.
BUG=b:177684735, b:176168400
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are
in CBFS and loaded by iwlwifi driver.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I477b55d64fd9d33d753b10b2de443041a12d13e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Modify I2C3 setting to follow I2C specification (lower than 400kHz).
Original setting:
.rise_time_ns = 184
.fall_time_ns = 42
Change to:
.rise_time_ns = 110
.fall_time_ns = 34
BUG=b:181091107
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ibdbb9a7dde524bdbde4789ee7ea005646080d97a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Ie3870bc666acaea316f00b205de512cf790e720c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Stamp_boost 1640 parameter is too short to keep APU performance.
Restore parameter to 2500 then APU could have longer boost time (~3xxx sec)
BUG=b:175364713
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test => pass
Change-Id: Ie08394d0b1a693f71336cb4cb6ce9528dfdce14b
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Let's not have 7 boards of all use a different name for
the .enable_dev function in mainboard chip_operations.
Change-Id: I07f3569e6af85f4f1635595125fe2881ab9ddd43
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The semantics of pirq_setup() from previous platforms was to
only setup the global pointers for PIC and APIC tables, not
to create or modify the tables themselves.
Change-Id: Iaa7c31eed21432dc2b3fe6b32803bd2658fd5e2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Recommendation from SOC to config IQ=8 for U3 port0,
vboost for all U3 ports for passing ESD pin test.
BUG=b:173476380
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run U3 SI/ESD pin test => pass
Change-Id: I0e6414f686a995536a0fd8aa0f6f70e5a36718a3
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50992
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust H1 I2C CLK:
404kHz -> 391 kHz
BUG=b:179753353
BRANCH=zork
TEST=1. emerge-zork coreboot chromeos-bootimage
2. power on proto board successfully
3. measure i2c freq by scope is close to 400kHz
Change-Id: Iedd47dd6fc4f7ac7f0aac480d63ddbdf85a84ec2
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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1. GPIO_4 to NC
BUG=b:179333669
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I4342b2beb7fc755bee47ee4fad0023d7a6592c4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50277
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Sometimes the USB device will be lost after DUT resume.
Adjust USB phy settings for all USB ports to fix the failed symptom.
BUG=b:174538960
BRANCH=zork
TEST=USB devices stay connected after running suspend test
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I25bca968bb4a740161b36e2082d1e500ae648712
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50020
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'
Change-Id: I3ba39077014c50c2dfb9fddf78813f1058c45cc1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I6e0f33172fbcecebddfccdf64c22685636a23936
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50524
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is ACPI specific config that applies to all the AMD SoCs. Stoney
doesn't currently use this, but we can add that functionality later.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0be7d917d7c5ba71347aa646822a883e2cf55743
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50557
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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configure IRQs as level triggered to prevent TP lost.
BUG=None
BRANCH=zork
TEST=1. emerge-zork coreboot chromeos-bootimage
2. power on, suspend DUT to check TP is functional
Change-Id: I81ffa889fbdfb01bf3057a8258fb4dd4ad7e88d5
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50420
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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EDGE IRQ from TS might be invalid to HOST, configure IRQs
as level triggered to prevent TS lost.
BUG=b:179594439
BRANCH=zork
TEST=1. emerge-zork coreboot chromeos-bootimage
2. power on, suspend DUT to check TS is functional
Change-Id: Ibbbc73b37932ba1359ffe6f572a15564bb341025
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50416
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Modify GPIO_140 delay time and add "disable_gpio_export_in_crs"
to meet touchscreen controller power on sequence.
BUG=b:174442484
BRANCH=master
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I36a7055b7be0963479f8a0f4dc49c92bc8fbdc9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50228
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since Jelboz support number pad,
due to one single coreboot for both Jelboz and Shuboz,
modify "overridetree.cb" setting to number pad support for Jelboz.
BUG=b:174964012
BRANCH=master
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ie0219419834b34b6eac589f28d3604f5f1b65679
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Fixes: b3c41329fd (mb/google/zork: Add Picasso based Zork mainboard and variants)
Change-Id: I68cd5ffc3117e714919bbce56e9af4c9982b3d54
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Recommendation from SOC to config IQ=8 for U3 port0,
vboost for all U3 ports for passing ESD pin test.
BUG=b:175192931
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run U3 SI/ESD pin test => pass
Change-Id: I42a94e03fb6f8230d4356d16b8e0d2164bc61e3f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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update telemetry to improve the performance.
BUG=b:168585079
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run AMD stardust test => pass
Change-Id: Ie0c941815d062d9af01858faf2121bc69f23ab44
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Icb3108a281dfb3f21248a7065821b8237143be1a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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Adjust H1 I2C CLK:
404kHz -> 391 kHz
BUG=b:178656936
BRANCH=master
TEST=1. emerge-zork coreboot chromeos-bootimage
2. power on proto board successfully
3. measure i2c freq by scope is close to 400kHz
Change-Id: I9067db9fc7a4d6aa2ce33b86ba6a611dfd5d7838
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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add UPD for RV2 USB3 phy setting adjust.
Note: it only for RV2 silicon and not available for RV/PCO.
Usb 3.1 PHY Parameters:
1. RX_EQ_DELTA_IQ_OVRD_VAL
-Override value for rx_eq_delta_iq. Range 0-0xF
2. RX_EQ_DELTA_IQ_OVRD_EN
-Enable override value for rx_eq_delta_iq. Range 0-0x1
3. Override value for rx_vref_ctrl. Range 0 - 0x1F
4. Enable override value for rx_vref_ctrl. Range 0 - 0x1
5. Override value for tx_vboost_lvl: 0 - 0x7.
6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
7. Override value for rx_vref_ctrl. Range 0 - 0x1F
8. Enable override value for rx_vref_ctrl. Range 0 - 0x1
9. Override value for tx_vboost_lvl: 0 - 0x7.
10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
BUG=b:175192931
TEST=Build/verify the valule will been apply on dirinboz
Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Improve performance and meet stardust test requirement.
PcdSet32(PcdTelemetry_VddcrVddfull_Scale_Current,102586)
PcdSet32(PcdTelemetry_VddcrVddOffset, 0)
PcdSet32(PcdTelemetry_VddcrSocfull_Scale_Current,24674)
PcdSet32(PcdTelemetry_VddcrSocOffset, 0)
BUG=b:176156237
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I81dbfafffe7625c3d0d80419466240508f9b041b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50256
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable this driver along with power saving.
BUG=b:177955523
BRANCH=zork
TEST=boot and see this message:
BayHub LV2: Power-saving enabled 110102
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Icd87ea585dfaa2185abf1f7bf803e9c9a6e63972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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Change-Id: I0d2ab4144970184f46e1d0e7a2464e94fa38aa63
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
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Change-Id: Idc11f1e131df2e01864fedac864bda5e11f2d17b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Clean up the unused UPD and re-sort the table, and also update
the new phy parameter in the soc code and overridetree.
remove:
EDpPhySel
EDpVersion
rename:
DpPhyOverride -> edp_phy_override
EDpPhySel -> edp_physel
DpVsPemphLevel -> edp_dp_vs_pemph_level
MarginDeemPh -> edp_margin_deemph
Deemph6db4 -> edp_deemph_6db_4
BoostAdj -> edp_boost_adj
eDP phy setting:
DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00(0.4v 0db swing 0,pre-emphasis 0)
COMMON_MAR_DEEMPH_NOM = 0x004b
COMMON_SELDEEMPH60 = 0x0
CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80
BUG=b:171269338
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Added device hid info to the MST RTD2141b device on
trembyle.
BRANCH=zork
BUG=b:147402710
TEST=Build and flash BIOS image, see 10EC2141 appears
under /sys/bus/i2c/devices
Signed-off-by: Shiyu Sun <sshiyu@chromium.org>
Change-Id: I97a67f9dbc31cd788d579252d7d355b24d97ca30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
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Change-Id: I4356a8bda71e84afe8c348d366479c5006bf2459
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49796
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Objects that are created with acpigen need to be declared
with External () for the generation of dsdt.asl to pass
iasl without errors.
There are some objects that are common to all platforms,
and some that should be declared only conditionally.
Having a top-level ASL helps to achieve this.
Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If0bc153cd3a3391b1607848436f0ab5fcd54ce7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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set pwron_varybl_to_blon to 0x5, which means fw will delay 20ms between backlight
on and vary backlight.
BUG=b:171269338
BRANCH=zork
TEST=Build; Verify the UPD was passed to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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needs to adjust the eDP phy setting to fix the eDP noise for WWAN.
DP_VS_LEVEL0_PREEMPH_LEVEL0, = 0x00 (0.4v 0db) swing 0, pre-emphasis 0)
COMMON_MAR_DEEMPH_NOM = 0x004B
COMMON_SELDEEMPH60 = 0x0
CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80
BUG=b:171269338
BRANCH=none
TEST=Build; Verify the UPD was passed to system integrated table
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ibe720e26d2257e05a989eaa1fd85d542005cf6a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48734
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This conflicts with the MSTH i2c_tunnel.
BUG=b:175146875
BRANCH=zork
TEST=Boot trembyle and inspect ACPI tables.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iac04c7dc361d427f5ebb99644aa70bd0c7dbb918
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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From AMD USB phy specialist recommended that for DB port2 (type-A), port3 (type-C C1)
the most effective corrections for the depressed eye are
tx_rise_tune=0x0
tx_pre_emp_amp_tune=0x3
tx_fsls_tune = 0x3
BUG=b:173476380
BRANCH=zork
TEST=1. emerge-zork coreboot
2. pass USB 2.0 SI eye diagram verification
Change-Id: Ib31c5d55e30b958d3e552e8d0b4a160947444636
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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From AMD USB phy specialist recommended that for DB port2 (type-A), port3 (type-C C1)
the most effective corrections for the depressed eye are:
tx_rise_tune=0x0
tx_pre_emp_amp_tune=0x3
tx_fsls_tune = 0x3
BUG=b:165209698
BRANCH=zork
TEST=1. emerge-zork coreboot
2. pass USB 2.0 SI eye diagram verification
Change-Id: I80afd6bf1257b9a72d0d7651b48d243ebaf5de2f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Change-Id: I306f8cd74af62c0cd30f445d20c47f774f122481
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49247
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The SoC code has in implicit dependency on this option, so select it in
the SoC code instead of the mainboard code.
Change-Id: Iea908c142f4a94a107cf74a31d9f5e29668d4b5b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Dalboz variants do not use an MST hub; remove the i2c tunnel for it.
That bus is actually connected to the battery on these devices, which
should not be exposed to the AP.
BUG=b:175658311
TEST=builds
BRANCH=zork
Change-Id: If1714a5c441bf185efd2517c7c94e57b5f351f5a
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49628
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enhance USB 2.0 M/B C0, DB C1 A1 port:
HS DC Voltage Level(TXVREFTUNE0): 0xe
COMPDISTUNE(COMPDISTUNE0): 0x7
BUG=b:165209698
BRANCH=zork
TEST=emerge-zork coreboot
Change-Id: I371e4295c2ee161096f0a277c0c649bf217269b2
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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1. Modify STAPM time constant 2500 to 1400.
2. Add telemetry setting:
VDD Slope : 30518
VDD Offset: 435
SOC Slope : 22965
SOC Offset: 165
BUG=b:177399751
BRANCH=master
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I251029389c10ee0f17f368b1c00ac666d372fc3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add Hynix DDR4 DRAM H5ANAG6NCJR-XNC, index was generated by gen_part_id
BUG=b:176313722
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Ia1947fa158a1113c4a0b1a0d55f657ddaac43382
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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The fw_config field SPI_SPEED is not used for zork devices.
To define SAR config, use the fw_config bit[23..26].
Then vilboz can loaded different WiFi SAR table for different SKUs.
BUG=b:176858126, b:176751675, b:176538384
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are
in CBFS and loaded by iwlwifi driver.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: Ic9cdcc497bf1a9f5bfed5e6d95040bfa602b0b89
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48732
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The FW config takes 2 bits for USE_FAN[27,28].
So FW_CONFIG_SHIFT_WWAN value should be 29.
BUG=b:174121847
BRANCH=zork
TEST=build vilboz
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ica6d04f9c48aa0800189283608bf57416ac75cf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49236
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that the _PRT generates a GNB IO-APIC routing table we no longer
need to route the PCI interrupts through the FCH IO-APIC. This change
unmaps the IRQs since they are no longer used.
BUG=b:170595019
TEST=Boot with `pci=nomsi amd_iommu=off` and verify /proc/interrupts
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3467934bfcac14311505bec49a12652490554e6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Original Stamp_boost parameter will cause boost time over 2500sec(3960sec)
To pass balance performance and skin temperature test, decrease stamp_boost:
2500 -> 1640
BUG=b:175364713
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test
Change-Id: I44f086af6b5dd552efd2bd1ef4db0d69b652826d
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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1. Add ELAN touchscreen/touchpad to overridetree.cb
2. Follow Dalboz setting to add variant.c
BUG=b:174528384
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ic3193ca7957251841e75a7e5c7a16fc5047919fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48001
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According Goodix GT7375P Programming Guide_Rev.0.6, increase the stop
delay time from 100 ms to 160 ms.
The power sequence is not met with the latest guide_rev.0.6.
BUG=b:176270381
BRANCH=zork
TEST=Confirm the measured waveform complies with Goodix touchscreen spec.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I687ffa2eb13a9ddecb3045c5e1540b94417329ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48907
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This table was wrong. It's also produced by the SoC code now.
BUG=b:170595019
TEST=Verify PCI IRQ: log messages
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I008b6896064672f9d45a8e12f6cfc62c0cc41536
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The EC generates EC_MKBP_EVENT_DP_ALT_MODE_ENTERED when USB-C
connections enter DP alt mode, which should wake the system from S3.
Configure S3 wake events to include MKBP so this actually wakes
the system.
BUG=b:174121852
BRANCH=zork
TEST=Generating DP event on MKBP via EC console wakes morphius
Change-Id: I8100c6253e8e5cae91586c4f2f45d66c15fecc6d
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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INT[E-H] are required because the GNB IO-APIC maps the 32 interrupts
onto the 8 INT[A-H] that feed into the FCH PIC/IO-APIC.
BUG=b:170595019
TEST=Verify ezkinil still boots
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9c6689e212b136f6f3c64152803ed161b2284275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Remove index0 DRAM assignment since it doesn't use in any build.
Add Hynix DDR4 DRAM H5ANAG6NCJR-XNC, index was generated by gen_part_id
BUG=b:175911098
BRANCH=zork
TEST=emerge-zork coreboot
Change-Id: I853a316c266afafeecff67b263005a77be316e2b
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48723
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add enable acp_i2s_use_external_48mhz_osc flag and then
WWAN sku will use external clock source at next build.
BUG=b:174121847
BRANCH=zork
TEST=build vilboz and check MISC_CLK_CNTL1.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ida747938373f648524b1e7f34bc69e372a69c4f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48556
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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gumboz is the dalboz/dirinboz follower.
update gumboz variant to align dirinboz settings.
BUG=b:174277853,b:173662179
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I80c03d531761c02b68bd127d889c3ace2dd9e99e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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from AMD USB phy specialist recommended that TXVREFTUNE0 shouldn't over 0xD (the maximum)
in order to have enough room to accomdate a safe disconnect threshhold in COMPDISTUNE0.
TXVREFTUNE0: 0xf -> 0xd
BUG=b:172687208
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Ia104454d95e5e8d6a212c97fb09d61125945eeea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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1. AGPIO5 to NC
2. EGPIO141 to NC
3. EGPIO144 to NC
BUG=b:174528384
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I51f291476e01982e1a3f92cd1b338a528434112d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48002
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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After checked, this project doesn't need this feature.
BUG=b:173066178
BRANCH=zork
TEST=check no WRDD method in acpi.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9a662953f3047d771f2df919ac80d0440842738e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48621
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This allows factoring out the common initialization for the integrated
UARTs.
Change-Id: I7399a13b9280b732086c6f8e6dfd9f1207d8c8ff
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48508
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove unused code that appears to be left over from grunt.
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Id5bdb1c957342d55c5e6378c503b8d90da050601
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48505
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update telemetry settings.
VDD Slope : 32643 -> 26939
VDD Offset: 208 -> 125
SOC Slope : 22742 -> 20001
SOC Offset: -83 -> 168
BUG=b:171668654
BRANCH=zork
TEST=1. emerge-zork coreboot
2. pass AMD SDLE test report
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ic63e069310aa4a66cd4c9058790dbed37e6967f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48288
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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set APU_EDP_BL_DISABLE(GPIO_85) to low to avoid the VARY_BL fast than
APU_DP_BLON.
BUG=b:171954512
BRANCH=zork
TEST=validate the panel sequence with scope.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ia6d3f4335583bb2d91a6bce96d89cff84247d0ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Use a new driver for the SX9324 proximity detector device.
This is first draft settings, will modify it after fine tuning.
BUG=b:172397658
BRANCH=zork
TEST=run "i2cdump -y -f 0 0x28" and checked all registers are expected.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I869d0b6640247099ca489e96ed94e03811a04bf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47867
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Latest HW schematic add LTE_RST pin to control module power sequence.
BUG=b:173490220
BRANCH=zork
TEST=measure the waveform is meet the LTE module spec.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0f0a35a905d711dd8d17dea2ae82a8dfa1fa05ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This is used as a signal to show the system state. It hadn't been used
up to this point as we're not currently using S0i3, but the fingerprint
sensor will use it to go into a low power mode, so set it appropriately
on Trembyle. Dalboz devices don't use the FPMCU, but set there as well
so that the state matches.
BUG=b:174695987
TEST=Verify GPIO state in S0 and S3 with the EC
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibc725905909830d44f77c2498a26edf6d7a3dc05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48255
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Vincent Palatin <vpalatin@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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At least a part or the remaining definitions in the soc-specific smi.h
files are also common, but those have to be verified more closely.
Change-Id: I5a3858e793331a8d2ec262371fa22abac044fd4a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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